Integration of MRAM into MOL for fast 1T1M cells

Abstract

A memory cell is provided in which a bottom electrode of a magnetoresistive random access memory (MRAM) device is connected to one of the source / drain contact structures of a transistor and a lower contact structure is connected to the other of the source / drain contact structures of the transistor. In this application, the MRAM device and the lower contact structure exist at the middle-of-line (MOL) rather than the back-end-of-line (BEOL), and moreover, the bottom electrode of the MRAM device and a lower portion of the lower contact structure exist in the same dielectric material (i.e., the MOL dielectric material).

Description

TECHNICAL FIELD

[0001] The present invention relates to a memory cell, and more particularly, to a memory cell comprising a transistor (1T) and a magnetoresistive random access memory (MRAM) device and a method of fabricating such a cell. BACKGROUND

[0002] MRAM is a non-volatile random access memory technology in which data is stored by a magnetic storage element. The element is typically formed of two ferromagnetic plates, each of which can hold a magnetization, separated by a thin dielectric layer (i.e., tunnel barrier). One of the two plates is a permanent magnet set to a particular polarity (i.e., magnetic reference layer); the magnetization of the other plate can be changed to match that of an external field used to store the memory (i.e., magnetic free layer). This configuration is referred to as a magnetic tunnel junction (MTJ) pillar.

[0003] In a front-end or neuromorphic computing system, MRAM devices are embedded in a back-end-of-line (BEOL) that is on top of a front-end-of-line (FEOL) that includes one or more transistors. There is a high wiring resistance from the MRAM devices embedded in the BEOL to the transistors present in the FEOL. The high wiring resistance is detrimental to memory speed.

[0004] Therefore, there is a need to provide a memory cell in which MRAM devices are connected to transistors in which the wiring resistance is low. SUMMARY

[0005] A memory cell is provided in which a bottom electrode of a MRAM device is connected to one of the source / drain contact structures of a transistor and a lower contact structure is connected to the other one of the source / drain contact structures of the transistor. In embodiments of the present invention, the MRAM device and the lower contact structure are present in the MOL, rather than in the BEOL as in typical prior art structures. In addition, the bottom electrode of the MRAM device and the lower portion of the lower contact structure are present in the same dielectric material (i.e., MOL dielectric material).

[0006] In one aspect of the application, a memory cell having low wire resistance is provided. In one embodiment of the application, the memory cell includes a FEOL level including a gate structure spanning over a semiconductor fin, with a source / drain structure on each side of the gate structure, and a source / drain contact structure on each source / drain structure. A MOL level is over the FEOL level and includes an MRAM device and a lower contact structure, with a bottom electrode contact of the MRAM device being in one of the source / drain contact structures on one side of the gate structure, and the lower contact structure contacting the other of the source / drain contact structures on the other side of the gate structure. A BEOL level is over the MOL level and includes a first upper contact structure contacting a surface of the lower contact structure, and a second upper contact structure contacting a surface of a top electrode of the MRAM device.

[0007] In another aspect of the application, a method of forming a memory cell having low wire resistance is provided. In one embodiment, the method includes forming a FEOL level including a gate structure spanning over a semiconductor fin, with a source / drain structure on each side of the gate structure, and a source / drain contact structure on each source / drain structure. Next, a dielectric material layer of a MOL level is formed over the FEOL level. A bottom electrode of an MRAM device is then formed in the dielectric material layer and contacts one of the source / drain contact structures on one side of the gate structure. Next, a magnetic tunnel junction (MTJ) pillar and a top electrode of the MRAM device are formed over the bottom electrode. A lower contact structure is then formed contacting the other of the source / drain contact structures on the other side of the gate structure, with a lower portion of the lower contact structure embedded in the dielectric material layer. Next, a back end of line (BEOL) level is formed over the MOL level and includes a first upper contact structure contacting a surface of the lower contact structure, and a second upper contact structure contacting a surface of the top electrode of the MRAM device. BRIEF DESCRIPTION OF DRAWINGS

[0008] FIG. 1A is a diagram showing various cross sections to be described herein; X-X is a cross section along a length direction of a semiconductor fin, Y-Y is a cross section perpendicular to and between an adjacent pair of semiconductor fins and in one of the source / drain regions.

[0009] FIG. 1Bis an X-X cross-sectional view of an exemplary structure that can be employed in one embodiment of the present application, the exemplary structure including a plurality of semiconductor fins extending upward from a substrate surface, a plurality of gate structures oriented perpendicular to each semiconductor fin and straddling a portion of each semiconductor fin, a source / drain structure located adjacent to each gate structure, and a source / drain contact structure present on each source / drain structure.

[0010] FIG. 1C is FIG. 1B a Y-Y cross-sectional view of the exemplary structure shown.

[0011] FIG. 2A is FIG. 1B an X-X cross-sectional view of the exemplary structure of

[0012] FIG. 2B is FIG. 2A a Y-Y cross-sectional view of the exemplary structure shown.

[0013] FIG. 3A is FIG. 2A an X-X cross-sectional view of the exemplary structure of

[0014] FIG. 3B is FIG. 3A a Y-Y cross-sectional view of the exemplary structure shown.

[0015] FIG. 4A is FIG. 3A an X-X cross-sectional view of the exemplary structure of

[0016] FIG. 4B is FIG. 4A a Y-Y cross-sectional view of the exemplary structure shown.

[0017] FIG. 5A is FIG. 4A an X-X cross-sectional view of the exemplary structure of

[0018] FIG. 5B is FIG. 5A a Y-Y cross-sectional view of the exemplary structure shown.

[0019] FIG. 6A isFIG. 5A The exemplary structure is shown in the XX cross-sectional view, where the organic planarization layer has a contact opening formed therein, which physically exposes the surface of another of the source / drain contact structures of the first gate structure.

[0020] FIG. 6B yes FIG. 6A A cross-sectional view of the exemplary structure shown.

[0021] FIG. 7A After removing OPL FIG. 6A A cross-sectional view of an exemplary structure.

[0022] FIG. 7B yes FIG. 7A A cross-sectional view of the exemplary structure shown in the figure.

[0023] FIG. 8A After the formation of the conductive metal-containing layer and the contact metal-containing layer FIG. 7A A cross-sectional view of an exemplary structure.

[0024] FIG. 8B yes FIG. 8A A cross-sectional view of the exemplary structure shown.

[0025] FIG. 9A After both the contact metal layer and the conductive metal layer are recessed. FIG. 8A A cross-sectional view of an exemplary structure.

[0026] FIG. 9B yes FIG. 9A A cross-sectional view of the exemplary structure shown.

[0027] FIG. 10A After forming a hard mask cap on the recessed contact metal layer and the recessed conductive metal layer. FIG. 9A A cross-sectional view of an exemplary structure.

[0028] FIG. 10B yes FIG. 10A A cross-sectional view of the exemplary structure shown.

[0029] FIG. 11A and FIG. 11B This is done after forming another OPL, then patterning another OPL existing in the source / drain region, a hard mask, a recessed contact metallized layer, and a recessed conductive metallized layer. FIG. 10A Cross-sectional view of exemplary structure P201903090US01.

[0030] FIG. 12Ais after removal of another OPL FIG. 11A is a cross-sectional view of the exemplary structure shown in FIG. 3B.

[0031] FIG. 12B is a cross-sectional view of the exemplary structure shown in FIG. 3B. FIG. 12A is a cross-sectional view of the exemplary structure shown in FIG. 3B.

[0032] FIG. 13A is a cross-sectional view of the exemplary structure shown in FIG. 3B. FIG. 12A is a cross-sectional view of the exemplary structure shown in FIG. 3B.

[0033] FIG. 13B is a cross-sectional view of the exemplary structure shown in FIG. 3B. FIG. 13A is a cross-sectional view of the exemplary structure shown in FIG. 3B.

[0034] FIG. 14A is a cross-sectional view of the exemplary structure shown in FIG. 3B. FIG. 13A is a cross-sectional view of the exemplary structure shown in FIG. 3B.

[0035] FIG. 14B is a cross-sectional view of the exemplary structure shown in FIG. 3B. FIG. 14A is a cross-sectional view of the exemplary structure shown in FIG. 3B.DETAILED DESCRIPTION

[0036] Embodiments of the present application will now be described in greater detail below with reference to the following discussion and drawings. It is to be understood that the drawings are designed solely for purposes of illustration and are not in accordance with the scale of the regions depicted. It should also be noted that like and corresponding elements are denoted by like reference numerals throughout the drawings.

[0037] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of various embodiments of the present application. It will be appreciated, however, by those having ordinary skill in the art that the various embodiments of the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known structures or process steps have been omitted in order to avoid obscuring the application.

[0038] It is to be understood that when an element such as a layer, region or substrate is referred to as being "on" or "above" another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly on" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "below" or "under" another element, it can be directly below or under the other element, or intervening elements can also be present. In contrast, when an element is referred to as being "directly below" or "directly under" another element, there are no intervening elements present.

[0039] One solution to the problems mentioned in the Background section is to move the MRAM device to the MOL, which is located between the FEOL and the BEOL. This solution is not easily implemented and can cause different problems than the ones described above. For example, ion beam etching used to form the MTJ pillar of the MRAM device can damage the gate structures and / or the source / drain contact structures. Also, a thick FEOL dielectric material is typically needed, which will significantly increase the height of the source / drain contact structures, which in turn provides an undesirably high source / drain contact resistance. One embodiment of the present invention provides a memory cell in which the bottom electrode of the MRAM device is connected to one of the source / drain contact structures of the transistor and the lower contact structure is connected to the other one of the source / drain contact structures of the transistor. In the memory cell of the present invention, both the MRAM device and the lower contact structure are present in the MOL. Also, in the memory cell of the present invention, the bottom electrode of the MRAM device and the lower portion of the lower contact structure are present in the same dielectric material, i.e., the MOL dielectric material.

[0040] Before describing the present invention in detail, first a reference is made to FIG. 1A which is a diagram showing various cross-sections that will be described. In FIG. 1A , element 16 refers to a gate structure, element 12 refers to a semiconductor fin, and element 26 refers to a source / drain contact structure. As shown, the gate structure 16 is oriented perpendicular to the semiconductor fin 12, and for the middle gate structure 16, the source / drain contact structure 26 is located on each side of the gate structure 16. In FIG. 1A , X-X is a cross-section along the longitudinal direction of one of the semiconductor fins 12, and Y-Y is a cross-section perpendicular to and between an adjacent pair of semiconductor fins and in one of the source / drain regions. As known to those skilled in the art, a first source / drain region is located on one side (i.e., a first side) of the gate structure, and a second source / drain region is located on the other side (i.e., a second side) of the gate structure, wherein the first side is opposite the second side.

[0041] Reference is now made to FIG. 1B-1C , which shows an exemplary structure that can be used in one embodiment of the present invention. FIG. 1B-1C The exemplary structure shown in

[0042] As shown in FIG. 1BAs shown, a gate cap 20 can be present on each gate structure 16, and a gate spacer 18 can be present on the sidewalls of each gate structure 16, and if present, on each gate cap 20. As FIG. 1C As shown, in some embodiments of the present application, the source / drain structures 24 located between each gate structure 16 can be merged. Also, as shown, the FEOL dielectric material 22 can be positioned laterally adjacent to the source / drain structures 24 and the source / drain contact structures 26, which in the embodiment shown are merged. FIG. 1C As shown, the trench isolation structure 14 can be present laterally adjacent to each semiconductor fin 12, and the FEOL dielectric material 22 can be positioned laterally adjacent to the source / drain structures 24 and the source / drain contact structures 26, which in the embodiment shown are merged.

[0043] FIG. 1B-1C The exemplary structures shown can be formed using processes known to those skilled in the art. For example, a gate-first process or a gate-last process can be used to form the exemplary structures shown in FIGS. 1-3. FIG. 1B-1C Details regarding the processes used to form the exemplary structures shown in FIGS. 1-3 are not provided so as not to obscure the method of the present application. FIG. 1B-1C Details regarding the processes used to form the exemplary structures shown in FIGS. 1-3 are not provided so as not to obscure the method of the present application.

[0044] In some embodiments of the present application, the substrate 10 can be composed of a semiconductor material having semiconductor properties. Exemplary semiconductor materials that can be used as the substrate 10 include, but are not limited to, silicon (Si), germanium (Ge), silicon-germanium alloys (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), a III-V compound semiconductor, or a II-VI compound semiconductor. A III-V compound semiconductor is a material that includes at least one element from Group III of the periodic table and at least one element from Group V of the periodic table. A II-VI compound semiconductor is a material that includes at least one element from Group II of the periodic table and at least one element from Group VI of the periodic table.

[0045] In other embodiments of the present application, the substrate 10 can be composed of an insulator, such as silicon dioxide or boron nitride. In such embodiments, an operational substrate (not shown) can be located beneath the insulator that provides the substrate 10.

[0046] The semiconductor fins 12 are composed of a semiconductor material as defined above for the substrate 10. In some embodiments, the semiconductor fins 12 are composed of the same semiconductor material as the substrate 10 in composition. In other embodiments, the semiconductor fins 12 are composed of a different semiconductor material than the substrate 10 in composition.

[0047] As used herein, a "semiconductor fin" refers to a semiconductor material that includes a pair of vertical sidewalls that are parallel to each other. As used herein, a surface is "vertical" if there exists a vertical plane that is offset from the surface by no more than three times the root-mean-square roughness of the surface. In one embodiment, each semiconductor fin 12 has a height from 20 nm to 200 nm, a width from 5 nm to 30 nm, and a length from 20 nm to 50 pm. Other heights and / or widths and / or lengths less than or greater than the ranges mentioned herein can also be used in the present application. Each semiconductor fin 12 is spaced apart from its nearest neighboring semiconductor fin 12 by a pitch from 20 nm to 100 nm; the pitch is measured from a point on one semiconductor fin to an exact point on the neighboring semiconductor fin. Furthermore, each semiconductor fin 12 is oriented parallel to each other. An opening or gap exists between each adjacent pair of semiconductor fins 12.

[0048] The semiconductor fins 12 can be formed by patterning an upper semiconductor material portion of a base semiconductor substrate. Such patterning can include, for example, photolithography and etching, or a sidewall image transfer (SIT) process. The base semiconductor substrate can be a bulk semiconductor substrate (i.e., a substrate composed entirely of at least one semiconductor material) or a semiconductor-on-insulator (SOI) substrate composed of a top semiconductor material layer, an insulator material, and a handle substrate. When a SOI substrate is used as the base semiconductor substrate, the top semiconductor material layer is patterned to provide the semiconductor fins 12 that extend upward from the insulator material of the SOI substrate.

[0049] The trench isolation structures 14 can be composed of a trench dielectric material, such as silicon dioxide. The trench isolation structures 14 can be formed by depositing a trench dielectric material within the gaps that exist between each semiconductor fin 12, and then performing an etch-back process on the deposited trench dielectric material. In some embodiments, the formation of the trench isolation structures 14 can be omitted.

[0050] Each gate structure 16 includes a gate dielectric material layer, not shown, and a gate conductor layer, also not shown. Each gate structure 16 forms a component of a transistor. In some embodiments, the gate dielectric material layer is entirely beneath the gate conductor layer. In other embodiments, the gate dielectric material layer is present on sidewalls and a bottom wall of the gate conductor layer.

[0051] The gate dielectric material layer can be composed of a gate dielectric material, such as an oxide, a nitride, and / or an oxynitride. In one example, the gate dielectric material that provides the gate dielectric material layer can be a high-k material having a dielectric constant greater than 4.0; all dielectric constants are measured in a vacuum unless stated to the contrary. Exemplary high-k dielectrics include, but are not limited to, Hf02, Zr02, La203, Al203, Ti02, SrTi03, LaAl03, Y203, HfO2x N y , ZrO x N y , La2O x N y , Al2O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y2O x N y , SiON, SiNx, silicates thereof, and alloys thereof. Each value of x is independently from 0.5 to 3, and each value of y is independently from 0 to 2. In some embodiments, a multi-layer gate dielectric structure including different gate dielectric materials (e.g., silicon dioxide) and high-k gate dielectrics can be formed and used as the gate dielectric material layer. The gate dielectric material layer can be formed from any deposition process including, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition (ALD). In one embodiment of the present application, the gate dielectric material providing the gate dielectric material layer can have a thickness in the range from 1 nm to 10 nm. Other thicknesses less than or greater than the above thickness range can also be used for the gate dielectric material layer.

[0052] The gate conductor layer can be composed of a gate conductor material. The gate conductor material used to provide the gate conductor layer can include any conductive material including, for example, doped polysilicon, elemental metals (e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium, and platinum), alloys of at least two elemental metals, elemental metal nitrides (e.g., tungsten nitride, aluminum nitride, and titanium nitride), elemental metal silicides (e.g., tungsten silicide, nickel silicide, and titanium silicide), or multi-layer combinations thereof. The gate conductor layer can be formed by any deposition process including, for example, CVD, PECVD, PVD, sputtering, or ALD. The gate conductor layer can have a thickness from 25 nm to 150 nm; although other thicknesses can also be used as the thickness of the gate conductor layer.

[0053] When present, the gate cap 20 is composed of a cap gate material, such as silicon dioxide, silicon nitride, or silicon oxynitride. The gate cap 20 can be formed using a deposition process such as CVD, PECVD, PVD, sputtering, or ALD. The gate cap 20 can have a thickness from 10 nm to 50 nm; although other thicknesses can also be used as the thickness of the gate cap 20.

[0054] The gate spacers 18 can be composed of a gate spacer dielectric material, such as silicon dioxide, silicon nitride, or silicon oxynitride. The gate spacers 18 can be composed of a gate spacer material that is the same in composition as the gate cap material that provides the gate cap 20 or different in composition from the gate cap material that provides the gate cap 20. The gate spacers 18 can be formed by a deposition process followed by a spacer etch.

[0055] The FEOL dielectric material 22 is composed of any dielectric material, such as silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. As used herein, the term "low-k" means a dielectric material having a dielectric constant less than 4.0. In another embodiment, a self-planarizing material, such as a spin-on glass (SOG) or a spin-on low-k dielectric material, such as SiLK® TM , can be used as the FEOL dielectric material 22. The FEOL dielectric material 22 can be formed using a deposition process, including, for example, CVD, PECVD, evaporation, or spin-on.

[0056] The source / drain structure 24 that is epitaxially grown from the exposed surface of the semiconductor fin 12 is composed of a semiconductor material and a dopant as defined above. The semiconductor material that provides the source / drain structure 24 can be the same in composition as the semiconductor material that provides the semiconductor fin 12 or different in composition from the semiconductor material that provides the semiconductor fin 12. The source / drain structure 24 can have at least one faceted surface.

[0057] The dopant that is present in the source / drain structure 24 can be a p-type dopant or an n-type dopant. The term "p-type" refers to the addition of an impurity to an intrinsic semiconductor that creates a deficiency of valence electrons. In silicon-containing semiconductor materials, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium, and indium. "N-type" refers to the addition of an impurity to an intrinsic semiconductor that contributes a free electron. In silicon-containing semiconductor materials, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic, and phosphorus. In one embodiment of the present invention, the concentration of n-type or p-type dopant within the source / drain structure 24 can range from 1 x 1018atoms / cm3to 1 x 1021atoms / cm3, although dopant concentrations greater than 1 x 1021atoms / cm3or less than 1 x 1018atoms / cm3are also contemplated. 18 3 to 1 x 1021atoms / cm3, although dopant concentrations greater than 1 x 1021atoms / cm3or less than 1 x 1018atoms / cm3are also contemplated. 21 3 to 1 x 1021atoms / cm3, although dopant concentrations greater than 1 x 1021atoms / cm3or less than 1 x 1018atoms / cm3are also contemplated. 21 3 to 1 x 1021atoms / cm3, although dopant concentrations greater than 1 x 1021atoms / cm3or less than 1 x 1018atoms / cm3are also contemplated. 18 3 to 1 x 1021atoms / cm3, although dopant concentrations greater than 1 x 1021atoms / cm3or less than 1 x 1018atoms / cm3are also contemplated.

[0058] ​​​​The source / drain contact structure 26 is typically made of a metal silicide, such as tungsten silicide, nickel silicide, or platinum silicide. The metal silicide can be formed using conventional metal-semiconductor alloy forming processes. The source / drain contact structure 26 may have a top surface coplanar with the top surface of the FEOL dielectric material 22. Besides the metal silicide, the source / drain contact structure 26 may be made of a contact metal or a contact metal alloy. Contact metals include copper, aluminum, tungsten, or cobalt. The contact metal or contact metal alloy providing the source / drain contact structure 26 can be formed by deposition processes such as CVD, PECVD, PVD, sputtering, or electroplating.

[0059] Now for reference FIG. 2A-2B This illustrates the first gate structure (i.e., the one forming multiple gate structures 16) in the formation of contacts. FIG. 2A The bottom electrode 30 is one of the source / drain contact structures 26 of the intermediate gate structure shown. FIG. 1B-1C An exemplary structure is shown, in which the bottom electrode 30 is embedded in the dielectric material layer 28. Although the formation of a single bottom electrode 30 is described and illustrated in this document, multiple bottom electrodes 30 may also be formed, each contacting one of the source / drain contact structures 26 of a particular gate structure 16.

[0060] The dielectric material layer 28 is composed of MOL dielectric materials, such as silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borosilicate glass (BPSG), spin-coated low-k dielectric layer, chemical vapor deposition (CVD) low-k dielectric layer, as defined above, or any combination thereof. In another embodiment, a self-planarizing material such as spin-coated glass (SOG) or such as SiLK... TM Spin-coated low-k dielectric materials can be used as MOL dielectric materials. Using a self-planarizing dielectric material as dielectric material layer 28 avoids the need for subsequent planarization steps. In one embodiment, dielectric material layer 28 can be formed using deposition processes including, for example, CVD, PECVD, evaporation, or spin-coating. In some embodiments, planarization processes (e.g., chemical mechanical polishing (CMP) or grinding) and / or etch-back processes are performed after the deposition of dielectric material layer 28. Dielectric material layer 28 may be compositionally the same as or different from FEOL dielectric material 22. Dielectric material layer 28 has sufficient thickness to prevent damage to gate structure 16 and / or source / drain contact structure 26 during subsequent formation of MTJ pillars. In one example, dielectric material layer 28 has a thickness from 20 nm to 100 nm.

[0061] After forming the dielectric material layer 28, openings are formed in the dielectric material layer 28 to physically expose the first gate structure of the plurality of gate structures 16 (i.e., FIG. 2Athe surface of one of the source / drain contact structures 26 associated with one of the gate structures (i.e., the intermediate gate structure) of the plurality of gate structures 16 shown in FIG. 1. The opening can be formed by photolithography and etching. The opening has a critical dimension (CD) that is smaller than the underlying source / drain contact structure 26. In addition, the opening formed into the dielectric material layer 28 physically exposes the surface of one of the source / drain contact structures 26 associated with one of the gate structures (i.e., the intermediate gate structure) of the plurality of gate structures 16 shown in FIG. 1. FIG. 2A the surface of one of the source / drain contact structures 26 associated with one of the gate structures (i.e., the intermediate gate structure) of the plurality of gate structures 16 shown in FIG. 1.

[0062] A bottom electrode 30 is then formed in the opening present in the dielectric material layer 28. The bottom electrode 30 can be composed of a conductive material, such as Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN, or any combination thereof. The bottom electrode 30 can be formed by a deposition process, such as sputtering, CVD, or PECVD. After the conductive material providing the bottom electrode 30 is deposited, a planarization process, such as CMP or polishing, can be performed.

[0063] Reference is now made to FIG. 3A-3B , which shows an exemplary structure of FIG. 2A-2B after forming a multilayer magnetic tunnel junction (MTJ) material stack 32 on the dielectric material layer 28 and the embedded bottom electrode 30, and forming a top electrode layer 42 on the MTJ material stack 32. In some embodiments and as shown in FIG. 3A-3B , a hard mask layer 44 can be formed on the top electrode layer 42.

[0064] The MTJ material stack 32 includes at least a magnetic pinned layer, a tunnel barrier layer, and a magnetic free layer. In some embodiments and as shown in FIG. 3A to 3B , the MTJ material stack 32 is a bottom pinned MTJ material stack that includes, from bottom to top, a magnetic pinned layer 36, a tunnel barrier layer 38, and a magnetic free layer 40. In addition, an optional metal seed layer 34 can also be present in the bottom pinned MTJ material stack. The bottom pinned MTJ material stack can include a non-magnetic spacer layer (not shown) on the magnetic free layer 40, a second magnetic free layer (not shown) on the non-magnetic spacer layer, and / or an MTJ cap layer (not shown) on the magnetic free layer 40 or the second magnetic free layer.

[0065] In other embodiments (not shown), the MTJ stack is a top pinned MTJ material stack that includes, from bottom to top, a magnetic free layer, a tunnel barrier layer, and a magnetic pinned layer; in this embodiment, the order of elements 36 and 40 is reversed from FIG. 3A-3BIn contrast to the embodiment shown in FIG. 1, the top pinned MTJ material stack in this embodiment can also include an optional metal seed layer below the magnetic free layer, a non-magnetic spacer layer on the magnetic free layer, a second magnetic free layer on the non-magnetic spacer layer, and / or an MTJ cap layer on the magnetic pinned layer.

[0066] The various material layers of the MTJ material stack 32 can be formed by utilizing one or more deposition processes, such as sputtering, plasma enhanced atomic layer deposition (PEALD), PECVD, or PVD.

[0067] The optional metal seed layer 34 can be composed of platinum (Pt), palladium (Pd), nickel (Ni), rhodium (Rh), iridium (Ir), rhenium (Re), or alloys and multilayers thereof. In one example, the optional metal seed layer 34 is composed of platinum (Pt).

[0068] The magnetic pinned layer 36 has a fixed magnetization. The magnetic pinned layer 36 can be composed of a metal or metal alloy (or stack thereof) that includes one or more metals that exhibit high spin polarization. In alternative embodiments, example metals for forming the magnetic pinned layer 36 include iron, nickel, cobalt, chromium, boron, or manganese. Example metal alloys can include the metals of the above examples. In another embodiment, the magnetic pinned layer 36 can be a multilayer arrangement having (1) a high spin polarization region formed from a metal and / or metal alloy that uses the above metals, and (2) a region composed of one or more materials that exhibit strong perpendicular magnetic anisotropy (strong PMA). Example materials that can be used that have strong PMA include metals such as cobalt, nickel, platinum, palladium, iridium, or ruthenium, and can be arranged as alternating layers. The strong PMA region can also include alloys that exhibit strong PMA, example alloys include cobalt-iron-terbium, cobalt-iron-gadolinium, cobalt-chromium-platinum, cobalt-platinum, cobalt-palladium, iron-platinum, and / or iron-palladium. The alloys can be arranged as alternating layers. In one embodiment, a combination of these materials and regions can also be used as the magnetic pinned layer 36.

[0069] The tunnel barrier layer 38 is composed of an insulator material and formed at a thickness that provides an appropriate tunneling resistance. Example materials for the tunnel barrier layer 38 include magnesium oxide, aluminum oxide, and titanium oxide, or higher electrical tunneling conductance materials such as semiconductors or low bandgap insulators.

[0070] The magnetic free layer 40 can be composed of a magnetic material (or stack of magnetic materials) that has a magnetization that can be oriented to change orientation relative to the magnetization of the magnetic pinned layer 36. Example magnetic materials for the magnetic free layer 40 include alloys and / or multilayers of cobalt, iron, cobalt-iron, alloys of nickel, alloys of nickel-iron, and alloys of cobalt-iron-boron.

[0071] If present, the non-magnetic metallic spacer layer is composed of a non-magnetic metal or metal alloy that allows magnetic information to pass therethrough and also allows the two magnetic free layers to magnetically couple together such that in an equilibrium state the first and second magnetic free layers are always parallel. The non-magnetic metallic spacer layer allows spin torque switching between the first and second magnetic free layers.

[0072] If present, the second magnetic free layer can include one of the magnetic materials of the magnetic free layer 40 described above. In one embodiment, the second magnetic free layer is composed of the same magnetic material as the magnetic free layer 40. In another embodiment, the second magnetic free layer is composed of a different magnetic material than the magnetic free layer 40.

[0073] If present, the MTJ cap layer can be composed of Nb, NbN, W, WN, Ta, TaN, Ti, TiN, Ru, Mo, Cr, V, Pd, Pt, Rh, Sc, Al, or other high melting point metal or conductive metal nitride. The MTJ cap layer can have a thickness from 2 nm to 25 nm; other thicknesses are possible and can be used as the thickness of the MTJ cap layer in the present disclosure.

[0074] The top electrode layer 42 can be composed of a conductive material such as Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN, or any combination thereof. The conductive material providing the top electrode layer 42 can be the same or different in composition from the conductive material providing the bottom electrode 30. In one embodiment of the present disclosure, the top electrode layer 42 can have a thickness from 100 nm to 500 nm; although other thicknesses are possible and can be used as the thickness of the top electrode layer 42. The top electrode layer 42 can be formed by a deposition process such as sputtering, PEALD, PECVD, or PVD.

[0075] As described above, a hard mask layer 44 can be formed on the top electrode layer 42. The hard mask layer 44 can be composed of any hard mask material including, for example, silicon dioxide, silicon nitride, and / or silicon oxynitride. The hard mask layer 44 can be formed using a deposition process such as PEALD, PECVD, or PVD. The hard mask layer 44 can have a thickness from 10 nm to 50 nm; although other thicknesses are possible and can be used as the thickness of the hard mask layer 44.

[0076] Referring now to FIG. 4A-4B , an exemplary structure of the FIG. 3A-3B is shown after patterning the top electrode layer 42 and the MTJ stack material 32 to provide a top electrode 42P and an MTJ pillar 32P, respectively, on at least the embedded bottom electrode 30. In embodiments where a hard mask layer 44 is present, the hard mask layer 44 is patterned at this point to provide a hard mask 44P on the top electrode 42P.

[0077] The optional hard mask layer 44, the patterning of the top electrode layer 42, and the MTJ material stack 32 includes an ion beam etching (IBE) process. In some embodiments, as shown in FIG. 4, during this patterning step, the upper portion of the dielectric material layer 28 is removed, i.e., recessed. In such embodiments, a mesa portion 28M of the dielectric material layer 28 is formed. The mesa portion 12M of the dielectric material layer 28 has a topmost surface that is located above the recessed portion of the dielectric material layer 28. In embodiments of the present application, the dielectric material layer 28, including the mesa portion 12M, is thicker than the recessed portion of the dielectric material layer 28. Due to the thickness of the dielectric material layer 28, no damage is caused to the underlying gate structure 16 and / or the source / drain contact structure 26. As shown in FIG. 4, the MTJ pillar 32P is located on the mesa portion 28M of the dielectric material layer 28. FIG. 4A FIG. 4A

[0078] The remaining (i.e., unpatterned) portion of the MTJ material stack 32 provides the MTJ pillar 32P. In one example and as shown in FIG. 4, the MTJ pillar 32P is a bottom pinned MTJ structure that includes, from bottom to top, a metal seed layer portion 34P (i.e., the remaining unetched portion of the metal seed layer 34), a magnetic pinning layer portion 36P (i.e., the remaining unetched portion of the magnetic pinning layer 36), a tunnel barrier layer portion 38P (i.e., the remaining unetched portion of the tunnel barrier layer 38), and a magnetic free layer portion 40P (i.e., the remaining unetched portion of the magnetic free layer 40). In another example (not shown), the MTJ pillar 32P is a top pinned MTJ structure that includes, from bottom to top, the magnetic free layer portion 40P, the tunnel barrier layer portion 38P, and the magnetic pinning layer portion 36P. In either embodiment (bottom pinned MTJ structure or top pinned MTJ structure), the MTJ pillar 32P can include the remaining portion of any other layers present in the MTJ material stack 32. FIG. 4A The shape of the MTJ pillar 32P, the top electrode 42P, and the hard mask 44P (if present) can be cylindrical; although other asymmetric shapes are possible and can be used as the shape of the MTJ pillar 32P, the top electrode 42P, and the hard mask 44P (if present) in embodiments of the present application. To avoid unwanted resputtering of metal particles of the bottom electrode 30 on the sidewalls of the MTJ pillar 32P, the CD of the MTJ pillar 32P, the top electrode 42P, and (if present) the hard mask 44P is equal to or greater than the CD of the bottom electrode 30.

[0079]

[0080] ​​​Typically, the MTJ pillar 32P, the top electrode 42P, and (if present) the hard mask 44P have outermost sidewalls that are vertically aligned with one another. In embodiments in which the mesa portion 28M of the dielectric material layer 28 is formed, the MTJ pillar 32P, the top electrode 42P, and (if present) the hard mask 44P have outermost sidewalls that are vertically aligned with the outermost sidewalls of the mesa portion 28M of the dielectric material layer 28.

[0081] Referring now to FIG. 5A-5B , an exemplary structure of FIG. 4A-4B is shown after formation of a dielectric material spacer 46 that laterally adjoins the MTJ pillar 32P, the top electrode 42P, and the hard mask 44P (if present). The dielectric material spacer 46 encapsulates and surrounds the MTJ pillar 32P, the top electrode 42P, and the hard mask 44P (if present). In some embodiments, as shown in FIG. 5A , a lower portion of the dielectric material spacer 46 is present along the sidewalls of the mesa portion 28M of the dielectric material layer 28. In such embodiments, the mesa portion 28M of the dielectric material layer 28 is encapsulated and surrounded by the lower portion of the dielectric material spacer 46.

[0082] The dielectric material spacer 46 is composed of a dielectric material that is different in composition from the dielectric material layer 28 and the hard mask layer 44. The dielectric material that provides the dielectric material spacer 46 can provide passivation of the MTJ pillar 32P and the top electrode 42P. In one embodiment, the dielectric material spacer 46 is composed of silicon nitride. In another embodiment, the dielectric material spacer 46 can be composed of a dielectric material that contains silicon, carbon, and hydrogen atoms. In some embodiments, in addition to carbon and hydrogen atoms, the dielectric material spacer 46 can include atoms of at least one of nitrogen and oxygen. In other embodiments, in addition to silicon, nitrogen, carbon, and hydrogen atoms, the dielectric material spacer 46 can include boron atoms. In one example, the dielectric material spacer 46 can be composed of an nBLOK dielectric material that includes silicon, carbon, hydrogen, nitrogen, and oxygen atoms. In an alternative example, the dielectric material spacer 46 can be composed of a SiBCN dielectric material that includes silicon, boron, carbon, hydrogen, and nitrogen atoms.

[0083] The dielectric material spacer 46 can be formed by deposition, e.g., CVD or PECVD, followed by spacer etching, e.g., reactive ion etching (RIE). The dielectric material spacer 46 can have a topmost surface that is coplanar with the topmost surface of the hard mask 44P or the topmost surface of the top electrode 42P (if the hard mask 44P is omitted).

[0084] Referring now to FIG. 6A-6B , an exemplary structure of FIG. 5A-5BAn exemplary structure, wherein the organic planarization layer has a contact opening 52 formed therein, the contact opening physically exposing the first gate structure (i.e., FIG. 6A The surface of another of the source / drain contact structures 26 in the intermediate gate structure shown. In an embodiment of the invention, the bottom electrode 30 contacts the source / drain contact structure 26 located on one side of the gate structure 16, and the contact opening 52 physically exposes the source / drain contact structures 26 located on opposite sides of the same gate structure 16.

[0085] OPL 50 may be composed of an organic polymer, which may include polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). OPL may be formed using deposition processes such as CVD, PECVD, or spin coating. OPL 50 has a height extending above the top surface of the hard mask 44P, or, if the hard mask 44P is omitted, a height extending above the top surface of the top electrode 42P.

[0086] Contact opening 52 can be formed by photolithography and etching. Due to the difference in etching selectivity between OPL 50 and dielectric material layer 28, the contact opening 52 present in dielectric material layer 28 can have tapered sidewalls (i.e., inwardly tapering sidewalls measured from top to bottom), such as... FIG. 6A and 6B As shown. In some embodiments, the contact opening 52 is located in a recessed portion of the dielectric material layer 28, which is laterally adjacent to the mesa portion 28M of the dielectric material layer 28 into which the bottom electrode 30 is embedded.

[0087] Now for reference FIG. 7A-7B This shows the effect after removing OPL 50. FIG. 6A-6B An exemplary structure. The OPL layer 50 can be removed using any material removal process, such as ashing.

[0088] Now for reference FIG. 8A-8B This shows the process after the formation of the conductive metal-containing layer 54 and the contact metal-containing layer 56. FIG. 7A-7B An exemplary structure. In some embodiments, the conductive metal layer 54 may be omitted.

[0089] The conductive metal layer 54 is formed in FIG. 7A to FIG. 7BThe exemplary structure shown comprises continuous layers on all exposed surfaces, including contact openings 52 formed in the dielectric material layer 28. The conductive metal-containing layer 54 is composed of a conductive liner material, such as Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, or WN. In some embodiments, the conductive metal-containing layer 54 may comprise a material stack of the conductive liner material. In one example, the conductive liner material may be composed of a stack of Ta / TaN. The conductive metal-containing layer 54 may be formed using deposition processes such as CVD, PECVD, PVD, or sputtering. The conductive metal-containing layer 54 may have a thickness from 1 nm to 15 nm; although other thicknesses of the conductive metal-containing layer 54 are also possible and may be used as such in embodiments of the invention.

[0090] The contact metal-containing layer 56 comprises any contact metal or contact metal alloy that is albeit etch-friendly. Examples of such albeit etch-friendly materials include, but are not limited to, ruthenium (Ru), aluminum (Al), or palladium (Pd). Typically, the composition of the contact metal-containing layer 56 differs from that of the conductive metal-containing layer 54, and the contact metal-containing layer 56 can be formed using deposition processes such as CVD, PECVD, electroplating, or sputtering. The contact metal-containing layer 56 is a continuous layer present throughout the conductive metal-containing layer 54. In embodiments where the conductive metal-containing layer 54 is omitted, the contact metal-containing layer 56 is formed on... FIG. 7A-7B The exemplary structure shown comprises continuous layers on all physically exposed surfaces, including contact openings 52 formed in the dielectric material layer 28. As shown, the lower portion of the contact metal-containing layer 56 exists within the contact openings 52 present in the dielectric material layer 28, and also includes the bottom electrode 30. The lower portion of the contact metal-containing layer 56 present in the contact openings 52 may have inwardly tapered sidewalls as described above.

[0091] Now for reference FIG. 9A-9B This shows the result after the contact metal-containing layer 56 and the conductive metal-containing layer 54 are recessed. FIG. 8A-8B An exemplary structure; if the conductive metal-containing layer 54 is omitted, only the contact metal-containing layer 56 is recessed. Recessing may include first planarizing the contact metal-containing layer 56, and then performing a recess etching. The remaining contact metal-containing layer 56 may be referred to as the recessed contact metal-containing layer 56R, and the remaining conductive metal-containing layer 54 may be referred to as the recessed conductive metal-containing layer 54R. The recessed contact metal-containing layer 56R and the recessed conductive metal-containing layer 54R have top surfaces that are coplanar with each other. The top surfaces of the recessed contact metal-containing layer 56R and the recessed conductive metal-containing layer 45R are located below at least the top surface of the top electrode 42P.

[0092] Now for reference FIG. 10A-10B, showing the exemplary structure after forming a hard mask cap 58 over the recessed contact metal-containing layer 56R and the recessed conductive metal-containing layer 54R, following FIG. 9A-9B . The hard mask cap 58 comprises any hard mask material and is compositionally different from the hard mask 44P and the dielectric material spacer 46 present on the top electrode 42P. The hard mask cap 58 can be formed by a deposition process followed by a planarization process, such as CMP. The hard mask cap 58 has a topmost surface that is generally coplanar with the topmost surface of the dielectric material spacer 46.

[0093] Reference is now made to FIG. 11A-11B , showing the exemplary structure after forming another OPL 60P, and then patterning the another OPL 60P present in the source / drain region, the hard mask 58, the recessed contact metal-containing layer 56R, and the recessed conductive metal-containing layer 54R (i.e., along the cross-section Y-Y as shown in FIG. 11B . FIG. 10A-10B The another OPL 60P can be composed of one of the materials described above for the OPL 50, and the OPL 60P can be formed using one of the deposition processes described above for forming the OPL 50.

[0094] The patterning can be performed by photolithography and etching. Each remaining (i.e., unetched) portion of the hard mask 58 can be referred to as a patterned hard mask cap 58P, each remaining (i.e., unetched) portion of the recessed contact metal-containing layer 56R can be referred to as a lower contact structure 56S, and each remaining (i.e., unetched) portion of the recessed conductive metal-containing layer 54R can be referred to herein as a conductive metal-containing liner 54L. In FIG. 12B , the lower contact structure 56S that is not present in the contact opening 52 present in the dielectric material layer 28 represents a dummy structure and is not used for electrical connection. As can be seen in FIG. 12B , the patterned structure comprising the patterned hard mask cap 58P and the lower contact structure 56S can have tapered sidewalls (in this case, the tapering is outward from the top to the bottom).

[0095] In FIG. 11A , the lower portion of the lower contact structure 56S present in the contact opening 52 and the entire bottom electrode 30 are located in the dielectric material layer 28. In particular, the bottom electrode 30 is entirely located in the dielectric material layer 28 including the mesa portion 28M, while the lower portion of the lower contact structure 56S present in the contact opening 52 is entirely located in the recessed portion of the dielectric material layer 38; the dielectric material layer 28 including the mesa portion 28M has a height (i.e., a vertical thickness) that is greater than the height of the recessed portion of the dielectric material layer 28.

[0096] Reference is now made to FIG. 12A-1B , showing the exemplary structure after removing the another OPL 60P. FIG. 11A-11BThe exemplary structure is shown. Another OPL 60P can be removed using any material removal process, such as ashing.

[0097] Now for reference FIG. 13A-13B This shows the process after forming and planarizing the low-k dielectric filler material 62. FIG. 12A-12B The exemplary structure is described above. The term "low-k" has the meaning defined above, i.e., a dielectric material having a dielectric constant of less than 4. In some embodiments, the low-k dielectric filler 62 comprises a Si-based dielectric material. The Si-based dielectric material may be silicon dioxide-based (e.g., SiOCH) or silsesquioxane (SSQ)-based (e.g., hydrogen-SSQ or methyl-SSQ). Other low-k dielectrics, such as non-silicon-based dielectric materials (i.e., polymers or amorphous carbon), may be used as the low-k dielectric filler 62. The low-k dielectric filler 62 may be formed using a deposition process, such as CVD, PECVD, or spin coating. Planarization of the deposited low-k dielectric filler 62 may be performed by CMP or grinding. After planarization, the low-k dielectric filler 62 has a top surface coplanar with the top surface of each patterned hard mask cap 58P. The dielectric filler 62 and the dielectric material layer 28 are present in the MOL.

[0098] Now for reference FIG. 14A-14B This illustrates the process after forming a BEOL dielectric material layer 64 having upper contact structures (66X, 66Y) formed therein. FIG. 13A-13B The exemplary structure is shown below. The BEOL dielectric material layer 64 may include one of the dielectric materials described above for the dielectric material layer 28. The BEOL dielectric material layer 64 may be formed using a deposition process, such as CVD, PECVD, or spin coating.

[0099] The upper contact structure (66X, 66Y) is formed by creating a pair of contact openings within the BEOL dielectric material layer 64. One contact opening extends to the surface of the lower contact structure 56S of the contact source / drain structure 26, while the other contact opening extends to the surface of the top electrode 44P. The pair of contact openings can be formed by photolithography and etching. Each contact opening is then filled with a contact metal or a contact metal alloy. Exemplary contact metals include copper, aluminum, or tungsten. An exemplary contact metal alloy is a copper-aluminum alloy.

[0100] As shown in the figure, the first upper contact structure 66X contacts the surface of the lower contact structure 56S, which in turn contacts the surface of one of the source / drain contact structures 26, while the second upper contact structure 66Y contacts the surface of the top electrode 42P located on the MTJ pillar 32P.

[0101] FIG. 14A-14BA memory cell (i.e., 1T1M) according to the present application is shown. The memory cell includes a FEOL that includes a gate structure (middle gate structure 16) straddling over a semiconductor fin 12 with a source / drain structure 24 on each side of the gate structure 16 and a source / drain contact structure 26 on each source / drain structure 24. A MOL level is over the FEOL level and includes an MRAM device (including a bottom electrode 30, an MTJ pillar 32P, and a top electrode 42P) and a lower contact structure 56S, with the bottom electrode 30 of the MRAM device contacting one of the source / drain contact structures (i.e., the source / drain contact structure 26 on the right side of the middle gate structure 16) on one side of the gate structure 16 and the lower contact structure 56S contacting another one of the source / drain contact structures (i.e., the source / drain contact structure 26 on the left side of the middle gate structure 16) on the other side of the gate structure 16. A BEOL level is over the MOL level and includes a first upper contact structure 66X that contacts a surface of the lower contact structure 56S, and a second upper contact structure 66Y that contacts a surface of the top electrode 42P of the MRAM device. Such a memory cell has low wiring resistance, and thus has fast storage speed.

[0102] While the application has been particularly shown and described with reference to particular embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the scope of the application. Accordingly, the disclosed application is not limited to the exact forms and details as described and illustrated, but falls within the scope of the appended claims.

Claims

1. A memory cell, comprising: a front-end-of-line (FEOL) level including a gate structure spanning over a semiconductor fin, with a source / drain structure on each side of the gate structure, and a source / drain contact structure on each source / drain structure; a middle-of-line (MOL) level over the FEOL and including a magnetoresistive random access memory (MRAM) device and a lower contact structure, with a bottom electrode contact of the MRAM device in one of the source / drain contact structures on one side of the gate structure, the lower contact structure contacting another of the source / drain contact structures on another side of the gate structure, and a lower portion of the bottom electrode of the magnetoresistive random access memory device and the lower contact structure existing in a same dielectric material; and a back-end-of-line (BEOL) level over the MOL level and including a first upper contact structure contacting a surface of the lower contact structure and a second upper contact structure contacting a surface of a top electrode of the MRAM device.

2. The memory cell of claim 1, wherein the MOL level includes a layer of dielectric material having a mesa portion and a recessed portion, and wherein a lower portion of the lower contact structure is embedded in the recessed portion of the layer of dielectric material and the bottom electrode is embedded in a region of the layer of dielectric material including the mesa portion.

3. The memory cell of claim 2, wherein the MRAM device further includes a magnetic tunnel junction (MTJ) pillar contacting the bottom electrode, with the MTJ pillar on the mesa portion of the layer of dielectric material.

4. The memory cell of claim 3, further including a dielectric material spacer encapsulating and surrounding the MTJ pillar and the top electrode, with a portion of the dielectric material spacer contacting a sidewall of the mesa portion of the layer of dielectric material.

5. The memory cell of claim 3, wherein the MTJ pillar is a bottom pinned MTJ structure.

6. The memory cell of claim 3, wherein the MTJ pillar is a top pinned MTJ structure.

7. The memory cell of claim 1, further including a conductive metal- containing liner between the lower contact structure and another source / drain structure on the other side of the gate structure, with the conductive metal-containing liner having a topmost surface that is coplanar with a topmost surface of the lower contact structure.

8. The memory cell of claim 7, wherein the topmost surface of the conductive metal-containing liner is below a topmost surface of a top electrode of the MRAM device.

9. The memory cell of claim 1, wherein a lower portion of the lower contact structure has tapered sidewalls.

10. The memory cell of claim 1, wherein the first upper contact structure and the second upper contact structure are partially in a BEOL dielectric material layer over the MOL level.

11. The memory cell of claim 3, wherein both the MTJ pillar and the top electrode have a first critical dimension, and wherein the bottom electrode has a second critical dimension that is smaller than the first critical dimension.

12. The memory cell of claim 3, wherein both the MTJ pillar and the top electrode are cylindrical in shape.

13. A method of forming a memory cell, the method comprising: forming a front end of line (FEOL) level including a gate structure straddling over a semiconductor fin, with a source / drain structure on each side of the gate structure, and a source / drain contact structure on each source / drain structure; forming a layer of dielectric material of a middle of line (MOL) level over the FEOL level; forming a bottom electrode of a magnetoresistive random access memory (MRAM) device in the layer of dielectric material, and the bottom electrode contacts one of the source / drain contact structures on one side of the gate structure; forming a magnetic tunnel junction (MTJ) pillar and a top electrode of the MRAM device over the bottom electrode; forming a lower contact structure that contacts the other of the source / drain contact structures on the other side of the gate structure, with a lower portion of the lower contact structure embedded in the layer of dielectric material; and forming a back end of line (BEOL) level over the MOL level, and the BEOL level includes a first upper contact structure that contacts a surface of the lower contact structure and a second upper contact structure that contacts a surface of the top electrode of the MRAM device, wherein the bottom electrode of the magnetoresistive random access memory device and the lower portion of the lower contact structure are present in the same dielectric material.

14. The method of claim 13, wherein the forming of the MTJ pillar and the top electrode includes: forming a MTJ material stack and a top electrode layer; and patterning the MTJ material stack and the top electrode layer with ion beam etching.

15. The method of claim 14, wherein during the ion beam etching, a portion of the layer of dielectric material is recessed laterally adjacent to the bottom electrode, and the lower portion of the lower contact structure is embedded in the recessed portion of the layer of dielectric material.

16. The method of claim 13, further comprising forming a dielectric material spacer that encapsulates and surrounds the MTJ pillar and the top electrode.

17. The method of claim 13, wherein forming the lower contact structure includes: forming a contact opening in the layer of dielectric material that physically exposes a surface of the other of the source / drain contact structures on the other side of the gate structure; forming a conductive metal-containing layer on the layer of dielectric material, the conductive metal-containing layer includes within the contact opening and along sidewalls and over a topmost portion of the top electrode; forming a contact metal-containing layer on the conductive metal-containing layer; and ​ ​ recessing the contact metal-containing layer and the electrically conductive metal-containing layer to a height below a height of the top electrode; forming a hardmask cap over the recessed contact metal-containing layer; and patterning the hardmask cap, the recessed contact metal-containing layer, and the recessed electrically conductive metal-containing layer located in the other side of the gate structure.

18. The method of claim 17, wherein the contact opening has tapered sidewalls, and wherein the lower portion of the lower contact structure embedded in the dielectric material layer has tapered sidewalls.

19. The method of claim 13, wherein the MTJ pillar is a bottom pinned MTJ structure.

20. The method of claim 13, wherein the MTJ pillar is a top pinned MTJ structure.

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