Command and Response Descriptor Processing in the Hardware-Software Intercommunication System

Abstract

Embodiments of an apparatus and method for command and response descriptor processing may be applicable to a communication system, such as a wireless communication system. In an example, the method for descriptor processing may include instantiating, by a microcontroller of a node, a command descriptor for a command of a packet at a first layer of a protocol stack. The method may further include passing a command pointer pointing to the command descriptor from the microcontroller of the node to an integrated circuit of the node. The method may further include the integrated circuit looking up the command descriptor. The method may further include the integrated circuit processing the command.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 964,058, filed on January 21, 2020, with the title "Centralized Tracking and Management of Software - Hardware Interworking Modules", the entire content of which is incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate to apparatuses and methods for descriptor processing, which can be applied to communication systems, such as wireless communication systems. Background Art

[0004] Communication systems (such as wireless communication systems) are widely deployed to provide various telecommunication services, such as telephony, video, data, messaging, and broadcasting. When receiving packets through a medium (e.g., through radio in the case of wireless communication), an RF (radio frequency) module can convert radio waves into bits. These bits can be initially processed by the physical layer and then passed up to the protocol stack. Similarly, bits for transmission can be provided to the top of the protocol stack and then packed for transmission by the physical layer.

[0005] Multiple data structures are created, each customized for a specific protocol layer of the protocol stack. These data structures are instantiated at runtime, distributed throughout the memory, and physically placed in queues as they are, to facilitate hardware / software interworking. The size of the memory used by this method depends on the size of bit groupings (e.g., code blocks, protocol data units, service data units, packets, etc.). Summary of the Invention

[0006] Embodiments of apparatuses and methods for descriptor processing are disclosed herein.

[0007] In one example, an apparatus for descriptor processing can include a microcontroller for instantiating a command descriptor for a command regarding a packet at a first layer of a protocol stack. The microcontroller can also be used to pass a command pointer pointing to the command descriptor to an integrated circuit of the apparatus. The integrated circuit can be used to look up the command descriptor. The integrated circuit can also be used to process the command.

[0008] In another example, a method for descriptor processing can include instantiating, by a microcontroller of a node, a command descriptor for a command regarding a packet at a first layer of a protocol stack. The method can also include passing a command pointer pointing to the command descriptor from the microcontroller of the node to an integrated circuit of the node. The method can also include looking up the command descriptor by the integrated circuit. The method can also include processing the command by the integrated circuit.

[0009] In another example, a system for descriptor processing may include a command instantiation / update module for instantiating command descriptors for commands regarding packets at a first layer of a protocol stack. The system may also include a command pointer passing module for passing a command pointer pointing to a command descriptor. The system may also include a command lookup module for looking up command descriptors. The system may also include a command processing module for processing commands.

[0010] In yet another example, a non-transitory computer-readable medium may encode instructions that, when executed by a microcontroller of a node, perform a process for descriptor processing. The process may include the microcontroller instantiating command descriptors for commands regarding packets at a first layer of a protocol stack. The process may also include passing a command pointer pointing to a command descriptor from the microcontroller to an integrated circuit of the node. The command descriptor may be configured to allow the integrated circuit to look up commands. The command descriptor may be configured to also allow the integrated circuit to process commands. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings incorporated herein and forming a part of the specification illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable a person skilled in the relevant art to make and use the present disclosure.

[0012] Figure 1 Illustrates a system for descriptor processing according to some embodiments of the present disclosure.

[0013] Figure 2 Illustrates a memory for descriptor maintenance according to some embodiments of the present disclosure.

[0014] Figure 3 Illustrates a method for descriptor processing according to some embodiments of the present disclosure.

[0015] Figure 4 Illustrates a system of functional blocks for descriptor processing according to some embodiments of the present disclosure.

[0016] Figure 5 Illustrates a detailed block diagram of a baseband chip implementing packet processing using a layer 2 circuit and a microcontroller according to some embodiments of the present disclosure.

[0017] Figure 6 Illustrates an exemplary wireless network in which aspects of the present disclosure may be implemented and that may incorporate descriptor processing according to some embodiments of the present disclosure.

[0018] Figure 7 Illustrates a node that may be used for descriptor processing according to some embodiments of the present disclosure. Detailed Implementation Modes

[0019] Although specific configurations and structures have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and structures can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure can also be used in various other applications.

[0020] It should be noted that references in the specification to "one embodiment", "an embodiment", "example embodiment", "some embodiments", etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but not necessarily every embodiment includes the particular feature, structure, or characteristic. Moreover, these phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, whether or not explicitly described, those skilled in the relevant art can implement such feature, structure, or characteristic in connection with other embodiments.

[0021] Generally, terms can be understood, at least in part, from their use in context. For example, the term "one or more" used herein depends, at least in part, on context and can be used to describe any feature, structure, or characteristic in the singular form or can be used to describe a combination of features, structures, or characteristics in the plural form. Similarly, terms such as "a", "an", or "the" can also be understood to denote singular usage or plural usage, at least in part, depending on context. Additionally, the term "based on" can be understood to not necessarily imply a set of exclusive factors, but can allow for additional factors that may not be explicitly described, also at least in part, depending on context.

[0022] Aspects of a wireless communication system will now be described with reference to various apparatuses and methods. These apparatuses and methods will be described in the detailed implementation modes below and illustrated in the drawings by various boxes, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether these elements are implemented as hardware, firmware, or software depends on the specific application and design constraints of the overall system.

[0023] The techniques described herein can be used in various wireless communication networks, such as code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, orthogonal frequency division multiple access (OFDMA) systems, single-carrier frequency division multiple access (SC-FDMA) systems, and other networks. The terms "network" and "system" are often used interchangeably. CDMA networks can implement radio access technologies (RATs), such as universal terrestrial radio access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. TDMA networks can implement RATs such as GSM. OFDMA networks can implement RATs such as long term evolution (LTE) or new radio (NR). The techniques and systems described herein can be used in the above-mentioned wireless networks and RATs, as well as other wireless networks and RATs. Similarly, the techniques and systems described herein can also be applied to wired networks, such as networks based on optical fiber, coaxial cable, or twisted pair, or satellite networks.

[0024] Some embodiments of the present disclosure relate to a mechanism that uses a monolithic centralized data structure in a memory as a basic unit to describe states and includes commands for protocol data units (PDUs), which are sometimes also referred to as packets, and the packets vertically traverse the protocol layers up and down. Such a data structure can be referenced by pointers at runtime to allow interoperability between software and hardware. A block of such pointers in consecutive memory locations can also facilitate highly automated processing in software and hardware.

[0025] For various technical aspects, some embodiments can have various benefits and / or advantages. For example, some embodiments can improve hardware efficiency. Instead of implementing four templates to accommodate four protocol layers - Medium Access Control (MAC), Radio Link Control (RLC), Packet Data Convergence Protocol (PDCP), and Service Data Adaptation Protocol (SDAP), a single general packet descriptor can be used. Similarly, some embodiments do not require an additional tracking module to track the position of PDUs in the stack, so the correct template among the four templates can be applied. In some embodiments, a single common template can be used. The active hardware modules can access only the required entries. In this way, there may be no confusion, no ambiguity, no chance of error, and no cross-checking.

[0026] In addition, some embodiments can save memory space. In the case of four protocol layers and four templates, there may be common fields among these four protocol layers. These common fields may be repeated between the templates. Therefore, some embodiments can avoid using unnecessary memory space to store and move those repeated fields. For example, compared with four data structures with many shared fields, one data structure can result in less memory usage. If 40 bytes can be saved on a single PDU, then 20,000 PDUs will save 800 kilobytes (KB) of memory. In some embodiments, there can be only one data structure that combines the necessary information fields required by four or more protocol layers. Therefore, this data structure does not need to be moved. Instead, pointers can be used to guide the control to access the data. In this way, less memory space can be consumed, and less memory movement can be caused. Less memory space can make the implementation cost lower, and less memory movement can make the power consumption lower, which can make the call time longer in the device.

[0027] Some embodiments can also be beneficial to software efficiency. In terms of hardware, in a method lacking a general packet descriptor, there may be counterparts for these four types of data structures declared and used throughout the protocol stack. Using a single general packet descriptor can provide a concise software implementation. For example, there can be only one structure and one memory to look up. This simplicity is also beneficial for data tracking, throughput analysis, and / or characterizing traffic flows.

[0028] Some embodiments can also provide memory space benefits for software. Simplicity in design can directly translate into code space savings. Some embodiments significantly reduce the memory size occupied by code. The reduction in memory space can reduce costs.

[0029] Some embodiments can also be beneficial for scalability. The scalability of a scheme with a centralized descriptor can be much greater than that of a scheme with multiple descriptors. Without changing the hardware, more information elements can be filled at the end of the data structure, and all modules in the software protocol stack can access these additional fields. Changing the hardware register definition may also require changing the hardware. Therefore, some embodiments can reduce the need for hardware upgrades.

[0030] Some embodiments can be beneficial for efficiency in various aspects. Using a single bookkeeping to track the usage of descriptors can make memory management easier. Fewer memory copies can also mean fewer bus cycles and less power consumption. In a fifth-generation (5G) network, less power consumption can enable longer call times and / or high throughput and massive data streams. Especially in power-constrained devices (such as battery-powered devices), various applications can benefit from such results.

[0031] Some embodiments can also be beneficial for development and debugging. A structure suitable for multiple software protocol modules can simplify coding and debugging. For example, a single macro can be provided in one place in the code to analyze the activity of data packets and their positions in the uplink or downlink during debugging. In software without a common packet descriptor, for the same purpose, this can replace hundreds of lines of code covering various loose ends, and there is still a risk of missing one or more actions in these hundreds of lines of code.

[0032] One aspect of some embodiments is a common packet descriptor. The common packet descriptor can include aspects such as location, status, size, behavior, and other protocol-related attributes considered at any given time. A single template or mold common packet descriptor can be applied in each case.

[0033] In the case of downlink processing in a user equipment (UE) or uplink processing in a base station (BS) or other access node, a specific embodiment of instantiating a general packet descriptor from an on-board memory pool can be made when decoding a data packet from the MAC layer. The descriptor can be released at the top of the PDCP layer. Thus, the life cycle of the descriptor can be the time taken to process the corresponding decoded data through the entire protocol stack. Since the MAC PDU can be the useful processing part from the MAC layer upwards, a general packet descriptor can be employed for each protocol data unit.

[0034] According to some embodiments, there can be various aspects of the interoperability between hardware and software. For example, command / response queues can provide one-way communication. These queues can act as first-in-first-out (FIFO) and can be paired to facilitate two-way communication between hardware and software in each protocol layer. Commands can be input from software into the queue to configure or indicate how the hardware should operate. Vice versa, responses can be fed from the hardware into another queue to indicate the status or response to any given command.

[0035] There may be no need for latency in either hardware or software. The sender can simply pump action items into the queue, while the receiver can extract and execute these action items from the queue. Software can rely on interrupts to keep it running, and hardware can use a clock or the completion of a previous task to periodically check and see if there is anything in the queue.

[0036] Commands and responses can be listed in a descriptor table pointed to by a pointer instantiated from the sender. The pointer can then be inserted at the end of the queue so that it can be serviced at the other end. Thus, the queue may only include pointers rather than the actual descriptor table.

[0037] There may be various ways to implement these different aspects. For example, some embodiments may be implemented as a system on chip (SoC). The SoC may include a microcontroller, a central processing unit (CPU), a CPU cache, a graphics processing unit (GPU), and other processing and storage elements. The SoC may include a camera image signal processor (ISP), a digital signal processor (DSP), and interfaces to on-chip and off-chip memories. The SoC may be broadly divided into a multi-core subsystem, a multimedia subsystem, and a modem subsystem. Each of these subsystems may be connected via a fabric system and may access memory, such as dual-channel memory.

[0038] The modem subsystem may be an integrated multi-mode modem. For example, the modem subsystem may be used to operate in third-generation (3G), fourth-generation (4G), LTE, and fifth-generation (5G) communication systems. The modem subsystem may also be used to operate using Bluetooth and WiFi. In addition, the modem subsystem may be used to receive other terrestrial wireless signals, such as frequency modulation (FM) and / or amplitude modulation (AM) wireless signals, and positioning signals, such as global positioning system (GPS), global navigation satellite system (GLONASS), Galileo, and / or Beidou. The modem subsystem may also be equipped for other communication methods, including satellite communication and near field communication (NFC). The DSP of the SoC may include multiple cores. For example, the multimedia subsystem may use one or more DSP cores, and the modem subsystem may use one or more other DSP cores.

[0039] Some aspects of the description of some embodiments of the present disclosure discuss hardware aspects and software aspects. In some cases, the hardware aspects may refer to aspects performed by dedicated hardware, such as a hardware-based protocol stack implementation. The following discussion Figure 5A specific example of a hardware-based protocol stack implementation is provided, which has multiple application-specific integrated circuits (ASICs, for example) that handle different layers of the protocol stack. On the other hand, the software aspect can refer to aspects that can be executed by a general-purpose processor or by a layer-independent dedicated modem processor. Figure 5 A specific example is shown in which the software aspect can be implemented on a microcontroller.

[0040] Figure 1 A software-hardware interoperable system 100 for descriptor processing according to some embodiments of the present disclosure is shown. As Figure 1 shown, the system can involve the exchange of commands and responses between an integrated circuit 110 (also referred to as hardware) and a microcontroller 120 (also referred to as software). The integrated circuit 110 can include dedicated circuits for processing input packets and / or output packets. In some embodiments, the software-hardware interoperable system 100 can be implemented in whole or in part in a baseband SoC, which can be part of a larger SoC.

[0041] The integrated circuit 110 can include circuits or sub-circuits for processing one or more specific layers of the protocol stack. Each of these layer-dedicated circuits or sub-circuits can be referred to as a hardware module. For example, as Figure 1 shown, the integrated circuit 110 can include a hardware SDAP module 130, a hardware PDCP module 140, a hardware RLC module 150, and a hardware MAC module 160.

[0042] Similarly, the microcontroller 120 can include functions implemented as software processes. Each of these functions can be used to process one or more specific layers of the protocol stack. As an example, software running on a general-purpose processor or a baseband processor can handle all the functions of the microcontroller 120. Each of these software processes can be referred to as a software module. For example, as Figure 1 shown, the microcontroller 120 can include a software SDAP module 135, a software PDCP module 145, a software RLC module 155, and a software MAC module 165.

[0043] As Figure 1As shown, the microcontroller 120 can provide commands to the integrated circuit 110. Similarly, the integrated circuit 110 can provide responses to the microcontroller 120. To provide these commands and responses, various queues can be used. For example, the software MAC module 165 can use queue 171 to provide commands and can receive responses in queue 172 from the hardware MAC module 160. Similarly, queues 173 and 174 can be used for commands and responses of the RLC layer respectively, queues 175 and 176 can be used for commands and responses of the PDCP layer respectively, and queues 177 and 178 can be used for commands and responses of the SDAP layer respectively.

[0044] As Figure 1 As shown in the enlarged portion in the lower right corner, queue 171 can include commands (CMD) 1 to CMD N. The software MAC module 165 can place these commands into queue 171, and the hardware MAC module 160 can read these commands from queue 171 in the order in which these commands are queued. Similarly, queue 172 can include responses (RSP) 1 to RSP N. The hardware MAC module 160 can place these responses into queue 172, and the software MAC module 165 can read these responses from queue 172 in the order in which these responses are queued.

[0045] As Figure 1 As shown in the further enlarged portion in the lower left corner, CMD N can include an address pointer. In some embodiments, CMD N can be just an address pointer. The address pointer can point to a location in the memory that contains a descriptor.

[0046] Figure 2 A memory 200 for storing descriptors according to some embodiments of the present disclosure is shown. The memory 200 can include a plurality of descriptors 205-1 to 205-n. Each descriptor can include various fields. The first field can be a pointer 210 to a given packet. In the case of downlink (DL) processing, the above-mentioned given packet can be a packet received at the physical (PHY) layer. In the case of uplink (UL) processing, the above-mentioned given packet can be a packet generated by the host or application of the user equipment (UE).

[0047] Each of descriptors 205-1 to 205-n may include multiple fields. The format of these fields may be designed to include enough fields for each layer of the protocol stack such that the same descriptor can be reused for each layer of the protocol stack. In some embodiments, each field may have a static length. In other embodiments, each field may have a dynamic length. A combination of dynamic length fields and static length fields is also allowed. The total descriptor length may be longer than the length required for any one layer. On the other hand, many layers may use the same fields. A descriptor with no field content may be regarded as a template. By including fields sufficient to serve each layer, a unified template can be used and reused at each layer.

[0048] The fields of each descriptor may include a field for command 220, which may provide a command or a response. For example, software may fill this field with a command. The descriptor may also include a field for status 230. For example, hardware may fill this field with a response to the command (such as "acknowledge" or "fail"). Other fields may indicate details about the packet or the communication of the packet, such as packet type 240, channel type 250, protocol type 260, and data length 270. These are just examples. Different fields may be used, as well as fewer or more fields.

[0049] Figure 3 A method 300 for descriptor processing according to some embodiments is shown. Figure 4 A system 400 for descriptor processing according to some embodiments is shown. System 400 may be used to perform, for example, Figure 3 the method shown. Figure 3 The steps on the right may be performed by software running on a processor, such as Figure 1 the microcontroller 120 in. Figure 4 The microcontroller 407 shown may implement Figure 3 the steps on the right using various software modules.

[0050] As Figure 3 shown on the right, at operation 310, the software of the system may receive an interrupt. The interrupt receiving module 410 may be used to implement operation 310. The receipt of the interrupt may be a trigger for issuing a command. At operation 315, the software may instantiate and / or update a command descriptor. For example, when a packet first arrives at the protocol stack, the software may instantiate the descriptor. Subsequently, the software may only update the descriptor until the packet leaves the stack. The command descriptor instantiation / update module 415 may be used to implement operation 315.

[0051] At operation 320, the software may pass a command pointer to the hardware. The command pointer may be an address stored in the memory 200, at which address a descriptor (such as descriptor 205-1) is stored. This passing at operation 320 may be performed by the microcontroller 120, placing the address in a queue, and the integrated circuit 110 may read the address from the queue in the same order in which the address was placed in the queue. This queuing manner may be referred to as FIFO. Other queuing manners may be used. The command pointer passing module 420 may be used to implement operation 320.

[0052] Figure 3 The left side shows operations that may be performed by the hardware of the system (such as Figure 1 the integrated circuit 110 in Figure 4 The integrated circuit 405 shown may be implemented using various modules to Figure 3 perform the steps on the left side. As Figure 3 shown, after operation 320, at operation 325, the system may receive a command pointer. Operation 325 may be implemented by a command pointer receiving module 425 in, for example, the integrated circuit 405. The integrated circuit 405 may be implemented individually in hardware, or hardware running software, or firmware. For example, the integrated circuit 405 may be composed of discrete ASICs, each ASIC performing packet processing corresponding to a single layer of the protocol stack.

[0053] Refer to Figure 3 , at operation 330, the system may use the pointer to look up a descriptor. This operation may be implemented using a command descriptor lookup module 430. Similarly, at operation 335, the system may process the command. The command processor module 435 may implement operation 335.

[0054] At operation 340, the system may update the descriptor to be used as a response descriptor. This process may also be regarded as instantiating a response descriptor. As an alternative, a separate response descriptor may be instantiated, although this may require using additional memory. Operation 340 may be implemented by the Figure 4 response descriptor instantiation / update module 440 in

[0055] Refer to Figure 3 , at operation 345, the system may pass a response pointer. The response pointer may be an address, which may be the same as the address passed at operation 320. This passing at operation 345 may be performed by the integrated circuit 110, placing the address in a queue, and the microcontroller 110 may read the address from the queue. Operation 345 may be implemented by the response pointer passing module 445.

[0056] For example, as Figure 1As shown, the queue for responses can be different from the queue for commands. At operation 350, the system can receive a response pointer, for example, using the response pointer receiving module 450. Next, at operation 355, the response descriptor lookup module 455 can look up the response descriptor. Looking up the response descriptor can involve reading from the memory 200.

[0057] Referring Figure 3 , at operation 360, the system can process the response using, for example, the response processor module 460. Then, when a new command descriptor is generated, the process can return to, for example, operation 315. For a given packet, the process at a given layer of the stack can end at operation 360 and can address subsequent packets at the given layer. The next layer of the stack can reuse the same command descriptor. Thus, at the second or subsequent layer, at operation 315, the command descriptor instantiation / update module 415 can only update an already existing descriptor, such as the descriptor processed by the response processor module 460 at operation 360 in the previous layer. As Figure 1 shown, each layer can have its own dedicated hardware and software.

[0058] Figure 5 FIG. shows a detailed block diagram of a baseband SoC 502 that implements Layer 2 packet processing using a Layer 2 circuit 508 and a microcontroller (MCU) 510 according to some embodiments of the present disclosure. The baseband SoC 502 can be an example of a software-hardware interoperable system, where software functions are implemented by the MCU 510 and hardware functions are implemented by the Layer 2 circuit 508. The MCU 510 can be an example of the microcontroller 120, and the Layer 2 circuit 508 can be Figure 1 an example of the integrated circuit 110 in. In some embodiments, the Layer 2 circuit 508 includes an SDAP circuit 520, a PDCP circuit 522, an RLC circuit 524, and a MAC circuit 526. Application-specific integrated circuits (ICs) (e.g., the SDAP circuit 520, the PDCP circuit 522, the RLC circuit 524, and the MAC circuit 526) controlled by the MCU 510 can be used to perform Layer 2 packet processing. In some embodiments, each of the SDAP circuit 520, the PDCP circuit 522, the RLC circuit 524, and the MAC circuit 526 is an IC dedicated to performing the functions of the corresponding layer in the Layer 2 user plane and / or control plane. For example, each of the SDAP circuit 520, the PDCP circuit 522, the RLC circuit 524, and the MAC circuit 526 can be an ASIC that can be customized for a specific purpose rather than for general purposes. Compared with a general processor, some ASICs may have high speed, small chip size, and low power consumption.

[0059] As Figure 5 shown, the baseband SoC 502 can be operatively coupled to the host processor 504 and the external memory 506 via the main bus 538. For uplink communication, a host processor 504, such as an application processor (AP), can generate raw data that has not been encoded and modulated by the PHY layer of the baseband SoC 502. Similarly, for downlink communication, data can be received by the host processor 504 after being initially decoded and demodulated by the PHY layer and subsequently processed by the Layer 2 circuitry 508. In some embodiments, the raw data is formatted into data packets according to any suitable protocol, such as an internet protocol (IP) packet. The external memory 506 can be shared by the host processor 504 and the baseband SoC 502 or any other suitable component.

[0060] In some embodiments, the external memory 506 stores raw data (e.g., IP packets) to be processed by the Layer 2 circuitry 508 of the baseband SoC 502 and stores data (e.g., MAC PDUs) processed by the Layer 2 circuitry 508 to be accessed by the Layer 1 (e.g., PHY layer). Conversely, in a downlink stream from the user equipment, the external memory 506 can store data received from the PHY layer and data output from the Layer 2 circuitry 508 after header removal and other tasks. The external memory 506 may or may not store any intermediate data of the Layer 2 circuitry 508, such as PDCP PDUs / RLC SDUs, or RLC PDUs / MAC SDUs. For example, the Layer 2 circuitry 508 can modify the data stored in the external memory 506.

[0061] As Figure 5 shown, the baseband SoC 502 can also include a direct memory access (DMA) 516, which can allow some of the Layer 2 circuitry 508 to directly access the external memory 506 independently of the host processor 504. The DMA 516 can include a DMA controller and any other suitable input / output (I / O) circuitry. As Figure 5 shown, the baseband SoC 502 can also include a local memory 514, such as on-chip memory on the baseband SoC 502, which is different from the external memory 506, which is off-chip memory not on the baseband SoC 502. In some embodiments, the local memory 514 includes one or more L1, L2, L3, or L4 caches. The Layer 2 circuitry 508 can also access the local memory 514 via the main bus 538.

[0062] As Figure 5 shown, the baseband SoC 502 may also include a memory 512 that can be shared (e.g., accessed) by the Layer 2 circuitry 508 and the MCU 510. It should be understood that although the memory 512 is shown as a separate memory separate from the local memory 514, in some examples, the memory 512 and the local memory 514 may be local partitions of the same physical memory structure, such as a static random-access memory (SRAM). In one example, logical partitions in the local memory 514 may be dedicated to or dynamically allocated to the Layer 2 circuitry 508 and the MCU 510 for exchanging commands and responses. In some embodiments, the memory 512 includes a plurality of command queues 534 for storing respective sets of commands and a plurality of response queues 536 for storing respective sets of responses. Each pair of corresponding command queue 534 and response queue 536 may be dedicated to one of the Layer 2 circuitry 508. Similarly, the command queue 534 may correspond to Figure 1 queues 171, 173, 175, and 177 in

[0063] As Figure 5 shown, the baseband SoC 502 may also include a local bus 540. In some embodiments, the MCU 510 may be operatively coupled to the memory 512 and the main bus 538 via the local bus 540. The MCU 510 may be used to generate respective sets of control commands and write each set of commands to the corresponding command queue 534 in the memory 512 via the local bus 540 and an interrupt. The MCU 510 may also read respective sets of responses (e.g., processing result status) from the response queues 536 in the memory 512 via the local bus 540 and an interrupt, respectively. In some embodiments, the MCU 510 generates a set of commands based on a set of responses from a higher layer in the Layer 2 protocol stack (e.g., the previous stage in Layer 2 uplink data processing) or a lower layer in the Layer 2 protocol stack (e.g., the previous stage in Layer 2 downlink data processing). Through the control commands in the command queue 534 in the memory 512, the MCU 510 is operatively coupled to the Layer 2 circuitry 508 and controls the operation of the Layer 2 circuitry 508 to process Layer 2 data. It should be understood that although Figure 5An MCU 510 is shown, but the number of MCUs is scalable such that multiple MCUs may be used in some examples. It should also be understood that in some embodiments, the memory 512 may be part of the MCU 510, e.g., a cache integrated with the MCU 510. It should also be understood that regardless of the naming, any suitable processing unit that can generate control commands to control the operation of the Layer 2 circuit 508 and check the response of the Layer 2 circuit 508 may be considered the MCU 510 disclosed herein.

[0064] The software and hardware interoperability system disclosed herein may be implemented by any suitable node in a wireless network (e.g., Figure 1 system 100 in Figure 5 and Figure 6 the baseband SoC 502 in). For example,

[0065] As Figure 6 shown, the wireless network 600 may include a network of nodes, such as user equipment (UE) 602, access nodes 604, and core network elements 606. The user equipment 602 may be any terminal device, such as a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, gaming console, printer, positioning device, wearable electronic device, smart sensor, or any other device capable of receiving, processing, and transmitting information, e.g., any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Internet-of-Things (IoT) node. It should be understood that the user equipment 602 is shown as a mobile phone for illustration only and not as a limitation.

[0066] The access node 604 may be a device that communicates with the user equipment 602, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, etc. The access node 604 may have a wired connection to the user equipment 602, a wireless connection to the user equipment 602, or any combination thereof. The access node 604 may be connected to the user equipment 602 through multiple connections, and the user equipment 602 may be connected to other access nodes in addition to the access node 604. The access node 604 may also be connected to other user equipment. It should be understood that the access node 604 is shown as a radio tower for illustration only and not as a limitation.

[0067] The core network element 606 can serve the access node 604 and the user equipment 602 to provide core network services. Examples of the core network element 606 can include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of the core network elements of an evolved packet core (EPC) system, which is the core network of an LTE system. Other core network elements can be used in LTE and other communication systems. In some embodiments, for the core network of an NR system, the core network element 606 includes an access and mobility management function (AMF) device, a session management function (SMF) device, or a user plane function (UPF) device. It can be understood that the core network element 606 is shown as a set of rack-mounted servers for illustration purposes only and not as a limitation.

[0068] The core network element 606 can be connected to a large network such as the Internet 608 or another IP network to transmit packet data over any distance. In this way, data from the user equipment 602 can be transmitted to other UEs connected to other access points, including, for example, a computer 610 that is wired or wirelessly connected to the Internet 608, or a tablet 612 that is wirelessly connected to the Internet 608 through a router 614. Thus, the computer 610 and the tablet 612 provide additional examples of possible UEs, and the router 614 provides an example of another possible access node.

[0069] A general example of a rack-mounted server is provided as an illustration of the core network element 606. However, there may be multiple elements in the core network, including database servers, such as database 616, and security and authentication servers, such as authentication server 618. For example, database 616 can manage data related to user subscriptions to network services. A home location register (HLR) is an example of a subscriber information standardization database for a cellular network. Similarly, authentication server 618 can handle the authentication of users, sessions, etc. In an NR system, an authentication server function (AUSF) device can be a specific entity that performs user equipment authentication. In some embodiments, a single server rack can handle multiple such functions, such that the connections between core network element 606, authentication server 618, and database 616 can be local connections within a single rack.

[0070] Although the above description uses the uplink processing and downlink processing of packets in a user equipment as examples in various discussions, similar techniques can also be used for processing in other directions and for processing in other devices (such as access nodes and core network nodes). For example, even if not specifically listed above or not specifically shown in the Figure 6 example network, any device that processes packets through multiple layers of a protocol stack can benefit from some embodiments of the present disclosure.

[0071] Figure 6 Each element in can be considered a node of the wireless network 600. In the following Figure 7 description of node 700, more details about possible implementation manners of the node are provided as examples. Node 700 can be configured to be Figure 6 the user equipment 602, access node 604, or core network element 606 in. Similarly, node 700 can also be configured to be Figure 6 the computer 610, router 614, tablet 612, database 616, or authentication server 618 in.

[0072] As Figure 7 shown, node 700 can include a processor 702, a memory 704, and a transceiver 706. These components are shown as being connected to each other through a bus 708, but other connection types are also allowed. When node 700 is the user equipment 602, additional components, such as a user interface (UI), sensors, etc., may also be included. Similarly, when node 700 is configured as the core network element 606, node 700 can be implemented as a blade in a server system. Other implementations are also possible.

[0073] The transceiver 706 can include any suitable device for transmitting and / or receiving data. The node 700 can include one or more transceivers, but only one transceiver 706 is shown for simplicity. The antenna 710 is shown as a possible communication mechanism of the node 700. Multiple antennas and / or antenna arrays can be used. In addition, examples of the node 700 can communicate using wired technologies instead of or in addition to wireless technologies. For example, the access node 604 can communicate wirelessly with the user equipment 602 and can communicate with the core network element 606 through a wired connection (e.g., through an optical fiber cable or a coaxial cable). Other communication hardware, such as a network interface card (NIC), can also be included.

[0074] As Figure 7 shown, the node 700 can include a processor 702. Although only one processor is shown, it can be understood that multiple processors can be included. The processor 702 can include a microprocessor, a microcontroller, a DSP, an ASIC, a field-programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gated logic, discrete hardware circuits, and other suitable hardware for performing the various functions described in this disclosure. The processor 702 can be a hardware device having one or more processing cores. The processor 702 can execute software. Whether referred to as software, firmware, middleware, microcode, hardware description language, or others, software should be interpreted broadly as instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, execution threads, processes, functions, etc. The software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for guiding hardware are also allowed under the broad software category.

[0075] As Figure 7As shown, node 700 may also include a memory 704. Although only one memory is shown, it can be understood that multiple memories may be included. Memory 704 can broadly include memory and storage. For example, memory 704 can include random-access memory (RAM), read-only memory (ROM), SRAM, dynamic RAM (DRAM), ferro-electric RAM (FRAM), electrically erasable programmable ROM (EEPROM), CD-ROM or other optical disc storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store the required program code in the form of instructions that can be accessed and executed by processor 702. Broadly speaking, memory 704 can be implemented by any computer-readable medium, such as a non-transitory computer-readable medium.

[0076] In various aspects of the present disclosure, the functions described herein can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, these functions can be stored or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media can be any available medium that can be accessed by a computing device (such as Figure 7 the node 700 in). By way of example and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disc memory, HDD (such as magnetic disk memory or other magnetic storage devices), flash drive, SSD, or any other medium that can be used to carry or store the required program code in the form of instructions or data structures and can be accessed by a processing system (such as a mobile device or a computer). As used herein, magnetic disks and optical discs include CDs, laser discs, optical discs, DVDs, and floppy disks, where magnetic disks typically reproduce data magnetically, while optical discs reproduce data optically with a laser. Combinations of the above should also be included within the scope of computer-readable media.

[0077] According to one aspect of the present disclosure, an apparatus for descriptor processing may include a microcontroller and an integrated circuit. The microcontroller can be used to instantiate command descriptors for commands regarding packets at the first layer of a protocol stack. The microcontroller can also be used to pass a command pointer pointing to the command descriptor to the integrated circuit. The integrated circuit can be used to look up the command descriptor. The integrated circuit can also be used to process the command.

[0078] In some embodiments, the first layer may be the MAC layer.

[0079] In some embodiments, a microcontroller may be used to receive an interrupt. The receipt of the interrupt may be a trigger for the microcontroller to issue a command.

[0080] In some embodiments, an integrated circuit may be used to instantiate a response descriptor or update the above command descriptor to be used as a response descriptor.

[0081] In some embodiments, an integrated circuit may be used to pass a response pointer pointing to the response descriptor.

[0082] In some embodiments, a microcontroller may be used to receive the response pointer. The microcontroller may also be used to look up the response descriptor. The microcontroller may also be used to process the response.

[0083] In some embodiments, the command descriptor may include a general packet descriptor.

[0084] In some embodiments, the command descriptor may be configured to be used by the first layer of the protocol stack and at least one other layer of the protocol stack.

[0085] In some embodiments, the command descriptor may be configured to be used by the first layer of the protocol stack and at least three other layers of the protocol stack.

[0086] In some embodiments, the response descriptor may be a general packet descriptor.

[0087] In some embodiments, the response descriptor may be configured to be used by the first layer of the protocol stack and at least one other layer of the protocol stack.

[0088] In some embodiments, the response descriptor may be configured to be used by the first layer of the protocol stack and at least three other layers of the protocol stack.

[0089] In some embodiments, the life cycle of the updated command descriptor may correspond to the packet passing through all layers of the protocol stack.

[0090] In some embodiments, a microcontroller may be used to instantiate a new command descriptor or update the command descriptor regarding the packet at the second layer of the protocol stack. The microcontroller may also be used to pass a command pointer pointing to the new command descriptor or a command pointer pointing to the updated command descriptor to the integrated circuit.

[0091] According to another aspect of the present disclosure, a method for descriptor processing may include instantiating, by a microcontroller of a node, a command descriptor for a command of a packet at a first layer of a protocol stack. The method may further include passing a command pointer pointing to the command descriptor from the microcontroller of the node to an integrated circuit of the node. The method may further include the integrated circuit looking up the command descriptor. The method may further include the integrated circuit processing the command.

[0092] In some embodiments, the first layer may be a MAC layer.

[0093] In some embodiments, the method may further include the microcontroller receiving an interrupt. The receipt of the interrupt may be a trigger for the microcontroller to issue a command.

[0094] In some embodiments, the method may further include the integrated circuit instantiating a response descriptor or updating the above command descriptor to be used as a response descriptor.

[0095] In some embodiments, the method may further include passing a response pointer pointing to the response descriptor to the microcontroller.

[0096] In some embodiments, the method may further include receiving the response pointer. The method may further include the microcontroller looking up the response descriptor. The method may further include the microcontroller processing the response.

[0097] In some embodiments, the command descriptor may be a general packet descriptor.

[0098] In some embodiments, the command descriptor may be configured to be used by the first layer of the protocol stack and at least one other layer of the protocol stack.

[0099] In some embodiments, the command descriptor may be configured to be used by the first layer of the protocol stack and at least three other layers of the protocol stack.

[0100] In some embodiments, the response descriptor may be a general packet descriptor.

[0101] In some embodiments, the response descriptor may be configured to be used by the first layer of the protocol stack and at least one other layer of the protocol stack.

[0102] In some embodiments, the response descriptor may be configured to be used by the first layer of the protocol stack and at least three other layers of the protocol stack.

[0103] In some embodiments, the lifecycle of the updated command descriptor corresponds to the packet passing through all layers of the protocol stack.

[0104] In some embodiments, the method may include instantiating a new command descriptor or updating a command descriptor regarding a packet by a microcontroller of a node at the second layer of a protocol stack. The method may include passing a command pointer pointing to the new command descriptor or a command pointer pointing to the updated command descriptor from the microcontroller of the node to an integrated circuit of the node.

[0105] According to another aspect of the present disclosure, a system for descriptor processing may include a command instantiation / update module for instantiating a command descriptor regarding a packet at the first layer of a protocol stack. The system may further include a command pointer passing module for passing a command pointer pointing to the command descriptor. The system may further include a command lookup module for looking up the command descriptor. The system may further include a command processing module for processing the command.

[0106] In some embodiments, the first layer may be a MAC layer.

[0107] In some embodiments, the system may include an interrupt receiving module for receiving an interrupt. The receipt of the interrupt may be a trigger for issuing a command.

[0108] In some embodiments, the system may include a response descriptor instantiation / update module for instantiating a response descriptor or updating the above-mentioned command descriptor to be used as a response descriptor.

[0109] In some embodiments, the system may include a response pointer passing module for passing a response pointer pointing to the response descriptor.

[0110] In some embodiments, the system may include a response pointer receiving module for receiving a response pointer. The system may further include a response descriptor lookup module for looking up the response descriptor. The system may further include a response processing module for processing the response.

[0111] In some embodiments, the command descriptor may be a general packet descriptor.

[0112] In some embodiments, the command descriptor may be configured to be used by the first layer of the protocol stack and at least one other layer of the protocol stack.

[0113] In some embodiments, the command descriptor may be configured to be used by the first layer of the protocol stack and at least three other layers of the protocol stack.

[0114] In some embodiments, the response descriptor may be a general packet descriptor.

[0115] In some embodiments, the response descriptor may be configured to be used by the first layer of the protocol stack and at least one other layer of the protocol stack.

[0116] In some embodiments, a response descriptor may be configured to be used by a first layer of a protocol stack and at least three other layers of the protocol stack.

[0117] In some embodiments, the lifetime of an updated command descriptor may correspond to a packet passing through all layers of the protocol stack.

[0118] In some embodiments, a command instantiation / update module may also be used to instantiate a new command descriptor for a packet or update a command descriptor for a packet at a second layer of the protocol stack. A command pointer passing module may also be used to pass a command pointer to the new command descriptor or a command pointer to the updated command descriptor.

[0119] According to another aspect of the present disclosure, a non-transitory computer-readable medium may encode instructions that, when executed by a microcontroller of a node, perform a process for descriptor processing. The process may include the microcontroller instantiating a command descriptor for a command for a packet at a first layer of the protocol stack. The process may also include passing a command pointer to the command descriptor from the microcontroller to an integrated circuit of the node. The command descriptor may be configured to allow the integrated circuit to look up the command. The command descriptor may be configured to also allow the integrated circuit to process the command.

[0120] In some embodiments, the first layer may be a MAC layer.

[0121] In some embodiments, the process may include the microcontroller receiving an interrupt. The receipt of the interrupt may be a trigger for the microcontroller to issue a command.

[0122] In some embodiments, the process may include receiving a response pointer to a response descriptor in response to the command. The process may also include the microcontroller looking up the response descriptor. The process may also include the microcontroller processing the response.

[0123] In some embodiments, the command descriptor may be a general packet descriptor.

[0124] In some embodiments, the command descriptor may be configured to be used by a first layer of the protocol stack and at least one other layer of the protocol stack.

[0125] In some embodiments, the command descriptor may be configured to be used by a first layer of the protocol stack and at least three other layers of the protocol stack.

[0126] In some embodiments, the response descriptor may be a general packet descriptor.

[0127] In some embodiments, the response descriptor may be configured to be used by a first layer of the protocol stack and at least one other layer of the protocol stack.

[0128] In some embodiments, a response descriptor can be configured to be used by a first layer of a protocol stack and at least three other layers of the protocol stack.

[0129] In some embodiments, the lifetime of an updated command descriptor can correspond to a packet passing through all layers of the protocol stack.

[0130] In some embodiments, the process can include a microcontroller of a node instantiating a new command descriptor or updating a command descriptor regarding a packet at a second layer of the protocol stack. The process can also include passing a command pointer to the new command descriptor or a command pointer to the updated command descriptor from the microcontroller of the node to an integrated circuit of the node.

[0131] The description of the specific embodiments above will disclose the general nature of the present disclosure, so that others can, without departing from the general concept of the present disclosure, easily modify such specific embodiments and / or adapt them to various applications by applying the knowledge within the art. Therefore, such adaptations and modifications are intended to be within the meaning and scope of the equivalents of the disclosed embodiments based on the teachings and guidance presented herein. It should be understood that the words or terms herein are for the purpose of description rather than limitation, so the terms or words of this specification will be interpreted by those skilled in the art according to the teachings and guidance.

[0132] Embodiments of the present disclosure have been described above by means of functional building blocks that illustrate the specified functions and their relationships. For the convenience of description, the boundaries of these functional building blocks have been arbitrarily defined here. Alternative boundaries can be defined as long as they are suitable for performing the specified functions and their relationships.

[0133] The Summary of the Invention and the Abstract sections may set forth one or more embodiments of the present disclosure as contemplated by the inventors, but not all exemplary embodiments, and thus, the Summary of the Invention and the Abstract are not intended to limit the present disclosure and the appended claims in any way.

[0134] Various functional blocks, modules, and steps have been disclosed above. The particular arrangements provided are illustrative and not restrictive. Therefore, the functional blocks, modules, and steps can be reordered or combined in a different manner than the examples provided above. Similarly, some embodiments only include a subset of the functional blocks, modules, and steps, and any such subset is allowed.

[0135] The breadth and scope of the present disclosure should not be limited by any of the above exemplary embodiments, but should be defined only in accordance with the claims and their equivalents.

Claims

1. An apparatus for descriptor processing, comprising: A microcontroller, configured to: Instantiate a command descriptor for a command of a packet at a first layer of a protocol stack, and Pass a command pointer pointing to the command descriptor to an integrated circuit of the apparatus; and The integrated circuit is configured to: Locate the command descriptor; And Process the command; Wherein, the integrated circuit is configured to instantiate a response descriptor or update the command descriptor for use as the response descriptor, and the integrated circuit is configured to pass a response pointer pointing to the response descriptor to the microcontroller.

2. The device according to claim 1, wherein The first layer includes a Media Access Control (MAC) layer.

3. The device according to claim 1 or 2, wherein, The microcontroller is configured to receive an interrupt, wherein the receipt of the interrupt is a trigger for the microcontroller to issue the command.

4. The device according to claim 3, wherein, The microcontroller is further configured to: Receive the response pointer; Locate the response descriptor; and Process the response.

5. The apparatus according to claim 1, wherein The command descriptor includes a general packet descriptor.

6. The device according to claim 5, wherein, The command descriptor is configured to be used by the first layer of the protocol stack and at least one other layer of the protocol stack.

7. The apparatus according to claim 6, wherein, The command descriptor is configured to be used by the first layer of the protocol stack and at least three other layers of the protocol stack.

8. The device according to claim 1 or 4, wherein The response descriptor includes a general packet descriptor.

9. The device according to claim 8, wherein, The response descriptor is configured to be used by the first layer of the protocol stack and at least one other layer of the protocol stack.

10. The device according to claim 9, wherein, The response descriptor is configured to be used by the first layer of the protocol stack and at least three other layers of the protocol stack.

11. The apparatus according to claim 7, wherein, The life cycle of the updated command descriptor corresponds to all layers of the packet passing through the protocol stack.

12. The device according to claim 1 or 4 or 5 or 6 or 7 or 9 or 10 or 11, wherein, The microcontroller is configured to: Instantiate a new command descriptor or update the command descriptor for the packet at a second layer of the protocol stack; And Pass a command pointer pointing to the new command descriptor or the command pointer pointing to the updated command descriptor to the integrated circuit.

13. A method for descriptor processing, comprising: Instantiating, by a microcontroller of a node, a command descriptor for a command of a packet at a first layer of a protocol stack; Passing a command pointer pointing to the command descriptor from the microcontroller of the node to an integrated circuit of the node; Locating, by the integrated circuit, the command descriptor; And Processing, by the integrated circuit, the command; Instantiating, by the integrated circuit, a response descriptor or updating the command descriptor for use as the response descriptor; Passing a response pointer pointing to the response descriptor to the microcontroller.

14. The method according to claim 13, wherein, The first layer includes a Media Access Control (MAC) layer.

15. The method according to claim 13 or 14, further comprising: Receiving an interrupt at the microcontroller, wherein the receipt of the interrupt is a trigger for the microcontroller to issue the command.

16. The method according to claim 15, further comprising: Receiving the response pointer; Locating, by the microcontroller, the response descriptor; And Processing, by the microcontroller, the response.

17. The method according to claim 13, wherein, The command descriptor includes a general packet descriptor.

18. The method according to claim 17, wherein, The command descriptor is configured to be used by the first layer of the protocol stack and at least one other layer of the protocol stack.

19. The method according to claim 18, wherein, The command descriptor is configured to be used by the first layer of the protocol stack and at least three other layers of the protocol stack.

20. The method according to claim 13 or 16, wherein The response descriptor includes a general packet descriptor.

21. The method according to claim 20, wherein The response descriptor is configured to be used by the first layer of the protocol stack and at least one other layer of the protocol stack.

22. The method according to claim 21, wherein, The response descriptor is configured to be used by the first layer of the protocol stack and at least three other layers of the protocol stack.

23. The method according to claim 19, wherein The life cycle of the updated command descriptor corresponds to the packet passing through all layers of the protocol stack.

24. The method according to claim 13 or 16 or 17 or 18 or 19 or 21 or 22 or 23, further comprising: Instantiating, by the microcontroller of the node, a new command descriptor in the second layer of the protocol stack or updating the command descriptor regarding the packet; And Passing, from the microcontroller of the node to the integrated circuit of the node, a command pointer pointing to the new command descriptor or the command pointer pointing to the updated command descriptor.

25. A system for descriptor processing, comprising: A command instantiation / updating module for instantiating a command descriptor for a command regarding a packet in the first layer of the protocol stack; A command pointer passing module for passing a command pointer pointing to the command descriptor; And A command lookup module for looking up the command descriptor; And A command processing module for processing the command; Wherein, the system includes a response descriptor instantiation / updating module for instantiating a response descriptor or updating the above command descriptor to be used as a response descriptor, and the system includes a response pointer passing module for passing a response pointer pointing to the response descriptor.

26. A non-transitory computer-readable medium encoding instructions that, when executed by a microcontroller of a node, perform a process for descriptor processing, the process comprising: Instantiating, by the microcontroller, a command descriptor for a command regarding a packet in the first layer of the protocol stack; And Passing, from the microcontroller to the integrated circuit of the node, a command pointer pointing to the command descriptor, Wherein, the command descriptor is configured to allow the integrated circuit to look up and process the command; Wherein, the integrated circuit is used to instantiate a response descriptor or update the command descriptor to be used as the response descriptor, and the integrated circuit is used to pass a response pointer pointing to the response descriptor to the microcontroller.

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