A memory chip and a control method of a memory chip

Abstract

The application provides a storage chip and a control method of the storage chip. The storage chip comprises a plurality of storage modules, each of the storage modules comprises a plurality of storage arrays, each of the storage arrays comprises: a first storage array, the first storage array works in a first storage mode; a second storage array, the second storage array works in a second storage mode; a control circuit connected with the first storage array and the second storage array, the control circuit is used for writing at least part of data in the second storage array into the first storage array, so that an external device reads and writes data to the first storage array; and writing at least part of data in the first storage array into the second storage array to back up data. Specifically, the external device only reads and writes the first storage array, so that the storage chip of the application has the characteristics of fast reading and writing speed and long service life, and the data in the first storage array can be backed up in the second storage array, so that the data will not be lost after power failure.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, especially to a storage chip and a control method of the storage chip. BACKGROUND

[0002] Dynamic random access memory (DRAM) stores information by the amount of charge on the capacitor in the storage unit, belongs to the volatile memory, the advantage is that the reading speed is fast, the storage unit life is almost infinite, but the disadvantage is that the storage unit needs to be refreshed constantly, and the data will be lost after power off. SUMMARY

[0003] The present application provides a storage chip and a control method of the storage chip, which has the characteristics of fast read-write speed, long service life and no data loss after power off.

[0004] In a first aspect, the present application provides a storage chip, the storage chip comprising: a plurality of storage modules, each storage module comprising a plurality of storage arrays, each storage array comprising: a first storage array, the first storage array operating in a first storage mode; a second storage array, the second storage array operating in a second storage mode; a control circuit connected to the first storage array and the second storage array, the control circuit being configured to: write at least part of data in the second storage array to the first storage array, so that an external device reads and writes data to the first storage array; and write at least part of data in the first storage array to the second storage array, so as to back up data.

[0005] The storage array comprises: a first sense amplifier connected to the first storage array and configured to read and write data of the first storage array; and a second sense amplifier connected to the second storage array and configured to read and write data of the second storage array.

[0006] The first storage array comprises: a plurality of first storage units, each first storage unit comprising: a first transistor, a control terminal of the first transistor being connected to a first word line, and a first terminal of the first transistor being connected to a first bit line; and a first capacitor, a first terminal of the first capacitor being connected to a second terminal of the first transistor, and a second terminal of the first capacitor being connected to a first control line. The second storage array comprises: a plurality of second storage units, each second storage unit comprising: a second transistor, a control terminal of the second transistor being connected to a second word line, and a second terminal of the second transistor being connected to a second bit line; and a second capacitor, a first terminal of the second capacitor being connected to a first terminal of the second transistor, and a second terminal of the second capacitor being connected to a second control line.

[0007] The memory array further comprises: a first switch circuit connected between the first sensitive amplifier and the first memory array; and a second switch circuit connected between the second sensitive amplifier and the second memory array; the first switch circuit is turned on to read data from the first memory array; and the second switch circuit is turned on to write at least part of the data in the first memory array to the second memory array.

[0008] The first switch circuit comprises: a first switch having a control end connected to the first driving line and a first end and a second end connected to the first bit line; and a second switch having a control end connected to the first driving line and a first end and a second end connected to the second bit line; and the second switch circuit comprises: a third switch having a control end connected to the second driving line and a first end and a second end connected to the first bit line; and a fourth switch having a control end connected to the second driving line and a first end and a second end connected to the second bit line.

[0009] The first sensitive amplifier comprises: a first amplifier connected to the first bit line, the second bit line and the first enable line; a third switch circuit connected to the first bit line, the second bit line, the column selection line, the first data line and the second data line; and a fourth switch circuit connected to the first bit line, the second bit line and the first pre-charge line.

[0010] The second sensitive amplifier comprises: a second amplifier connected to the first bit line, the second bit line and the second enable line; a fifth switch circuit connected to the first bit line, the second bit line, the column selection line, the third data line and the fourth data line; and a sixth switch circuit connected to the first bit line, the second bit line and the second pre-charge line; and the first data line, the second data line, the third data line and the fourth data line are connected to a common data line.

[0011] The memory module further comprises: a column circuit connected to the column selection line and the common data line; and a row circuit connected to the first word line and the second word line.

[0012] The row circuit further comprises a word line driving circuit connected to the first word line and the second word line.

[0013] In a second aspect, the application provides a control method of a memory chip, which comprises: writing at least part of data in a second memory array to a first memory array to enable an external device to read and write data to the first memory array; and writing at least part of data in the first memory array to the second memory array to perform data backup; wherein the first memory array operates in a first memory mode and the second memory array operates in a second memory mode.

[0014] The beneficial effects of the present application are different from the prior art. Each storage array in the storage chip of the present application comprises: a first storage array, the first storage array working in a first storage mode; a second storage array, the second storage array working in a second storage mode; a control circuit connected to the first storage array and the second storage array, the control circuit being configured to write at least part of data in the second storage array into the first storage array, so that an external device reads and writes data to the first storage array; and write at least part of data in the first storage array into the second storage array for data backup. Specifically, the external device only reads and writes the first storage array, so that the storage chip of the present application has the characteristics of fast read and write speed and long service life. The data in the first storage array can be backed up in the second storage array, so that the data will not be lost after power failure. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort, wherein:

[0016] Figure 1 is a structural schematic diagram of a first embodiment of the storage chip of the present application;

[0017] Figure 2 is a structural schematic diagram of a storage module BANK in Figure 2

[0018] Figure 3 is a structural schematic diagram of a first embodiment of the storage array in Figure 2

[0019] Figure 4 is a structural schematic diagram of a second embodiment of the storage array in Figure 2

[0020] Figure 5 is a connection schematic diagram of the first data line, the second data line, the third data line and the fourth data line and the common data line;

[0021] Figure 6 is a structural schematic diagram of an embodiment of the word line driving circuit;

[0022] Figure 7 is a flow schematic diagram of a first embodiment of the control method of the storage chip;

[0023] Figure 8 is a signal timing schematic diagram of reading and writing the first storage array;

[0024] ​​​Figure 9 is Figure 7 Timing diagram of step S71 in

[0025] Figure 10 is Figure 7 Timing diagram of step S72 in DETAILED DESCRIPTION

[0026] To make the technical problems solved by the present application, the technical solutions adopted and the technical effects reached more clear, the technical solutions of the embodiments of the present application will be further described in detail below with reference to the drawings.

[0027] Reference herein to "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. It is expressly understood that the embodiments described herein are merely examples from a multitude of possible embodiments which can be claimed.

[0028] The terms "first", "second", and the like in the present application are used to distinguish different objects, and are not used to describe a particular order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a list of steps or units is not limited to the listed steps or units, but can optionally further include steps or units not listed, or can optionally further include other steps or units inherent to such processes, methods, products or devices.

[0029] Please refer to Figure 1 , Figure 1 The structural schematic diagram of the first embodiment of the storage chip of the present application is shown in the figure. Specifically, the storage chip 1 includes a plurality of storage modules BANK, and each storage module BANK is independent of each other. Please refer to Figure 2 , Figure 2 The structural schematic diagram of the storage module BANK is shown in the figure. Each storage module BANK includes a plurality of storage arrays 10. Please refer to Figure 3 , Figure 3As shown in Fig. 1, a structure schematic diagram of a storage chip is provided. The storage chip comprises a first storage array 11, a second storage array 12 and a control circuit 13. The first storage array 11 works in a first storage mode, and the second storage array 12 works in a second storage mode. It can be understood that the first storage mode and the second storage mode are different. The control circuit 13 is connected to the first storage array 11 and the second storage array 12. The control circuit 13 is configured to write at least part of data in the second storage array 12 into the first storage array 11, so that an external device reads and writes data to the first storage array 11; and write at least part of data in the first storage array 11 into the second storage array 12, so as to back up data.

[0030] Specifically, please refer to Fig. 1 Figure 2 The control circuit is further connected to a column circuit COL and an XDEC circuit. The XDEC circuit is a row decoder circuit. The control circuit controls the signal of a column selection line CSL and the transmission of data on a common data line MDQ according to a row address through the XDEC circuit, and controls the word line, the sense amplifier and the data line switch according to a column address through the COL.

[0031] It should be noted that the first storage array 11 is a DRAM storage array, and the second storage array 12 is a non-volatile storage array. The DRAM stores information by the amount of charge on the capacitor in the storage unit, belongs to a volatile memory, has the advantages of fast reading speed and almost infinite storage unit life, but has the disadvantages of needing to constantly refresh the storage unit and losing data after power failure. By simultaneously providing the DRAM storage array and the non-volatile storage array on the storage chip, when the external device reads and writes data, the DRAM storage array can be directly read and written to inherit the fast reading and writing speed of the DRAM, at least part of the data stored in the DRAM storage array is written into the non-volatile storage array to back up data and avoid data loss when power failure, and at least part of the data backed up in the non-volatile storage array is written into the DRAM storage array to inherit the feature that the data in the non-volatile storage array will not be lost after power failure. Therefore, the storage chip of the present application can have the features of fast reading and writing speed, long service life and no data loss after power failure.

[0032] In the embodiment of the present application, the first storage array 11 and the second storage array 12 are provided in the same storage chip. Specifically, a plurality of storage chips are prepared on the same wafer, each of which is divided into two parts, one part is prepared for the first storage array 11, and the other part is prepared for the second storage array 12, that is, the first storage array 11 and the second storage array 12 are provided on the same plane.

[0033] In an embodiment, the second storage array 12 can be a ferroelectric random access memory (FeRAM) which is a non-volatile memory that does not lose content when power is off, has the advantages of high speed, high density, low power consumption and radiation resistance, and stores information by different polarization states of ferroelectric capacitors in storage cells.

[0034] In an embodiment of the present application, the DRAM and the FeRAM are integrated in the same chip. When an external device performs data read / write, data is directly read / written from the DRAM, and the read speed is fast. When power is off, data in the DRAM is written into the FeRAM, and the data will not be lost. After power is on or a user instruction is received, data in the FeRAM is written into the DRAM, so as to read / write data from the DRAM. It should be noted that since the read / write speed of the FeRAM is much slower than that of the DRAM, in a preferred embodiment, a user can issue an instruction in advance to write data in the FeRAM into the DRAM. Specifically, the instruction can be issued in idle time (the idle time refers to time when the DRAM is not read / written). Compared with writing data in the FeRAM into the DRAM when the DRAM is read / written, the read / write time is greatly reduced, and the read / write speed is improved.

[0035] In another embodiment of the present application, the second storage array 12 can also be other capacitive non-volatile memory, which is not limited herein.

[0036] Please refer to Figure 4 , Figure 4 FIG. 2 is a structural schematic diagram of a second embodiment of a storage array of the present application. The second embodiment is based on the first embodiment shown in FIG. 1. Figure 3 The storage array 10 further includes a first sensitive amplifier 14 and a second sensitive amplifier 15. The first sensitive amplifier 14 is connected to the first storage array 11 and is used for data read / write of the first storage array 11. The second sensitive amplifier 15 is connected to the second storage array 12 and is used for data read / write of the second storage array 12.

[0037] It should be noted that the storage array 10 includes a plurality of first storage arrays 11 and a plurality of second storage arrays 12. Each first storage array 11 includes a plurality of first storage cells 111, and each second storage array 12 includes a plurality of second storage cells 121.

[0038] As shown in Figure 4As shown, each first storage unit 111 includes a first transistor Q1 and a first capacitor C1. The control terminal of the first transistor Q1 is connected to the first word line WLA, and the first terminal of the first transistor Q1 is connected to the first bit line BL. The first terminal of the first capacitor C1 is connected to the second terminal of the first transistor Q1, and the second terminal of the first capacitor C1 is connected to the first control line PLA. Each second storage unit 121 includes a second transistor Q2 and a second capacitor C2. The control terminal of the second transistor Q2 is connected to the second word line WLB, and the second terminal of the second transistor Q2 is connected to the second bit line BLN. The first terminal of the second capacitor C2 is connected to the first terminal of the second transistor Q2, and the second terminal of the second capacitor C2 is connected to the second control line PLB.

[0039] Please continue to see Figure 4 The first sensitive amplifier 14 includes a first amplifier 141, a third switch circuit 142, and a fourth switch circuit 143. The first amplifier 141 is connected to the first bit line BL, the second bit line BLN, and the first enable line SEA. The third switch circuit 142 is connected to the first bit line BL, the second bit line BLN, the column selection line CSL, the first data line LA, and the second data line LAN.

[0040] The fourth switch circuit 143 is connected to the first bit line BL, the second bit line BLN, and the first pre-charge line EQL. Specifically, the third switch circuit 142 includes a switch T1 and a switch T2. The first terminal of the switch T1 is connected to the first bit line BL, the second terminal of the switch T1 is connected to the first data line LA, and the control terminal of the switch T1 is connected to the column selection line CSL. The fourth switch circuit 143 includes a switch T3 and a switch T4. The first terminal of the switch T3 is connected to the first bit line BL, and the control terminal of the switch T3 is connected to the first pre-charge line EQL. The first terminal of the switch T4 is connected to the second terminal of the switch T3, the second terminal of the switch T4 is connected to the second bit line BLN, and the control terminal of the switch T4 is connected to the first pre-charge line EQL.

[0041] The second sensitive amplifier 15 comprises a second amplifier 151, a fifth switch circuit 152 and a sixth switch circuit 153. The second amplifier 151 is connected with the first bit line BL, the second bit line BLN and the second enable line SEB. The fifth switch circuit 152 is connected with the first bit line BL, the second bit line BLN, the column selection line CSL, the third data line LB and the fourth data line LBN. The sixth switch circuit 153 is connected with the first bit line BL, the second bit line BLN and the second pre-charge line RST. Specifically, the fifth switch circuit 152 comprises a switch T5 and a switch T6. The first end of the switch T5 is connected with the first bit line BL, the second end of the switch T5 is connected with the third data line LB, and the control end of the switch T5 is connected with the column selection line CSL. The first end of the switch T6 is connected with the fourth data line LBN, the second end of the switch T6 is connected with the second bit line BLN, and the control end of the switch T6 is connected with the column selection line CSL. The sixth switch circuit 153 comprises a switch T7 and a switch T8. The first end of the switch T7 is connected with the first bit line BL, and the control end of the switch T7 is connected with the second pre-charge line RST. The first end of the switch T8 is connected with the second end of the switch T7, the second end of the switch T8 is connected with the second bit line BLN, and the control end of the switch T8 is connected with the second pre-charge line RST.

[0042] In an embodiment of the present application, the first data line LA, the second data line LAN, the third data line LB and the fourth data line LBN are connected with a common data line MDQ / MDQN. Specifically, please refer to Figure 5 , Figure 5 are part of the first sensitive amplifier 14 and the second sensitive amplifier 15. Specifically, the first data line LA is connected with the common data line MDQ through a switch N1, and the second data line LAN is connected with the common data line MDQN through a switch N2. The first end of the switch N1 is connected with the first data line LA, the second end of the switch N1 is connected with the common data line MDQN, and the control end of the switch N1 receives a signal MAS, which is used to control the conduction and the non-conduction of the switch N1. The first end of the switch N2 is connected with the second data line LAN, the second end of the switch N2 is connected with the common data line MDQN, and the control end of the switch N2 receives the signal MAS, which is used to control the conduction and the non-conduction of the switch N2. That is, the switch N1 and the switch N2 are simultaneously conducted and non-conducted. The third data line LB is connected with the common data line MDQ through a switch N3, and the fourth data line LBN is connected with the common data line MDQN through a switch N4. The first end of the switch N3 is connected with the third data line LB, the second end of the switch N3 is connected with the common data line MDQN, and the control end of the switch N3 receives a signal MBS, which is used to control the conduction and the non-conduction of the switch N3. The first end of the switch N4 is connected with the fourth data line LBN, the second end of the switch N4 is connected with the common data line MDQN, and the control end of the switch N4 receives the signal MBS, which is used to control the conduction and the non-conduction of the switch N4. That is, the switch N3 and the switch N4 are simultaneously conducted and non-conducted.

[0043] Please continue to see Figure 4 , the storage array 10 further comprises a first switch circuit 16 and a second switch circuit 17. Among them, the first switch circuit 16 is connected between the first sensitive amplifier 14 and the first storage array 11; the second switch circuit 17 is connected between the second sensitive amplifier 15 and the second storage array 12. The first switch circuit 16 is turned on, and the data in the first storage array 11 is read; the second switch circuit 17 is turned on, and at least part of the data in the first storage array 11 is written into the second storage array 12. Specifically, the first switch circuit 16 comprises: a first switch M1 and a second switch M2, the control end of the first switch M1 is connected with the first drive line SAT, and the first end of the first switch M2 and the second end of the first switch M2 are connected with the first bit line BL. The control end of the second switch M2 is connected with the first drive line SAT, and the first end of the second switch M2 and the second end of the second switch M2 are connected with the second bit line BLN. The second switch circuit 17 comprises: a third switch M3 and a fourth switch M4, the control end of the third switch M3 is connected with the second drive line SBC, and the first end of the third switch M3 and the second end of the third switch M3 are connected with the first bit line BL; the control end of the fourth switch M4 is connected with the second drive line SBC, and the first end of the fourth switch M4 and the second end of the fourth switch M4 are connected with the second bit line BLN.

[0044] In an embodiment, as shown in Figure 2 , the storage array 10 further comprises a row circuit and a column circuit 19, wherein the row circuit is connected with the first word line WLA and the second word line WLB. The row circuit comprises a word line drive circuit 18 and XDEC, please see Figure 6 , Figure 6Fig. 1 is a schematic diagram of a structure of an embodiment of a word line driving circuit, which includes switch Al, switch A2 and switch A3. The first end of switch Al receives signal WLDV, and the second end of switch Al is connected to word line WL. The first end of switch A2 is connected to word line WL, and the control end of switch A2 and the control end of switch Al receive global word line signal MWLN. The second end of switch A2 is connected to word line low. The first end of switch A3 is connected to word line WL, and the second end of switch A3 is connected to word line low. The control end of switch A3 receives signal WLRST. When signal MWLN is valid, WLDV is valid and WLRST is invalid, word line WL is valid, otherwise, WL is invalid and at low level. It should be noted that word line WL is connected to first word line WLA and second word line WLB. The word line of memory array 10, the first enable line of first amplifier and the second enable line of second amplifier are connected to XDEC circuit, which generates an enable signal and transmits the enable signal to first amplifier and second amplifier by using the first enable line and the second enable line. XDEC circuit is connected to and controlled by control circuit 13, and XDEC circuit is a row decoder circuit. Column circuit 19 is connected to column selection line CSL and common data line MDQ / MDQN.

[0045] The memory chip of the present application has two working modes, i.e., working in first memory array 11 and working in second memory array 12. When working in first memory array 11, the signal output by first driving line SAT is valid, switch Ml and switch M2 are turned on, the signal output by second driving line SBC is invalid, and switch M3 and switch M4 are turned off. At this time, first memory array 11 is connected to first bit line BL and second bit line BLN, and read / write operation can be performed on first memory cell 111 controlled by first word line WLA. Assuming that first memory array 11 is DRAM, during activation operation, the signal output by first pre-charge line EQL is invalid, first word line WLA is opened, and the potential of first bit line BL changes according to the amount of stored charge in first memory cell 111, while second bit line BLN remains unchanged as a reference potential. With the establishment of voltage difference between first bit line BL and second bit line BLN, the signal output by first enable line SEA is valid, and first amplifier 141 starts to work, amplifies the voltage difference between first bit line BL and second bit line BLN and completes the write-back of the capacitance of first memory cell 111.

[0046] When working at the second storage array 12, the signal outputted by the first driving line SAT is invalid, the switch M1 and the switch M2 are cut off, the signal outputted by the second driving line SBC is valid, and the switch M3 and the switch M4 are turned on. At this time, the second storage array 12 is connected to the first bit line BL and the second bit line BLN, and the read-write operation can be performed on the second storage unit 121 controlled by the second word line WLB. Assuming that the second storage array 12 is FeRAM, in the read operation, the signal outputted by the second pre-charge line RST is invalid, the second word line WLB is opened, the signal outputted by the second control line PLB is raised, and the second storage unit 121 generates different amounts of polarization charges on the second bit line BLN according to the polarization state of the ferroelectric capacitor, causing the change of its own potential, while the first bit line BL is the reference potential. With the voltage difference between the first bit line BL and the second bit line BLN established, the signal outputted by the second enable line SEB is valid, and the second amplifier starts to work 151 to amplify the voltage difference between the first bit line BL and the second bit line BLN.

[0047] In an embodiment of the present application, the DRAM and the FeRAM are integrated in the same chip, and when the external device performs data read-write, the data is directly read and written from the DRAM, the reading speed is fast, when power off, the data in the DRAM is written into the FeRAM, the data will not be lost, and after power on or receiving the user instruction, the data in the FeRAM is written into the DRAM, so as to read and write the data from the DRAM. It should be noted that since the read-write speed of the FeRAM is much slower than that of the DRAM, in a preferred embodiment, the user can issue an instruction in advance to write the data of the FeRAM into the DRAM. Specifically, the instruction can be issued to write the data of the FeRAM into the DRAM in the idle time (the idle time refers to the time when the DRAM is not read and written). Compared with writing the data of the FeRAM into the DRAM when the DRAM is read and written, the read-write time is greatly reduced, and the read-write speed is improved.

[0048] Please refer to Figure 7 The flowchart of the first embodiment of the control method of the storage chip of the present application is shown, and specifically includes:

[0049] Step S71: Write at least part of the data in the second storage array into the first storage array, so that the external device performs data read-write on the first storage array.

[0050] Specifically, the first storage array works in the first storage mode, and the second storage array works in the second storage mode.

[0051] The control method of the present application further includes performing data read-write on the first storage array. The first storage array can be DRAM. That is, performing data read-write on the first storage array is to perform data read-write on the DRAM, which has the advantages of fast read-write speed and long capacitor life.

[0052] At this time, please combine Figure 8 , Figure 8 is a signal timing diagram for reading and writing the first storage array. The signal output by the first drive line SAT is valid, and the switches M1 and M2 are turned on, so that the first storage array is connected to the first sense amplifier; the signal output by the second drive line SBC is invalid, and the switches M3 and M4 are turned off, so that the second storage array is disconnected from the second sense amplifier. The read / write instruction is received, and the selected page is activated according to the row address in the read / write instruction, which specifically includes:

[0053] In the t1 stage, the signal output by the first pre-charge line EQL is valid, and the switches T3 and T4 are turned on, so that the first bit line BL and the second bit line BLN are connected to the reference potential.

[0054] In the t2 stage, the signal output by the first pre-charge line EQL is invalid, and the first word line WLA is opened, so that the potential of the first bit line BL changes according to the amount of stored charge in the first storage unit, while the second bit line BLN remains unchanged as the reference potential.

[0055] In the t3 stage, as the voltage difference between the first bit line BL and the second bit line BLN is established, the signal output by the first enable line SEA is valid. The first amplifier starts to work, amplifies the voltage difference between the first bit line BL and the second bit line BLN, and completes the write-back of the capacitor in the first storage unit, at which time the first amplifier serves as a data buffer for the selected page. According to the column address in the read / write instruction, a specific first amplifier is selected, and data is read and written, which specifically includes: the signal MSA is valid, the switches N1 and N2 are turned on, the first data line LA and the second data line LAN of the first amplifier are connected to the common data line MDQ / MDQN through the switches N1 and N2, the signal output by the column selection CSL is valid, the switches T1 and T2 are turned on, and the selected first amplifier is connected to the first data line LA and the second data line LAN through the switches T1 and T2. The row circuit accesses the data in the first amplifier through the common data line MDQ / MDQN, the first data line LA and the second data line LAN.

[0056] In the t4 stage, after the first amplifier completes the transmission and write-back of the data, the signal output by the first enable line SEA is invalid, the signal output by the first pre-charge line EQL is valid, and the first amplifier, the first bit line BL and the second bit line BLN are reset to the initial state.

[0057] At power-up, or when the user controls to write at least part of the data in the second storage array to the first storage array, so that the external device reads and writes the first storage array. Specifically, this step is completed by the read operation of the second storage array and the write operation of the first storage array. For details, please refer to Figure 9 , Figure 9The signal timing diagram of step S71 is shown in the figure. Firstly, the read operation of the second storage array, during the read operation of the second storage array, the signal output by the first driving line SAT is invalid, the switches M1 and M2 are turned off, the first sensitive amplifier is disconnected with the first storage array; the signal output by the second driving line SBC is invalid, the switches M3 and M4 are turned on, the second sensitive amplifier is connected with the second storage array. Specifically, it includes:

[0058] In the t1 stage, the signal output by the second pre-charge line RST is valid, the first bit line BL and the second bit line BLN are reset to low level, and then RST is invalid.

[0059] In the t2 stage, the second word line WLB is opened, the signal output by the second control line PLB is raised, the second storage unit generates different amounts of polarization charges on the second bit line BLN according to the polarization state of the ferroelectric capacitor, causing the change of its own potential, while the first bit line BL is the reference potential, and the voltage difference between the first bit line BL and the second bit line BLN is established.

[0060] In the t3 stage, the signal output by the second enable line SEB is valid, and the second amplifier starts to work to amplify the voltage difference between the first bit line BL and the second bit line BLN.

[0061] In the t4 stage, the signal output by the second control line PLB is lowered, if the signal output by the first bit line BL is high, the polarization direction of the ferroelectric capacitor in the second storage unit is rewritten, recorded as data "1"; if the signal output by the first bit line BL is low, the polarization direction of the ferroelectric capacitor in the second storage unit remains unchanged, still as data "0".

[0062] In the t5 stage, the second word line WLB is closed, and the second storage array is completed, at this time the second amplifier is still opened, and the first bit line level represents the corresponding data "0" and "1".

[0063] During the write operation of the first storage array, specifically, it includes:

[0064] In the t6 stage, the first word line WLA is opened, the first storage unit of the first storage array is connected with the first bit line BL, and the capacitor in the first storage unit is charged according to the level of the first bit line BL.

[0065] In the t7 stage, the first word line WLA is closed, the first storage array is completed, then the signal output by the second enable line SEB is invalid, the second amplifier is closed, and the signal output by the second pre-charge line RST is valid, the second amplifier, the first bit line BL and the second bit line BLN are reset to the initial state.

[0066] Step S72: write at least part of the data in the first storage array into the second storage array to perform data backup.

[0067] The at least part of the data in the first storage array is written into the second storage array for data backup. Specifically, in an embodiment, the at least part of the data in the first storage array is written into the second storage array for data backup after power-off or under user control. The writing of the at least part of the data in the first storage array into the second storage array comprises a read operation of the first storage array and a write operation of the second storage array.

[0068] In the read operation of the first storage array, the data is first read from the storage unit of the first storage array to the first amplifier, in the process, the signal output by the first driving line SAT is active, the switches M1 and M2 are turned on, the first storage array is connected to the first sensitive amplifier; the signal output by the second driving line SBC is inactive, the switches M3 and M4 are turned off, and the second storage array is disconnected from the second sensitive amplifier. For details, please refer to Figure 10 , Figure 10 The signal timing diagram of step S72 is shown in the following table, which specifically comprises:

[0069] In the t1 stage, the signal output by the first pre-charge line EQL is active, the switches T3 and T4 are turned on, and the first bit line BL and the second bit line BLN are connected to the reference potential.

[0070] In the t2 stage, the signal output by the first pre-charge line EQL is inactive, the row circuit activates the selected first word line WLA according to the row address, and the potential of the first bit line BL changes according to the amount of charge stored in the first storage unit, while the second bit line BLN remains unchanged as a reference voltage.

[0071] In the t3 stage, with the establishment of the voltage difference between the first bit line BL and the second bit line BLN, the signal output by the first enable line SEA is active. The first amplifier starts to work, amplifies the voltage difference between the first bit line BL and the second bit line BLN, and completes the write-back to the capacitor of the first storage unit, and then the first word line WLA is closed.

[0072] Then, the data is moved from the first amplifier to the second amplifier, in the process, the signal output by the first driving line SAT is inactive, the switches M1 and M2 are turned off, the first storage array is disconnected from the first sensitive amplifier; the signal output by the second driving line SBC is active, the switches M3 and M4 are turned on, and the second storage array is connected to the second sensitive amplifier.

[0073] At the t4 stage, the signal outputted by the first enable line SEA is invalid, the first amplifier is closed, the first bit line BL and the second bit line BLN are disconnected from the first amplifier and connected to the second amplifier. At this time, the first bit line BL and the second bit line BLN still keep high or low. The signal outputted by the second enable line SEB is valid, the second amplifier starts to work, the data is moved, and the voltage difference between the first bit line BL and the second bit line BLN is further amplified to high or low required by the second storage array operation.

[0074] Finally, the data is written from the second amplifier to the second storage array, specifically including:

[0075] At the t5 stage, the second word line WLB is opened, and the signal outputted by the second control line PLB is raised. If the first bit line BL is low, the polarization direction of the ferroelectric capacitor in the second storage unit is changed, recorded as data "0".

[0076] At the t6 stage, the signal outputted by the second control line PLB is lowered. If the first bit line BL is high, the polarization direction of the ferroelectric capacitor in the second storage unit is changed to another direction, recorded as "1".

[0077] At the t7 stage, the second word line WLB is closed, the signal outputted by the second enable line SEB is invalid, the second amplifier is closed, and the signal outputted by the second pre-charge line RST is valid, so as to reset the second amplifier, the first bit line BL and the second bit line BLN to the initial state.

[0078] The control method of the storage chip combines two different modes of storage arrays together, which has the characteristics of low power consumption, specifically represented as not needing to refresh after saving data in the second storage array; the characteristics of fast read-write speed, specifically represented as reading and writing the first storage array faster than reading and writing the second storage array; the characteristics of long service life, specifically represented as most data is completed in the working mode of the first storage array, which does not damage the capacitor of the second storage array, and realizes the comparable service life with the first storage array; the characteristics of non-volatility, specifically represented as the data in the first storage array can still be saved in the second storage array after power off, and restored to the first storage array after power on. Further, it also has the advantages of low delay and high bandwidth. The low delay is specifically represented as the automatic continuous operation of the first storage array and the second storage array in the storage chip, without the need for user intervention, and the delay is low. The high bandwidth is specifically represented as the data is moved between the first amplifier of the first storage array and the second amplifier of the second storage array in page units, and only one operation is needed to complete the movement of all data in the entire page.

[0079] The above merely illustrates the embodiments of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation using the content of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A memory chip, characterized by, The application relates to a storage chip, comprising: a plurality of storage modules, each of which comprises a plurality of storage arrays, each of which comprises: a first storage array operating in a first storage mode; a second storage array operating in a second storage mode; a control circuit connected to the first storage array and the second storage array, which is used to write at least part of data in the second storage array into the first storage array so that an external device reads and writes data in the first storage array, and write at least part of data in the first storage array into the second storage array for data backup; the storage array comprises a first sensitive amplifier and a second sensitive amplifier, the first sensitive amplifier is connected to the first storage array and is used for reading and writing data in the first storage array, and the second sensitive amplifier is connected to the second storage array and is used for reading and writing data in the second storage array; the first sensitive amplifier comprises a first amplifier connected to a first bit line, a second bit line and a first enable line, a third switch circuit connected to the first bit line, the second bit line, a column selection line, a first data line and a second data line, and a fourth switch circuit connected to the first bit line, the second bit line and a first pre-charge line.

2. The storage chip according to claim 1, wherein the first storage array comprises a plurality of first storage units, each of which comprises: a first transistor with a control end connected to a first word line and a first end connected to the first bit line; a first capacitor with a first end connected to a second end of the first transistor and a second end connected to a first control line; the second storage array comprises a plurality of second storage units, each of which comprises: a second transistor with a control end connected to a second word line and a second end connected to the second bit line; a second capacitor with a first end connected to a first end of the second transistor and a second end connected to a second control line.

3. The memory chip of claim 2, wherein, The storage array further comprises: a first switch circuit connected between the first sensitive amplifier and the first storage array; a second switch circuit connected between the second sensitive amplifier and the second storage array; when the first switch circuit is turned on, data in the first storage array is read; and when the second switch circuit is turned on, at least part of data in the first storage array is written into the second storage array.

4. The memory chip of claim 3, wherein, The first switch circuit comprises: a first switch with a control end connected to a first drive line and a first end and a second end connected to the first bit line; a second switch with a control end connected to the first drive line and a first end and a second end connected to the second bit line; the second switch circuit comprises: a third switch with a control end connected to a second drive line and a first end and a second end connected to the second bit line. A third switch, a control end of the third switch being connected to a second driving line, a first end of the third switch and a second end of the third switch being connected to the first bit line; A fourth switch, a control end of the fourth switch being connected to the second driving line, a first end of the fourth switch and a second end of the fourth switch being connected to the second bit line.

5. The memory chip of claim 4, wherein, The second sensitive amplifier comprises: A second amplifier, the second amplifier being connected to the first bit line, the second bit line and a second enable line; A fifth switch circuit, the fifth switch circuit being connected to the first bit line, the second bit line, a column selection line, a third data line and a fourth data line; A sixth switch circuit, the sixth switch circuit being connected to the first bit line, the second bit line and a second pre-charge line; The first data line, the second data line, the third data line and the fourth data line are connected to a common data line.

6. The memory chip of claim 5, wherein, The storage module further comprises: A column circuit, the column circuit being connected to the column selection line and the common data line; A row circuit, the row circuit being connected to the first word line and the second word line.

7. The memory chip of claim 6, wherein, The row circuit further comprises a word line driving circuit, the word line driving circuit being connected to the first word line and the second word line.

8. A control method of a memory chip, characterized by, The method comprises: Writing at least part of data in a second storage array of a storage array into a first storage array of the storage array, so that an external device reads and writes data to the first storage array; Writing at least part of data in the first storage array into the second storage array, for data backup; The first storage array works in a first storage mode, and the second storage array works in a second storage mode; The storage array comprises a first sensitive amplifier and a second sensitive amplifier, the first sensitive amplifier being connected to the first storage array and being used for reading and writing data of the first storage array, and the second sensitive amplifier being connected to the second storage array and being used for reading and writing data of the second storage array. The first sensitive amplifier comprises: a first amplifier, the first amplifier being connected to a first bit line, a second bit line and a first enable line; a third switch circuit, the third switch circuit being connected to the first bit line, the second bit line, a column selection line, a first data line and a second data line; and a fourth switch circuit, the fourth switch circuit being connected to the first bit line, the second bit line and a first pre-charge line.

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