Three-dimensional semiconductor structure and method of manufacturing the same

Abstract

A three-dimensional semiconductor structure and a method of fabricating the same. The method of fabricating the three-dimensional semiconductor structure includes providing a substrate, forming a plurality of semiconductor layers stacked along a first direction on the substrate, the first direction being a direction perpendicular to a top surface of the substrate, and forming a first conductive layer extending along the first direction, the first conductive layer including a plurality of gates stacked along the first direction, the gates surrounding the semiconductor layers. The method improves the density and performance of semiconductor devices.

Description

Technical Field

[0001] This application relates to the field of memory, and more particularly to a three-dimensional semiconductor structure and its fabrication method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, consisting of many repeating memory cells. Each memory cell typically includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the transistor to turn on or off, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line.

[0003] In the current 3D DRAM manufacturing process, transistors are usually arranged in a multi-layered, lateral transistor structure, but the density and performance of 3D DRAM devices still need to be improved. Summary of the Invention

[0004] Some embodiments of this application provide a method for fabricating a three-dimensional semiconductor structure, including:

[0005] Provide a base;

[0006] Multiple semiconductor layers are formed on the substrate and stacked along a first direction, wherein the first direction is perpendicular to the top surface of the substrate;

[0007] A first conductive layer is formed extending along a first direction, the first conductive layer including a plurality of gates stacked along the first direction, the gates surrounding the semiconductor layer.

[0008] In some embodiments, the process of forming a plurality of semiconductor layers stacked along a first direction includes:

[0009] A stacked structure in which an isolation layer and a first sacrificial layer are alternately layered is formed on the substrate;

[0010] The stacked structure is etched along a second direction to form a plurality of parallel first trenches penetrating the stacked structure. The first trenches extend along the second direction, which is a direction parallel to the top surface of the substrate.

[0011] The second sacrificial layer is filled into the plurality of parallel first trenches;

[0012] A portion of the second sacrificial layer and a portion of the first sacrificial layer in the remaining stacked structure are removed along a third direction, while retaining the isolation layer in the remaining stacked structure. A second trench is formed at the location where the second sacrificial layer is removed, penetrating the stacked structure along the first direction. A cavity is formed at the location where the first sacrificial layer is removed, extending along the third direction. The cavity communicates with the second trench. The third direction is a direction perpendicular to the second direction and parallel to the top surface of the substrate.

[0013] The cavity is filled with semiconductor material to form the semiconductor layer.

[0014] In some embodiments, the process of filling the cavity with semiconductor material to form the semiconductor layer is as follows:

[0015] A semiconductor material layer is formed on the sidewalls and bottom surface of the second trench and in the cavity, the semiconductor material layer filling the cavity;

[0016] The semiconductor material layer on the sidewalls and bottom surface of the second trench is removed by a maskless etching process, while the semiconductor material layer in the cavity is retained, and the semiconductor layer is formed in the cavity.

[0017] In some embodiments, the material of the semiconductor layer includes: IGZO, doped amorphous silicon, doped polycrystalline silicon, doped germanium silicon, In2O3, Ga2O3, ZnO, InGaZnO, InZnO, InGaO, GaZnO, InAlO, InSnO, InMgO, GaZnMgO, GaZnSnO, GaAlZnO, GaAlSnO, HfZnO, HfInZnO, HfAlGaZnO, InMgZnO, NbO, NiO, CoO, SnO, Cu2O, AgAlO, CuAlO3, AlScOC, Sr3BPO3, La2SiO4Se, LaCuSe, Rb2Sn2O3, La2O2S2, K2Sn2O3, Na2FeOSe2, or ZnRh2O4. In some embodiments, the process of the first conductive layer includes:

[0018] Remove the isolation layer between adjacent semiconductor layers, leaving the semiconductor layers suspended and exposing their surfaces;

[0019] A conductive material is deposited on the surface of the semiconductor layer to form the first conductive layer extending along the first direction.

[0020] In some embodiments, the first sacrificial layer and the second sacrificial layer are made of the same material, and the first sacrificial layer and the second sacrificial layer are made of a different material than the isolation layer.

[0021] In some embodiments, the material of the isolation layer is one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide, and the materials of the first sacrificial layer and the second sacrificial layer are one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, amorphous silicon, amorphous carbon, and polycrystalline silicon.

[0022] In some embodiments, the process of removing a portion of the second sacrificial layer and a portion of the first sacrificial layer in the remaining stacked structure along a third direction, while retaining the isolation layer in the remaining stacked structure, includes:

[0023] The second sacrificial layer is etched downward along the first direction to form two first openings in the second sacrificial layer;

[0024] A portion of the first sacrificial layer in the remaining stacked structure is etched along the first opening, retaining the isolation layer in the remaining stacked structure, so as to form two third trenches extending in the third direction in the first sacrificial layer accordingly.

[0025] The first opening and the third groove are filled with support material to form two first support layers;

[0026] The second sacrificial layer located between the two first support layers is etched downward again along the first direction to form the second trench in the second sacrificial layer, the second trench being located between the first support layers;

[0027] A portion of the first sacrificial layer in the remaining stacked structure is etched along the second trench to form the cavity in the first sacrificial layer, the cavity being located between the isolation layers.

[0028] In some embodiments, after forming the first conductive layer, the method further includes:

[0029] Remove the first support layer to expose the first opening and the third trench;

[0030] Semiconductor material is deposited in the first opening and the third trench, and the semiconductor material in the opening is etched back to form a source and a drain connected to the semiconductor layer at both ends of the semiconductor layer.

[0031] In some embodiments, a plurality of second conductive layers are formed stacked along a first direction, the extension direction of the second conductive layers being perpendicular to the extension direction of the semiconductor layers and parallel to the top surface of the substrate.

[0032] In some embodiments, prior to forming the first conductive layer, the semiconductor layer is further subjected to a circular arcing process.

[0033] In some embodiments, after the first conductive layer is formed, an isolation dielectric layer is formed to fill the space between adjacent first conductive layers.

[0034] In some embodiments, the gate includes a gate dielectric layer located on the surface of the semiconductor layer and a first conductive layer located on the gate dielectric layer surrounding the semiconductor layer.

[0035] Some embodiments of this application also provide a three-dimensional semiconductor structure, including:

[0036] Base;

[0037] A plurality of semiconductor layers are stacked on the substrate along a first direction, wherein the first direction is perpendicular to the top surface of the substrate;

[0038] A first conductive layer is located on the substrate and extends along a first direction, the first conductive layer including a plurality of gates stacked along the first direction, the first conductive layer surrounding the semiconductor layer.

[0039] In some embodiments, the three-dimensional semiconductor structure further includes a source and a drain located at opposite ends of the semiconductor layer along its extension direction and connected to the semiconductor layer; a plurality of second conductive layers stacked on a substrate along a first direction, the extension direction of the second conductive layers being perpendicular to the extension direction of the semiconductor layer and parallel to the top surface of the substrate, the second conductive layers being connected to the drain / source; and a capacitor connected to the source / drain.

[0040] The method for fabricating a three-dimensional semiconductor structure in some of the foregoing embodiments of this application involves providing a substrate and then forming a plurality of semiconductor layers stacked along a first direction on the substrate, the first direction being a direction perpendicular to the top surface of the substrate; and forming a first conductive layer extending along the first direction, the first conductive layer including a plurality of gates stacked along the first direction, the gates surrounding the semiconductor layer. Embodiments of this application form a self-aligned first conductive layer along a first direction perpendicular to the top surface of the substrate using, for example, an atomic layer deposition process. The first conductive layer includes a plurality of stacked gates, which are completed in a single step, greatly increasing the density and performance of the semiconductor device. Attached Figure Description

[0041] Figure 1-56 This is a schematic diagram of the fabrication process of the three-dimensional semiconductor structure in some embodiments of this application;

[0042] Figure 57 This is a schematic flowchart illustrating the fabrication process of a three-dimensional semiconductor structure according to some embodiments of this application. Detailed Implementation

[0043] The specific embodiments of this application will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this application in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this application. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0044] In some embodiments of this application, a method for fabricating a three-dimensional semiconductor structure is first provided, with reference to... Figure 57 The steps include:

[0045] S101 provides the substrate;

[0046] S102, a plurality of semiconductor layers stacked along a first direction are formed on the substrate, wherein the first direction is perpendicular to the top surface of the substrate;

[0047] S103, forming a first conductive layer extending along a first direction, the first conductive layer including a plurality of gates stacked along the first direction, the first conductive layer surrounding the semiconductor layer.

[0048] The aforementioned process will now be described in detail with reference to the accompanying drawings.

[0049] Proceed to step S101, providing the substrate. Please refer to the following for details. Figures 1-4 ,in Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 3 for Figure 1 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 4 for Figure 1 A schematic diagram of the cross-sectional structure along the cutting line CC1, providing a substrate 200.

[0050] The substrate 200 can be made of single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other group III-V compounds. In this embodiment, the substrate 200 is made of single-crystal silicon (Si).

[0051] In step S102, a plurality of semiconductor layers stacked along a first direction are formed on the substrate, wherein the first direction is perpendicular to the top surface of the substrate. The process of forming the semiconductor layers is described in detail below.

[0052] Continue to refer to Figures 1-4 A stacked structure 201 is formed on the substrate 200, in which an isolation layer 202 and a first sacrificial layer 203 are alternately stacked.

[0053] The stacked structure 201 includes alternately stacked isolation layers 202 and first sacrificial layers 203. The alternating stacking of isolation layers 202 and first sacrificial layers 203 means that after forming an isolation layer 202, a first sacrificial layer is formed on the surface of the first sacrificial layer 202, and then the steps of forming isolation layers 202 and first sacrificial layers 203 on the isolation layers 202 are repeated cyclically. The number of isolation layers 202 and first sacrificial layers 203 can be determined according to actual needs. In this embodiment, four isolation layers 202 and three first sacrificial layers 203 are used as an example, and the bottom and top layers of the stacked structure 201 are both isolation layers 202. In other embodiments, the number of isolation layers 202 and first sacrificial layers 203 can be other numbers.

[0054] The isolation layer 202 and the first sacrificial layer 203 are formed by deposition processes.

[0055] The isolation layer 202 is used for electrical isolation between devices. The first sacrificial layer 203 will be subsequently removed to form the corresponding component in the 3D DARM. The first sacrificial layer 203 is made of a different material than the isolation layer 202 so that when the first sacrificial layer 203 is subsequently removed, the first sacrificial layer 203 has a high etch selectivity (etch selectivity greater than 2:1) relative to the isolation layer 202, so that the isolation layer 202 is not etched or is etched by a small amount while the first sacrificial layer 203 is being removed.

[0056] In some embodiments, the material of the isolation layer 202 is one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride, and the material of the first sacrificial layer 203 is one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, amorphous silicon, amorphous carbon, and polycrystalline silicon. In this embodiment, the material of the isolation layer is silicon oxide, and the material of the first sacrificial layer 203 is silicon nitride.

[0057] refer to Figures 5-8 ,in Figure 6 for Figure 5 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 7 for Figure 5 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 8 for Figure 5 A cross-sectional view along the cutting line CC1 shows the stacked structure 201 etched along the second direction, forming a plurality of parallel first trenches 204 penetrating the stacked structure 201. The first trenches 204 extend along the second direction, which is parallel to the top surface of the substrate 200.

[0058] The first trench 204 penetrates the stacked structure 201. The plurality of first trenches 204 are parallel to each other, and the formed first trenches 204 extend along a second direction. In this application, the direction of the cutting line AA1 is parallel to the second direction.

[0059] In some embodiments, when forming the first trench 204, the substrate 200 is over-etched such that the bottom of the first trench 204 is located in the substrate 200.

[0060] In some embodiments, before etching the stacked structure 201, a patterned first mask layer (not shown in the figure) is formed on the surface of the stacked structure 201. The patterned first mask layer has a plurality of openings extending in a second direction, and the positions of the plurality of openings correspond to the positions of a plurality of first trenches to be formed. Using the patterned first mask layer as a mask, the stacked structure 201 is etched along the openings to form a plurality of parallel first trenches 204 extending in the second direction in the stacked structure. The patterned first mask layer is then removed.

[0061] In some embodiments, etching the stacked structure 201 can be performed using an anisotropic dry etching process, such as anisotropic plasma etching.

[0062] refer to Figures 9-12 ,in Figure 10 for Figure 9 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 11 for Figure 9 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 12 for Figure 9 A cross-sectional structural diagram along the cutting line CC1, showing the plurality of parallel first grooves 204 (reference). Figure 5 and Figure 8 The second sacrificial layer 205 is filled in.

[0063] The second sacrificial layer 205 fills the first trench, and the surface of the second sacrificial layer 205 is flush with the surface of the topmost isolation layer 202.

[0064] The material of the second sacrificial layer 205 is the same as that of the first sacrificial layer 202, so that the first and second sacrificial layers can be removed simultaneously during subsequent etching processes, reducing the difficulty of the process. In some embodiments, the material of the second sacrificial layer 205 can be one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, amorphous silicon, amorphous carbon, and polycrystalline silicon. In this embodiment, the material of the second sacrificial layer 205 is silicon nitride.

[0065] In some embodiments, reference Figures 13-16 ,in Figure 14 for Figure 13 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 15 for Figure 13 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 16 for Figure 13 A cross-sectional view along the cutting line CC1 shows that the second sacrificial layer 205 is etched downwards along the first direction to form two first openings 207 in the second sacrificial layer 205; a portion of the first sacrificial layer 203 in the remaining stacked structure 201 is etched along the first openings 207, while retaining the isolation layer 202 in the remaining stacked structure, to correspondingly form two third trenches 227 extending along a third direction in the first sacrificial layer 203.

[0066] The two first openings 207 and the two third trenches 227 are subsequently used to form two first support layers. The length of the subsequently formed semiconductor layer (or channel region) is defined by the two first support layers, and the width of the subsequently formed semiconductor layer (or channel region) is defined by the two first trenches formed above, thereby enabling the position and size of the semiconductor layer to have high precision.

[0067] In some embodiments, before etching the second sacrificial layer 205, a patterned second mask layer is formed on the surface of the second sacrificial layer 205 and the stacked structure. The patterned second mask layer has a plurality of openings extending in a third direction, and the positions of the plurality of openings correspond to the positions of the plurality of third trenches to be formed. Using the patterned second mask layer as a mask, the second sacrificial layer 205 and the first sacrificial layer 203 are etched along the openings to form two parallel third trenches 207 extending in a third direction in the second sacrificial layer 205 and the first sacrificial layer 203.

[0068] In some embodiments, etching the second sacrificial layer 205 and the first sacrificial layer 203 can be performed using a dry or wet etching process. In other embodiments, etching the second sacrificial layer 205 and the first sacrificial layer 203 can be performed in two steps: first, the second sacrificial layer 205 is etched using an anisotropic dry etching process, and then the first sacrificial layer 203 is etched using a dry or wet etching process.

[0069] In some embodiments, when forming the first opening 207 and the third trench 207, the second opening 208 and the fourth trench 228 are also simultaneously formed in the second sacrificial layer 205 and the first sacrificial layer 203 on one side of the third trench 207. The second opening 208 and the fourth trench 228 also disconnect the second sacrificial layer 205 and the first sacrificial layer 202. A second support layer is subsequently formed in the second opening 208 and the fourth trench 228, and the region between the second support layer and the adjacent first support layer is the region for forming a capacitor.

[0070] refer to Figures 17-20 ,in Figure 18 for Figure 17 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 19 for Figure 17 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 20 for Figure 17 A cross-sectional view along the cutting line CC1 shows that the first opening and the third groove are filled with supporting material to form a first supporting layer 209.

[0071] In some embodiments, the first support layer 209 is used to support the stacked structure and maintain the mechanical stability of the structure. The first support layer 209 is also used to define the area of ​​the subsequently formed semiconductor layer (or channel region) (to prevent over-etching or other effects on other areas) and the length of the formed semiconductor layer (or channel region). Furthermore, the first support layer 209 can be made of doped semiconductor material, so that the first support layer 209 can also serve as the source and drain of the transistor without the need for additional processes to form the source and drain, thereby simplifying the process steps.

[0072] In other embodiments, the material of the first support layer 209 is different from the materials of the isolation layer 202, the first sacrificial layer 203, and the second sacrificial layer 205. The material of the first support layer 209 can be polycrystalline silicon, amorphous silicon, amorphous carbon, doped silicon oxide, or silicon oxynitride. Subsequently, after the first conductive layer is formed, the first support layer is removed to expose both ends of the semiconductor layer. Source and drain electrodes are formed at the locations where the first support layer is removed, respectively, at the two ends of the semiconductor layer.

[0073] In some embodiments, when forming the first support layer 209, support material is filled into the first opening and the third trench to form a second support layer 210. The material of the second support layer 210 may be the same as or different from the material of the first support layer 209. When the second support layer 210 and the first support layer 209 are made of the same material, they can be formed in the same process. When the second support layer 210 and the first support layer 209 are made of different materials, they are formed sequentially in different processes.

[0074] refer to Figures 21-24 ,in Figure 22 for Figure 21 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 23 for Figure 21 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 24 for Figure 21 A cross-sectional view along the cutting line CC1 shows that the second sacrificial layer located between the two first support layers 209 is etched downwards again along the first direction to form the second trench 211 in the second sacrificial layer. The second trench 211 is located between the first support layers 209. A portion of the remaining first sacrificial layer in the stacked structure is etched along the second trench 211 to form the cavity 212 in the first sacrificial layer. The cavity 212 is located between the isolation layers 202 and communicates with the second trench 211.

[0075] In some embodiments, the removal of the second sacrificial layer and the first sacrificial layer between adjacent first support layers 209 is performed using a dry or wet etching process. In another embodiment, the removal of the second sacrificial layer and the first sacrificial layer between adjacent first support layers 209 may be performed using a combination of anisotropic dry etching and isotropic dry or wet etching processes.

[0076] refer to Figures 25-28 ,in Figure 26 for Figure 25 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 27 for Figure 25 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 28 for Figure 25 A cross-sectional structural diagram along the cutting line CC1, in the cavity 211 (reference) Figure 21 , Figure 22 and Figure 24The cavity 211 is formed by filling the cavity with semiconductor material. In this embodiment, the cavity 211 is formed by etching the sacrificial layer, and then the semiconductor layer 213 is formed, for example, by atomic layer deposition. The semiconductor layer 213 serves as a self-aligned channel.

[0077] The semiconductor layer 213 serves as the channel region of the transistor. In some embodiments, the material of the semiconductor layer includes: IGZO, doped amorphous silicon, doped polycrystalline silicon, doped germanium silicon, In2O3, Ga2O3, ZnO, InGaZnO, InZnO, InGaO, GaZnO, InAlO, InSnO, InMgO, GaZnMgO, GaZnSnO, GaAlZnO, GaAlSnO, HfZnO, HfInZnO, HfAlGaZnO, InMgZnO, NbO, NiO, CoO, SnO, Cu2O, AgAlO, CuAlO3, AlScOC, Sr3BPO3, La2SiO4Se, LaCuSe, Rb2Sn2O3, La2O2S2, K2Sn2O3, Na2FeOSe2, or ZnRh2O4. When amorphous IGZO is used as the semiconductor layer (channel region) material, the carrier mobility of the formed transistor is improved, thus enhancing the performance of DRAM. The doped amorphous silicon, doped polycrystalline silicon, and doped germanium silicon can contain either N-type or P-type impurity ions. In some embodiments, the P-type impurity ions are one or more of boron, gallium, and indium, and the N-type impurity ions include one or more of phosphorus, arsenic, and antimony.

[0078] In one embodiment, the semiconductor layer 213 is formed as follows: a semiconductor material layer is formed on the sidewalls and bottom surface of the second trench 211 and in the cavity, the semiconductor material layer filling the cavity; the semiconductor material layer on the sidewalls and bottom surface of the second trench 211 is removed by a maskless etching process, the semiconductor material layer in the cavity is retained, and the semiconductor layer 213 is formed in the cavity. When forming a semiconductor layer using the aforementioned specific process, a semiconductor material layer is first formed through a deposition process. Then, only the semiconductor material layer on the sidewalls and bottom surface of the second trench 211 needs to be removed. The presence of the second trench 211 makes the etching process for removing part of the semiconductor material layer less difficult, and the etching process is less prone to fluctuations. Therefore, the semiconductor layer 213 formed is highly uniform on both sides exposed in the second trench. Furthermore, the flatness of the upper and lower surfaces of the semiconductor layer 213 depends on the flatness of the isolation layer 202. Since the isolation layer 202 has a flat surface, the upper and lower surfaces of the semiconductor layer 213 also have flat surfaces. Moreover, this process can use different semiconductor materials to form semiconductor layers, thereby achieving different electrical properties and meeting different customer needs.

[0079] In some embodiments, the semiconductor material layer is formed using an atomic layer deposition process. The maskless etching process employs anisotropic dry etching.

[0080] Step S103 is performed to form a first conductive layer extending along a first direction. The first conductive layer includes a plurality of gates stacked along the first direction, the gates surrounding the semiconductor layer. The process of forming the first conductive layer is described in detail below.

[0081] refer to Figures 29-32 ,in Figure 30 for Figure 29 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 31 for Figure 29 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 32 for Figure 29 A cross-sectional view along the cutting line CC1 shows the removal of the isolation layer 202 between adjacent semiconductor layers 213, leaving the semiconductor layers 213 suspended and exposing their surfaces.

[0082] The isolation layer 202 is removed using a dry etching process.

[0083] After the isolation layer 202 is removed, several semiconductor layers 213 are suspended on the substrate 200. The two ends of the semiconductor layers 213 are supported by the first support layer 209. Subsequently, by forming the first conductive layer, the suspended trench layers 213 can be covered or surrounded.

[0084] Before removing the isolation layer 202, the areas on both sides of the two first support layers 209 can be covered by a mask layer.

[0085] In some embodiments, reference Figures 33-36 ,in Figure 34 for Figure 33 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 35 for Figure 33 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 36 for Figure 33 A cross-sectional structural diagram along the cutting line CC1 shows that, before forming several discrete first conductive layers, the semiconductor layer 213 is further subjected to arc-shaped processing.

[0086] The purpose of rounding the semiconductor layer 213 is to remove the right angles or sharp corners on the surface of the semiconductor layer 213, so that the semiconductor layer 213 has a rounded surface, such as a circular surface or an elliptical surface, to prevent leakage current from the formed transistor.

[0087] In some embodiments, the arcing process includes: oxidizing the semiconductor layer 213 to form an oxide layer on the surface of the semiconductor layer 213, the oxidation process including furnace tube oxidation or ISSG (In-Situ Steam Generation); and removing the oxide layer, which can be done by wet etching or dry etching.

[0088] refer to Figures 37-40 ,in Figure 38 for Figure 37 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 39 for Figure 37 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 40 for Figure 37 A cross-sectional view along the cutting line CC1 shows a first conductive layer 214 extending along a first direction. The first conductive layer 214 includes a plurality of gates stacked along the first direction, the gates surrounding the semiconductor layer 213. In this embodiment, a self-aligned first conductive layer is formed by atomic layer deposition along a first direction perpendicular to the top surface of the substrate. The first conductive layer includes a plurality of stacked gates, which are completed in a single step, significantly increasing the density and performance of the semiconductor device.

[0089] The first conductive layer 214 serves as the word line of the DRAM memory.

[0090] The first conductive layers 214 are discrete, and each first conductive layer 214 covers a plurality of semiconductor layers 213 in a first direction.

[0091] Before forming the first conductive layer 214, the method further includes: a gate dielectric layer on the surface of the semiconductor layer 213, and then forming the first conductive layer 214 surrounding the semiconductor layer 213 on the surface of the gate dielectric layer.

[0092] The material of the gate dielectric layer can be silicon oxide or a high-K (K greater than 2.5) dielectric material, and the material of the first conductive layer can be one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, and Wsi.

[0093] In some embodiments, the formation process of the first conductive layer 214 is as follows: a gate dielectric layer is formed on the surface of the semiconductor layer 214; a metal layer is formed on the surface of the gate dielectric layer, in the second trench, and in the space after the first sacrificial layer is removed; the metal layer at the bottom and sidewall of the second trench is etched along the second direction to break the metal layer and form a plurality of discrete first conductive layers.

[0094] In some embodiments, reference Figures 41-44,in Figure 42 for Figure 41 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 43 for Figure 41 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 44 for Figure 41 A cross-sectional structural diagram along the cutting line CC1 shows that after the first conductive layer 214 is formed, an isolation dielectric layer 216 is formed to fill the space between adjacent word lines.

[0095] The material of the isolation dielectric layer 216 may be one or more of the following: silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide), or low dielectric constant (K less than 2.5).

[0096] In some embodiments, after forming the first conductive layer 214, reference Figures 45-48 ,in Figure 46 for Figure 45 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 47 for Figure 45 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 48 for Figure 45 The cross-sectional structure diagram along the cutting line CC1 also includes: removing the first support layer to expose the first opening 207 and the third trench 227. The removal of the first support layer can be achieved by a wet etching process.

[0097] refer to Figures 49-52 ,in Figure 50 for Figure 49 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 51 for Figure 49 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 52 for Figure 49 A cross-sectional view along the cutting line CC1 shows that semiconductor material is deposited in the first opening 207 and the third trench, and the semiconductor material in the first opening 207 is etched back to form a source 229 and a drain 230 connected to the semiconductor layer 213 at both ends.

[0098] The semiconductor material includes doped polycrystalline silicon or germanium silicon.

[0099] In some embodiments, the method further includes: removing the isolation layer between the drains 230 to expose the drains 230, and forming a plurality of second conductive layers (not shown) extending in a third direction on the surface of the plurality of drain regions, each of the second conductive layers being connected to the plurality of drain regions 230 of each layer. The second conductive layers serve as bit lines of the DRAM memory.

[0100] refer to Figures 53-56 ,in Figure 54 for Figure 53 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 55 for Figure 53 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 56 for Figure 53 A cross-sectional view along the cutting line CC1 shows a second isolation medium layer 231 that fills the first opening.

[0101] The material of the second insulating dielectric layer 231 can be one or more of the following: silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide), and low dielectric constant (K less than 2.5).

[0102] In some embodiments, the method further includes removing the first sacrificial layer and the second sacrificial layer between the source electrode 229 and the second support layer to form a second cavity; and forming a capacitor connected to the source electrode 229 in the second cavity.

[0103] In some embodiments of this application, a three-dimensional semiconductor structure formed by the aforementioned method is also provided, with reference to... Figures 53-56 ,include:

[0104] 200 for the substrate;

[0105] A plurality of semiconductor layers 213 are stacked on the substrate 200 along a first direction, wherein the first direction is perpendicular to the top surface of the substrate 200;

[0106] A first conductive layer 214 is located on the substrate 200 and extends along a first direction. The first conductive layer 214 includes a plurality of gates stacked along the first direction and surrounds the semiconductor layer 213.

[0107] In some embodiments, the system further includes a source 229 and a drain 230 located at opposite ends of the semiconductor layer 213 along its extension direction and connected to the semiconductor layer 213; a plurality of second conductive layers stacked on the substrate 200 along a first direction, the extension direction of the second conductive layers being perpendicular to the extension direction of the semiconductor layer and parallel to the top surface of the substrate (i.e., extending along a third direction), each of the second conductive layers being connected to the plurality of drains 230 or sources 229; and a capacitor connected to the source 229 or drain 230.

[0108] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A method for fabricating a three-dimensional semiconductor structure, characterized in that, include: Provide a base; Multiple semiconductor layers are formed on the substrate and stacked along a first direction, wherein the first direction is perpendicular to the top surface of the substrate; A first conductive layer is formed extending along a first direction, the first conductive layer including a plurality of gates stacked along the first direction, the gates surrounding the semiconductor layer; The process of forming multiple semiconductor layers stacked along the first direction includes: A stacked structure in which an isolation layer and a first sacrificial layer are alternately layered is formed on the substrate; The stacked structure is etched along a second direction to form a plurality of parallel first trenches penetrating the stacked structure. The first trenches extend along the second direction, which is a direction parallel to the top surface of the substrate. The second sacrificial layer is filled into the plurality of parallel first trenches; A portion of the second sacrificial layer and a portion of the first sacrificial layer in the remaining stacked structure are removed along a third direction, while retaining the isolation layer in the remaining stacked structure. A second trench is formed at the location where the second sacrificial layer is removed, penetrating the stacked structure along the first direction. A cavity is formed at the location where the first sacrificial layer is removed, extending along the third direction. The cavity communicates with the second trench. The third direction is a direction perpendicular to the second direction and parallel to the top surface of the substrate. The cavity is filled with semiconductor material to form the semiconductor layer.

2. The method for fabricating a three-dimensional semiconductor structure as described in claim 1, characterized in that, The process of filling the cavity with semiconductor material to form the semiconductor layer is as follows: A semiconductor material layer is formed on the sidewalls and bottom surface of the second trench and in the cavity, the semiconductor material layer filling the cavity; The semiconductor material layer on the sidewalls and bottom surface of the second trench is removed by a maskless etching process, while the semiconductor material layer in the cavity is retained, and the semiconductor layer is formed in the cavity.

3. The method for fabricating a three-dimensional semiconductor structure as described in claim 1 or 2, characterized in that, The materials of the semiconductor layer include: IGZO, doped amorphous silicon, doped polycrystalline silicon, doped germanium silicon, In2O3, Ga2O3, ZnO, InGaZnO, InZnO, InGaO, GaZnO, InAlO, InSnO, InMgO, GaZnMgO, GaZnSnO, GaAlZnO, GaAlSnO, HfZnO, HfInZnO, HfAlGaZnO, InMgZnO, NbO, NiO, CoO, SnO, Cu2O, AgAlO, CuAlO3, AlScOC, Sr3BPO3, La2SiO4Se, LaCuSe, Rb2Sn2O3, La2O2S2, K2Sn2O3, Na2FeOSe2 or ZnRh2O4.

4. The method for fabricating a three-dimensional semiconductor structure as described in claim 1 or 2, characterized in that, The process of forming the first conductive layer includes: Remove the isolation layer between adjacent semiconductor layers, leaving the semiconductor layers suspended and exposing their surfaces; A conductive material is deposited on the surface of the semiconductor layer to form the first conductive layer extending along the first direction.

5. The method for fabricating a three-dimensional semiconductor structure as described in claim 1 or 2, characterized in that, The first sacrificial layer and the second sacrificial layer are made of the same material, but the first sacrificial layer and the second sacrificial layer are made of a different material than the isolation layer.

6. The method for fabricating a three-dimensional semiconductor structure as described in claim 5, characterized in that, The material of the isolation layer is one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride, and the materials of the first sacrificial layer and the second sacrificial layer are one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, amorphous silicon, amorphous carbon, and polycrystalline silicon.

7. The method for fabricating a three-dimensional semiconductor structure as described in claim 1, characterized in that, The process of removing a portion of the second sacrificial layer and a portion of the first sacrificial layer from the remaining stacked structure along a third direction, while retaining the isolation layers in the remaining stacked structure, includes: The second sacrificial layer is etched downward along the first direction to form two first openings in the second sacrificial layer; A portion of the first sacrificial layer in the remaining stacked structure is etched along the first opening, retaining the isolation layer in the remaining stacked structure, so as to form two third trenches extending along the third direction in the first sacrificial layer accordingly. The first opening and the third groove are filled with support material to form two first support layers; The second sacrificial layer located between the two first support layers is etched downward again along the first direction to form the second trench in the second sacrificial layer, the second trench being located between the first support layers; A portion of the first sacrificial layer in the remaining stacked structure is etched along the second trench to form the cavity in the first sacrificial layer, the cavity being located between the isolation layers.

8. The method for fabricating a three-dimensional semiconductor structure as described in claim 7, characterized in that, After forming the first conductive layer, the method further includes: Remove the first support layer to expose the first opening and the third trench; Semiconductor material is deposited in the first opening and the third trench, and the semiconductor material in the opening is etched back to form a source and a drain connected to the semiconductor layer at both ends of the semiconductor layer.

9. The method for fabricating a three-dimensional semiconductor structure as described in claim 1 or 2, characterized in that, A plurality of second conductive layers are formed and stacked along a first direction, wherein the extension direction of the second conductive layers is perpendicular to the extension direction of the semiconductor layer and parallel to the top surface of the substrate.

10. The method for fabricating a three-dimensional semiconductor structure as described in claim 1 or 2, characterized in that, Before forming the first conductive layer, the process further includes: rounding the semiconductor layer.

11. The method for fabricating a three-dimensional semiconductor structure as described in claim 1 or 2, characterized in that, After the first conductive layer is formed, an isolation dielectric layer is formed to fill the space between adjacent first conductive layers.

12. The method for fabricating a three-dimensional semiconductor structure as described in claim 1 or 2, characterized in that, The gate includes a gate dielectric layer located on the surface of the semiconductor layer and a first conductive layer located on the gate dielectric layer surrounding the semiconductor layer.

13. A three-dimensional semiconductor structure prepared by the preparation method according to any one of claims 1 to 12, characterized in that, include: Base; A plurality of semiconductor layers are stacked on the substrate along a first direction, wherein the first direction is perpendicular to the top surface of the substrate; A first conductive layer is located on the substrate and extends along a first direction, the first conductive layer including a plurality of gates stacked along the first direction, the first conductive layer surrounding the semiconductor layer.

14. The three-dimensional semiconductor structure as described in claim 13, characterized in that, It also includes a source and a drain, which are respectively located at both ends of the semiconductor layer in the extension direction and connected to the semiconductor layer; A plurality of second conductive layers are stacked on the substrate along the first direction, the extension direction of the second conductive layers is perpendicular to the extension direction of the semiconductor layer and parallel to the top surface of the substrate, and the second conductive layers are connected to the drain / source. A capacitor connected to the source / drain.

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