A method for manufacturing a silicon carbide field effect tube device

Abstract

The present invention provides a method for manufacturing a silicon carbide field effect transistor device, comprising: step S1, providing a silicon carbide substrate deposited with an epitaxial layer and depositing a first and a second hard mask on the epitaxial layer, respectively, and then ion implanting to obtain two well regions; step S2, depositing a third hard mask on the first and second hard masks, and photolithographically patterning on the third hard mask, then removing the third hard mask around the first hard mask and forming a side wall on the side wall; step S3, forming two source regions along the side wall; step S4, removing the first, second, and third hard masks, and depositing a fourth hard mask to cover the two source regions, and then etching the P+ contact region; step S5, forming a gate and a source. The beneficial effect is that the method etches the source region by depositing the third hard mask of the ONO medium, shielding the well region that does not need source region injection, making the base series resistance of all regions of the field effect transistor device almost the same, and avoiding the point with low avalanche tolerance in the device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a method for manufacturing a silicon carbide field effect transistor device. Background Art

[0002] Silicon carbide semiconductors have excellent physical and electrical properties such as large bandgap width, high critical breakdown field strength, high thermal conductivity, and high carrier saturation drift velocity, which makes them have broad application prospects in the field of high-temperature, high-frequency, and high-power device electronics. Since silicon carbide can be obtained by thermal oxidation to obtain silicon dioxide, the research and development and application of field effect transistor devices and related circuits based on silicon carbide materials become possible. Compared with other types of silicon carbide power devices, silicon carbide field effect transistor devices have the advantages of high switching speed, high reverse blocking voltage, and low on-resistance. In addition, the driving circuit is simple and compatible with existing silicon-based power devices. It is a highly anticipated new type of power switching device with extremely outstanding potential and advantages.

[0003] The channel resistance accounts for a large proportion of the on-resistance of silicon carbide field effect transistor devices. In order to reduce the on-resistance of the device, a self-alignment process is usually used to form a short channel. The self-alignment process causes the active area to be injected simultaneously on the well area, so the transition area and the terminal in the device are prone to areas with low avalanche resistance. Summary of the invention

[0004] In view of the problems existing in the prior art, the present invention provides a method for manufacturing a silicon carbide field effect transistor device, which specifically comprises the following steps:

[0005] Step S1, providing a silicon carbide substrate with an epitaxial layer deposited thereon and depositing a hard mask on the epitaxial layer along the length direction of the epitaxial layer, then using a first mask to etch on the hard mask to obtain a first hard mask and a second hard mask, and performing ion implantation to obtain two well regions;

[0006] Step S2, depositing a third hard mask on the first hard mask and the second hard mask, and using a second mask to photolithographically pattern the third hard mask, then removing the third hard mask around the first hard mask along the pattern and forming a sidewall on the sidewall of the first hard mask;

[0007] Step S3, performing source region ion implantation using the sidewalls on both sides of the first hard mask and the etched cross section of the third hard mask as masks to form two source regions;

[0008] Step S4, removing the first hard mask, the second hard mask and the third hard mask, and depositing a fourth hard mask to cover the two source regions, and then using a third mask to etch one side of the fourth hard mask, and performing ion implantation to obtain a P+ contact region;

[0009] Step S5, forming a gate and a source of the silicon carbide field effect transistor device respectively on the two source regions and the P+ contact region, and depositing metal on the back side of the silicon carbide substrate to form a drain of the silicon carbide field effect transistor device.

[0010] Preferably, in the step S1, a first oxide layer and a first polysilicon layer are sequentially deposited on the epitaxial layer to form the first hard mask and the second hard mask.

[0011] Preferably, in the step S2, a second silicon oxide layer, a silicon nitride layer and a third silicon oxide layer are sequentially deposited on the first hard mask and the second hard mask to form the third hard mask.

[0012] Preferably, the thickness of the second silicon oxide layer is 20-2000 Å, the thickness of the silicon nitride layer is 1000 Å-8000 Å, and the thickness of the third silicon oxide layer is 1000 Å-20000 Å.

[0013] Preferably, the step S2 comprises:

[0014] Step S21, depositing the third hard mask on the first hard mask and the second hard mask;

[0015] Step S22, using a second mask to photolithographically pattern the third hard mask;

[0016] Step S23, removing the third silicon oxide layer in the third hard mask around the first hard mask by a wet etching method;

[0017] Step S24, removing the photoresist remaining from the photolithography pattern on the second hard mask using the second mask;

[0018] Step S25 , removing the silicon nitride layer in the third hard mask around the first hard mask by a dry etching method, and forming sidewall spacers on two sidewalls of the first hard mask respectively.

[0019] Preferably, the process of performing source region ion implantation to form two source regions in step S3 further includes generating channels on one side of the source regions in the two well regions close to the first hard mask according to the sidewalls.

[0020] Preferably, after removing the first hard mask, the second hard mask and the third hard mask in step S4, the step further includes performing high temperature activation and diffusion treatment on the two source regions and the two well regions.

[0021] Preferably, step S5 comprises:

[0022] Step S51, removing the fourth hard mask and depositing a field oxide layer above the P+ contact region, and then using a fourth mask to etch the field oxide layer to obtain an active region;

[0023] Step S52, growing a sacrificial oxide layer above the two source regions, then removing the sacrificial oxide layer by a wet etching method, and growing a gate oxide layer to cover the two source regions;

[0024] Step S53, depositing a second polysilicon layer on the gate oxide layer and the field oxide layer respectively, and etching the second polysilicon layer using a fifth mask to obtain a polysilicon gate;

[0025] Step S54, depositing a dielectric layer on the gate oxide layer, the field oxide layer and the second polysilicon layer, and etching the dielectric layer using a sixth mask and a seventh mask respectively to obtain gate-source contact holes and the gate and the source of the silicon carbide field effect transistor device, and then depositing metal on the back side of the silicon carbide substrate to form the drain of the silicon carbide field effect transistor device.

[0026] Preferably, the step S54 includes:

[0027] Step S541, depositing the dielectric layer on the gate oxide layer, the field oxide layer and the second polysilicon layer, and etching the dielectric layer using the sixth mask to obtain the gate-source contact hole;

[0028] Step S542, sputtering a top layer of metal on the dielectric layer, and etching the top layer of metal using the seventh mask to form the gate and the source of the silicon carbide field effect transistor device;

[0029] Step S543, reducing the thickness of the back side of the silicon carbide substrate, and depositing metal on the back side of the silicon carbide substrate by sputtering or evaporation to form the drain of the silicon carbide field effect transistor device.

[0030] Preferably, the step S542 further comprises depositing a passivation layer on the top metal layer, and etching the passivation layer using an eighth mask to form a top structure.

[0031] The above technical solution has the following advantages or beneficial effects:

[0032] (1) This method etches the source region by depositing a third hard mask of ONO dielectric, shielding the well region that does not require source region injection, making the base series resistance of all regions of the field effect transistor device almost the same, avoiding the point with low avalanche tolerance in the device, and improving the reliability of the device;

[0033] (2) This method forms a sidewall on the sidewall of the first polysilicon layer in the original cell region through subsequent etching of the silicon nitride layer, and also forms a self-aligned channel through subsequent source region implantation;

[0034] (3) The field effect transistor device manufactured by this method is more flexible in design, and the device edge and other areas can be flexibly designed as needed. At the same time, this method is compatible with existing process steps and is safe and reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A flowchart of the steps of the method in a preferred embodiment of the present invention;

[0036] Figure 2 It is a schematic diagram of the design of an existing field effect transistor device in a preferred embodiment of the present invention;

[0037] Figure 3 This is a schematic diagram of the design of a field effect transistor device in a preferred embodiment of the present invention;

[0038] Figure 4 FIG. 1 is a schematic diagram of forming a P-well region or an N-well region in a preferred embodiment of the present invention;

[0039] Figure 5 is a schematic diagram of deposition of a third hard mask in a preferred embodiment of the present invention;

[0040] Figure 6 FIG. 1 is a schematic diagram of forming a side wall in a preferred embodiment of the present invention;

[0041] Figure 7 FIG. 1 is a schematic diagram of forming a source region in a preferred embodiment of the present invention;

[0042] Figure 8 The specific flow chart of step S2 in the preferred embodiment of the present invention;

[0043] Fig. 9 FIG. 1 is a schematic diagram of a structure after the first hard mask, the second hard mask and the third hard mask are removed in a preferred embodiment of the present invention;

[0044] Fig.10 FIG. 1 is a schematic diagram of forming a P+ contact region in a preferred embodiment of the present invention;

[0045] Fig.11 This is a specific flow chart of step S5 in a preferred embodiment of the present invention;

[0046] Fig.12 The specific flow chart of step S54 in the preferred embodiment of the present invention;

[0047] Fig.13This is an overall schematic diagram of a silicon carbide field effect transistor device in a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0048] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment, and other embodiments may also fall within the scope of the present invention as long as they conform to the gist of the present invention.

[0049] In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a method for manufacturing a silicon carbide field effect transistor device is provided. Figure 1 As shown, specifically comprising the following steps:

[0050] Step S1, providing a silicon carbide substrate 2 with an epitaxial layer 1 deposited thereon and depositing a hard mask on the epitaxial layer 1 along the length direction of the epitaxial layer 1, then using a first mask to etch on the hard mask to obtain a first hard mask 3 and a second hard mask 4, and performing ion implantation to obtain two well regions 5;

[0051] Step S2, depositing a third hard mask 6 on the first hard mask 3 and the second hard mask 4, and using a second mask plate to photolithographically pattern the third hard mask 6, then removing the third hard mask 6 around the first hard mask 3 along the pattern and forming a sidewall 7 on the sidewall of the first hard mask 3;

[0052] Step S3, using the sidewalls 7 on both sides of the first hard mask 3 and the etched cross-section of the third hard mask 6 as masks to perform source ion implantation to form two source regions 8;

[0053] Step S4, removing the first hard mask 3, the second hard mask 4 and the third hard mask 6, and depositing a fourth hard mask 9 to cover the two source regions 8, then using the third mask to etch one side of the fourth hard mask 9, and performing ion implantation to obtain a P+ contact region 10;

[0054] In step S5 , a gate 11 and a source 12 of a SiC FET device are formed on the two source regions 8 and the P+ contact region 10 , respectively, and a metal is deposited on the back side of the SiC substrate 2 to form a drain 13 of the SiC FET device.

[0055] Specifically, in this embodiment, Figure 2 Schematic diagram of the design of the existing field effect device. As can be seen from the figure, the P-well region in the existing field effect transistor device surrounds the source region 8, and the source region 8 surrounds the gate-source contact hole. The existing field effect transistor device adopts a self-alignment process to form a short channel. The self-alignment process causes the N-type source region 8 to be injected while the P-well region is injected. Therefore, the transition region and the terminal region in the device are prone to low avalanche tolerance areas (the area circled in the figure), and by Figure 3It can be seen that the source regions 8 in the field effect transistor device manufactured by this method are separated by gate-source contact holes, which eliminates the area with low avalanche resistance, improves the avalanche resistance of the field effect transistor device, and further improves the reliability of the field effect transistor device.

[0056] Specifically, in this embodiment, the epitaxial layer 1 has a specific doping concentration and the doping concentration can be custom designed.

[0057] Specifically, in this embodiment, the silicon carbide substrate 2 may be silicon carbide of 4H-SiC, 6H-SiC, 3C-SiC or 15R-SiC crystal type.

[0058] Preferably, the silicon carbide substrate 2 may be a P-type substrate or an N-type substrate. When the silicon carbide substrate 2 is a P-type substrate, an N-well region is etched in step S1 , and when the silicon carbide substrate 2 is an N-type substrate, a P-well region is etched in step S1 .

[0059] In a preferred embodiment of the present invention, Figure 4 As shown, in step S1 , a first oxide layer 14 and a first polysilicon layer 15 are sequentially deposited on the epitaxial layer 1 to form a first hard mask 3 and a second hard mask 4 .

[0060] Specifically, in this embodiment, the second hard mask 4 is the same as the first hard mask 3 , and both are composed of a first oxide layer 14 and a first polysilicon layer 15 .

[0061] In a preferred embodiment of the present invention, Figure 5 As shown, in step S2 , a second silicon oxide layer 16 , a silicon nitride layer 17 and a third silicon oxide layer 18 are sequentially deposited on the first hard mask 3 and the second hard mask 4 to form a third hard mask 6 .

[0062] Specifically, in this embodiment, the third hard mask 6 is an ONO (Oxide-Nitride-Oxid) medium hard mask, that is, from bottom to top, it includes a second silicon oxide layer 16, a silicon nitride layer 17 and a third silicon oxide layer 18.

[0063] In a preferred embodiment of the present invention, the thickness of the second silicon oxide layer 16 is 20-2000 Å, the thickness of the silicon nitride layer 17 is 1000 Å-8000 Å, and the thickness of the third silicon oxide layer 18 is 1000 Å-20000 Å.

[0064] Specifically, in this embodiment, the thicknesses of the second silicon oxide layer 16, the silicon nitride layer 17 and the third silicon oxide layer 18 are determined by the channel length of the designed field effect transistor device and the implantation conditions of the source region 8, and can be adaptively adjusted.

[0065] In a preferred embodiment of the present invention, Figure 6-8 As shown, step S2 includes:

[0066] Step S21, depositing a third hard mask 6 on the first hard mask 3 and the second hard mask 4;

[0067] Step S22, using a second mask to photolithographically pattern the third hard mask 6;

[0068] Step S23, removing the third silicon oxide layer in the third hard mask 6 around the first hard mask 3 according to a wet etching method;

[0069] Step S24, removing the photoresist remaining from the photolithography pattern on the second hard mask 4 using the second mask;

[0070] In step S25 , the silicon nitride layer 17 in the third hard mask 6 around the first hard mask 3 is removed by dry etching, and sidewall spacers 7 are formed on two sidewalls of the first hard mask 3 .

[0071] Specifically, in this embodiment, the width of the sidewall 7 determines the channel length of the field effect transistor device, and can be adaptively adjusted according to the requirements of the designed field effect transistor device.

[0072] In a preferred embodiment of the present invention, the process of performing source ion implantation to form two source regions 8 in step S3 also includes generating channels at one side of the source regions 8 in the two well regions 5 close to the first hard mask 3 according to the sidewalls 7 .

[0073] Specifically, in the present embodiment, a self-aligned channel is formed in the original cell region due to the blocking of the first polysilicon layer 15 and the side wall 7, and at the same time, a masking layer of the source region 8 is formed in the transition region and the terminal region through the third hard mask 6, thereby shielding the P-well region or N-well region where source injection is not required, so that the base series resistance of all regions of the field effect transistor device is almost the same, thereby avoiding points with low avalanche tolerance in the device.

[0074] In a preferred embodiment of the present invention, after removing the first hard mask 3 , the second hard mask 4 , and the third hard mask 6 in step S4 , the step further includes performing high temperature activation and diffusion treatment on the two source regions 8 and the two well regions 5 .

[0075] Specifically, in this embodiment, Fig. 9 It is a schematic diagram after the first hard mask 3 , the second hard mask 4 and the third hard mask 6 are removed.

[0076] In a preferred embodiment of the present invention, Fig.10 , 11 As shown, step S5 includes:

[0077] Step S51, removing the fourth hard mask 9 and depositing a field oxide layer 19 above the P+ contact region 10, and then using a fourth mask to etch the field oxide layer 19 to obtain an active region;

[0078] Step S52, growing a sacrificial oxide layer above the two source regions 8, then removing the sacrificial oxide layer by wet etching, and growing a gate oxide layer 20 to cover the two source regions 8;

[0079] Step S53, depositing a second polysilicon layer 22 on the gate oxide layer 20 and the field oxide layer 19 respectively, and etching the second polysilicon layer 22 using a fifth mask to obtain a polysilicon gate 11;

[0080] In step S54, a dielectric layer 21 is deposited on the gate oxide layer 20, the field oxide layer 19 and the second polysilicon layer 22, and a sixth mask and a seventh mask are used to etch the dielectric layer 21 to obtain gate-source contact holes and the gate 11 and source 12 of the silicon carbide field effect transistor device, and then metal is deposited on the back side of the silicon carbide substrate 2 to form the drain 13 of the silicon carbide field effect transistor device.

[0081] Specifically, in this embodiment, a thick oxide layer is deposited as the field oxide layer 19, and the thick oxide layer refers to an oxide layer with a thickness > 0.5um. The active area is the area where the primitive cell of the field effect transistor device is formed, that is, the area where the current is conducted when the field effect transistor device is working, and the source region 8 is the NPS region of each primitive cell.

[0082] Specifically, in this embodiment, after a sacrificial oxide layer is grown on the field oxide layer 19 and removed by a wet etching method, the gate oxide layer 20 is directly grown on the region.

[0083] In a preferred embodiment of the present invention, Fig.12 , 13 As shown, step S54 includes:

[0084] Step S541, depositing a dielectric layer 21 on the gate oxide layer 20, the field oxide layer 19 and the second polysilicon layer 22, and etching the dielectric layer 21 using a sixth mask to obtain gate-source contact holes;

[0085] Step S542, sputtering a top metal layer on the dielectric layer 21, and etching the top metal layer using a seventh mask to form a gate 11 and a source 12 of a silicon carbide field effect transistor device;

[0086] Step S543 , thinning the back side of the silicon carbide substrate 2 , and depositing metal on the back side of the silicon carbide substrate 2 by sputtering or evaporation to form the drain 13 of the silicon carbide field effect transistor device.

[0087] In a preferred embodiment of the present invention, step S542 further includes depositing a passivation layer on the top metal layer, and etching the passivation layer using an eighth mask to form a top structure.

[0088] The above description is only a preferred embodiment of the present invention, and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the contents of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a silicon carbide field effect transistor device, It is characterized in that Specifically include the following steps: Step S1, providing a silicon carbide substrate with an epitaxial layer deposited thereon and depositing a hard mask on the epitaxial layer along the length direction of the epitaxial layer, then using a first mask to etch the hard mask to obtain a first hard mask and a second hard mask, and performing ion implantation to obtain two well regions; Step S2, depositing a third hard mask on the first hard mask and the second hard mask, and using a second mask to photolithographically pattern the third hard mask, then removing the third hard mask around the first hard mask along the pattern and forming a sidewall on the sidewall of the first hard mask; Step S3, performing source region ion implantation using the sidewalls on both sides of the first hard mask and the etched cross section of the third hard mask as masks to form two source regions; Step S4, removing the first hard mask, the second hard mask and the third hard mask, and depositing a fourth hard mask to cover the two source regions, and then using a third mask to etch one side of the fourth hard mask, and performing ion implantation to obtain a P+ contact region; Step S5, forming a gate and a source of the silicon carbide field effect transistor device respectively on the two source regions and the P+ contact region, and depositing metal on the back side of the silicon carbide substrate to form a drain of the silicon carbide field effect transistor device; The step S5 comprises: Step S51, removing the fourth hard mask and depositing a field oxide layer above the P+ contact region, and then using a fourth mask to etch the field oxide layer to obtain an active region; Step S52, growing a sacrificial oxide layer above the two source regions, then removing the sacrificial oxide layer by a wet etching method, and growing a gate oxide layer to cover the two source regions; Step S53, depositing a second polysilicon layer on the gate oxide layer and the field oxide layer respectively, and etching the second polysilicon layer using a fifth mask to obtain a polysilicon gate; Step S54, depositing a dielectric layer on the gate oxide layer, the field oxide layer and the second polysilicon layer, and etching the dielectric layer using a sixth mask and a seventh mask respectively to obtain gate-source contact holes and the gate and the source of the silicon carbide field effect transistor device, and then depositing metal on the back side of the silicon carbide substrate to form the drain of the silicon carbide field effect transistor device; The step S54 comprises: Step S541, depositing the dielectric layer on the gate oxide layer, the field oxide layer and the second polysilicon layer, and etching the dielectric layer using the sixth mask to obtain the gate-source contact hole; Step S542, sputtering a top layer of metal on the dielectric layer, and etching the top layer of metal using the seventh mask to form the gate and the source of the silicon carbide field effect transistor device; Step S543, thinning the back side of the silicon carbide substrate, and depositing metal on the back side of the silicon carbide substrate by sputtering or evaporation to form the drain of the silicon carbide field effect transistor device; In the step S2, a second silicon oxide layer, a silicon nitride layer and a third silicon oxide layer are sequentially deposited on the first hard mask and the second hard mask to form the third hard mask; The step S2 comprises: Step S21, depositing the third hard mask on the first hard mask and the second hard mask; Step S22, using a second mask to photolithographically pattern the third hard mask; Step S23, removing the third silicon oxide layer in the third hard mask around the first hard mask by a wet etching method; Step S24, removing the photoresist remaining from the photolithography pattern on the second hard mask using the second mask; Step S25 , removing the silicon nitride layer in the third hard mask around the first hard mask by a dry etching method, and forming sidewall spacers on two sidewalls of the first hard mask respectively.

2. The method according to claim 1, It is characterized in that In the step S1, a first oxide layer and a first polysilicon layer are sequentially deposited on the epitaxial layer as the hard mask, and then a first mask is used to etch the hard mask to obtain the first hard mask and the second hard mask.

3. The method according to claim 1, It is characterized in that The thickness of the second silicon oxide layer is 20-2000 Å, the thickness of the silicon nitride layer is 1000 Å-8000 Å, and the thickness of the third silicon oxide layer is 1000 Å-20000 Å.

4. The method according to claim 1, It is characterized in that The process of performing source region ion implantation to form two source regions in step S3 also includes generating channels on one side of the source regions in the two well regions close to the first hard mask according to the sidewalls.

5. The method according to claim 1, It is characterized in that After removing the first hard mask, the second hard mask and the third hard mask in step S4, the step further includes performing high temperature activation and diffusion treatment on the two source regions and the two well regions.

6. The method according to claim 1, It is characterized in that The step S542 further includes depositing a passivation layer on the top metal layer, and etching the passivation layer using an eighth mask to form a top structure.

Images