Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The semiconductor structure includes: a substrate and protrusions on the substrate protruding from sub-device regions; a channel structure layer, located on the protrusions and spaced apart from them, comprising one or more spaced-apart channel layers; a dielectric wall, located longitudinally on the substrate between adjacent sub-device regions, comprising a main dielectric wall portion protruding from the substrate and a dielectric wall protrusion portion protruding longitudinally from the main dielectric wall portion, the dielectric wall protrusion portion contacting the sidewall of the channel layer; a gate structure, located on each sub-device region, spanning the top of the channel structure layer and surrounding the exposed channel layer of the dielectric wall; and source / drain doped layers, located on the protrusions on both sides of the gate structure and contacting the channel structure layer. Embodiments of the present invention reduce the influence of the dielectric wall on the stress exerted by the source / drain doped layers on the channel layer, thereby optimizing the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor transistors are evolving towards higher device density and higher integration, and semiconductor process nodes are continuously shrinking in accordance with Moore's Law. Transistors, as the most basic semiconductor material, are currently widely used. Therefore, as the device density and integration of semiconductor transistors increase, the channel length of transistors must be continuously shortened to adapt to the shrinking process nodes.

[0003] To better adapt to the requirement of proportionally shrinking transistor dimensions, semiconductor manufacturing processes have gradually transitioned from planar transistors to more efficient three-dimensional transistors, such as FinFETs and Gate-all-around (GAA) transistors. GAA transistors include vertical and horizontal types. In a GAA transistor, the gate surrounds the channel region from all sides. Compared to planar transistors, GAA transistors offer stronger control over the channel and better suppress short-channel effects.

[0004] To expand the scalability of these devices, a new architecture called Forksheet transistors has been proposed. Compared to GAA transistors or Nanosheets, in Forksheets, the channel is controlled by a fork-shaped gate structure, and a "dielectric wall" is introduced between the nFET and pFET devices. The arrangement of the dielectric wall allows for a smaller spacing between the nFET and pFET devices within a standard cell, thus giving Forksheets better scalability in terms of area and performance.

[0005] However, the performance of Forksheet still needs improvement. Summary of the Invention

[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which reduces the influence of dielectric walls on the stress applied by the source / drain doped layers to the channel layer, thereby optimizing the performance of the semiconductor structure.

[0007] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate including discrete device cell regions, each device cell region including a plurality of sub-device regions arranged longitudinally; a protrusion protruding from the substrate of the sub-device regions and extending laterally; a channel structure layer located on the protrusion and spaced apart from the protrusion, the channel structure layer including one or more channel layers spaced apart from bottom to top; a dielectric wall located on the substrate between adjacent sub-device regions along the longitudinal direction, the dielectric wall including a dielectric wall main portion protruding from the substrate and a dielectric wall protrusion extending longitudinally from the dielectric wall main portion, the dielectric wall protrusion contacting the sidewall of the channel layer; a gate structure located on each sub-device region, spanning the top of the channel structure layer of the sub-device region and surrounding the exposed channel layer of the dielectric wall; and source / drain doped layers located on the protrusions on both sides of the gate structure and contacting the channel structure layer.

[0008] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, including providing a substrate, including discrete device cell regions, each device cell region including a plurality of longitudinally arranged sub-device regions, a laterally extending and protruding protrusion formed on the substrate of the sub-device regions, a stacked structure formed on the protrusion, the stacked structure including one or more stacked channel stacks, an initial dielectric wall formed between the stacked structures along the longitudinal direction and in contact with the stacked structure; forming a dummy gate structure across the stacked structure and the initial dielectric wall on the substrate; forming source and drain doped layers in the stacked structures on both sides of the dummy gate structure; removing the dummy gate structure to form a gate opening, exposing... Exposing the stacked structure; removing the sacrificial layer in the channel stack to form a via, the via being surrounded by the protrusion and the channel layer adjacent to the protrusion and the initial dielectric wall, or the via being surrounded by the adjacent channel layer and the initial dielectric wall; the via being connected to the gate opening; isotropically etching the initial dielectric wall to form a dielectric wall, the dielectric wall including a dielectric wall main portion protruding on the substrate and a dielectric wall protrusion portion protruding longitudinally from the dielectric wall main portion, the dielectric wall protrusion portion contacting the sidewall of the channel layer; after forming the dielectric wall, forming a gate structure in the gate opening and via in each of the sub-device regions.

[0009] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0010] The semiconductor structure provided in this embodiment of the invention includes a dielectric wall comprising a main portion of the dielectric wall protruding from the substrate and a dielectric wall protrusion extending longitudinally from the main portion of the dielectric wall. The dielectric wall protrusion contacts the sidewall of the channel layer. Compared with a dielectric wall without the dielectric wall protrusion or with flush sidewalls, the dielectric wall protrusion in this embodiment of the invention makes it easier for the dielectric wall to deform under stress, thereby reducing the dielectric wall's resistance to stress in the channel layer. This reduces the impact of the dielectric wall on the stress applied to the channel layer by the source / drain doping layer, thereby improving the carrier mobility in the channel layer and enhancing the performance of the semiconductor structure.

[0011] In an optional embodiment, the bottom wall of the dielectric wall protrusion is recessed relative to the bottom wall of the channel layer, and the top wall of the dielectric wall protrusion is recessed relative to the top wall of the channel layer. This exposes the top and bottom corners of the channel layer near the dielectric wall, reducing the contact area between the dielectric wall and the channel layer. The source / drain doped layer applies stress to the channel layer to improve carrier mobility in the channel region. The reduced contact area between the dielectric wall and the channel layer further reduces the barrier effect of the dielectric wall on stress within the channel layer, decreasing the impact of the dielectric wall on the stress applied by the source / drain doped layer to the channel layer. This, in turn, improves carrier mobility within the channel layer and optimizes the performance of the semiconductor structure.

[0012] In the semiconductor structure formation method provided in this embodiment of the invention, the initial dielectric wall is isotropically etched to form a dielectric wall. The dielectric wall includes a main portion protruding from the substrate and a dielectric wall protrusion extending longitudinally from the main portion. The dielectric wall protrusion contacts the sidewall of the channel layer. Compared with a scheme where the dielectric wall does not have the dielectric wall protrusion or has flush sidewalls, in this embodiment of the invention, by forming the dielectric wall protrusion, the dielectric wall protrusion is more likely to deform under stress, thereby reducing the dielectric wall's resistance to stress in the channel layer. This correspondingly reduces the influence of the dielectric wall on the stress applied by the source / drain doped layer to the channel layer, thereby improving the carrier mobility in the channel layer and enhancing the performance of the semiconductor structure.

[0013] In an optional embodiment, during the step of isotropically etching the initial dielectric wall to form the dielectric wall, the bottom wall of the protruding portion of the dielectric wall is recessed relative to the bottom wall of the channel layer, and the top wall of the protruding portion of the dielectric wall is recessed relative to the top wall of the channel layer. This exposes the top and bottom corners of the channel layer near the dielectric wall, reducing the contact area between the dielectric wall and the channel layer. The source / drain doped layer is used to apply stress to the channel layer to improve the carrier mobility in the channel region. The reduced contact area between the dielectric wall and the channel layer further reduces the barrier effect of the dielectric wall on the stress within the channel layer, decreasing the influence of the dielectric wall on the stress applied by the source / drain doped layer to the channel layer. This, in turn, helps to improve the carrier mobility within the channel layer and optimizes the performance of the semiconductor structure.

[0014] In an optional embodiment, after isotropic etching of the initial dielectric wall, before forming the gate structure, the channel layer is rounded at the corners. This rounded corners of the channel layer result in a thickness at the longitudinal end of the channel layer that is less than the thickness at the middle of the channel layer. Consequently, the size of the channel layer in contact with the dielectric wall is smaller than the maximum thickness of the channel layer. This further reduces the barrier effect of the dielectric wall on the stress within the channel layer, decreases the influence of the dielectric wall on the stress applied by the source / drain doped layers to the channel layer, and further improves the carrier mobility within the channel layer. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a semiconductor structure.

[0016] Figures 2 to 3 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0017] Figures 4 to 19 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0018] As the background technology shows, the performance of current forksheet devices needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using an example of a semiconductor structure.

[0019] Figure 1 This is a schematic diagram of a semiconductor structure. Specifically, Figure 1 It is a cross-sectional view taken at the location of the channel structure layer along the direction perpendicular to the extension of the channel structure layer (i.e., longitudinal direction).

[0020] The semiconductor structure includes: a substrate 10, comprising discrete device cell regions (not shown), each device cell region including a first sub-device region i and a second sub-device region ii arranged longitudinally at intervals, the first sub-device region i being used to form a first type transistor and the second sub-device region ii being used to form a second type transistor, the first type transistor and the second type transistor having different channel conductivity types; a protrusion 11, protruding from the substrate 10 of the first sub-device region i and the second sub-device region ii and extending laterally; a channel structure layer 12, located on the protrusion 11 and spaced apart from the protrusion 11, the channel structure layer 12 including one or more spaced channel layers 13; a dielectric wall 14, located longitudinally on the substrate 10 between the channel structure layers 12 and in contact with the sidewall of the channel structure layer 12; and a gate structure 15, spanning the top of the channel structure layer 12 and surrounding the channel layer 13 exposed by the dielectric wall 14.

[0021] The semiconductor structure is a fork-type gate transistor. The first sub-device region i and the second sub-device region ii are isolated by the dielectric wall, so that the distance between the first sub-device region i and the second sub-device region ii is closer, which is beneficial to the miniaturization of device size and the improvement of circuit integration.

[0022] The semiconductor structure typically includes a source / drain doped layer (not shown), located on the protrusions 11 on both sides of the gate structure 15 and in contact with the channel structure layer 12. The source / drain doped layer is used to provide stress to the channel layer 13 to improve the mobility of charge carriers.

[0023] However, since the dielectric wall 14 is provided between the channel layers 13 of adjacent sub-device regions ii in the longitudinal direction (i.e., perpendicular to the extension direction of the channel structure layer), and the sidewall of the channel layer 14 is in contact with the dielectric wall 14, the dielectric wall 14 easily hinders the stress applied by the source and drain doped layers to the channel layer 13. As a result, the stress of the channel layer 13 is small near the dielectric wall 14, and the effect of increasing the carrier mobility of the device channel is not obvious, resulting in poor device performance.

[0024] To address the aforementioned technical problem, this invention provides a semiconductor structure in which the dielectric wall includes a dielectric wall protrusion extending longitudinally from the main portion of the dielectric wall. The dielectric wall protrusion contacts the sidewall of the channel layer. Furthermore, the bottom wall of the dielectric wall protrusion is recessed relative to the bottom wall of the channel layer, and the top wall of the dielectric wall protrusion is recessed relative to the top wall of the channel layer. This allows the dielectric wall to expose the top and bottom corners of the channel layer near the dielectric wall, reducing the contact area between the dielectric wall and the channel layer. The source / drain doped layer applies stress to the channel layer to improve carrier mobility in the channel region. The reduced contact area between the dielectric wall and the channel layer correspondingly reduces the barrier effect of the dielectric wall on stress within the channel layer, thus reducing the influence of the dielectric wall on the stress applied by the source / drain doped layer to the channel layer. This, in turn, improves carrier mobility within the channel layer and optimizes the performance of the semiconductor structure.

[0025] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figure 2 and Figure 3 A schematic diagram of an embodiment of the semiconductor structure of the present invention is shown. Figure 2 This is a cross-sectional view at the location of the trench structure layer along the direction perpendicular to the extension of the trench structure layer. Figure 3 for Figure 2 A sectional view along the B-B1 direction.

[0026] like Figure 2 and Figure 3 As shown, in this embodiment, the semiconductor structure includes: a substrate 100, including discrete device unit regions 100A, each device unit region 100A including a plurality of sub-device regions I arranged longitudinally; a protrusion 110, protruding from the substrate 100 of the sub-device regions I, the protrusion 110 extending laterally; a channel structure layer 120, located on the protrusion 110 and spaced apart from the protrusion 110, the channel structure layer 120 including one or more channel layers 130 arranged sequentially from bottom to top; and a dielectric wall 140 located along the longitudinal direction in adjacent sub-device regions. On the substrate 100 between I, the dielectric wall 140 includes a dielectric wall main portion 41 protruding from the substrate 100 and a dielectric wall protrusion 42 protruding longitudinally from the dielectric wall main portion 41, the dielectric wall protrusion 42 contacting the sidewall of the channel layer 130; a gate structure 300, located on each sub-device region I, spanning the top of the channel structure layer 120 of the sub-device region I and surrounding the exposed channel layer 130 of the dielectric wall 140; and a source / drain doped layer 160, located on the protrusions 110 on both sides of the gate structure 300 and contacting the channel structure layer 120.

[0027] The substrate 100 is used to provide a process platform for the formation of fork-type gate transistors.

[0028] In this embodiment, the substrate 100 is a silicon substrate, meaning the substrate material is single-crystal silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0029] The device unit area 100A is used to form device units.

[0030] The device unit area 100A includes a plurality of sub-device areas I arranged longitudinally. As one embodiment, the device unit area 100A includes two sub-device areas I, namely, a first sub-device area I(a) and a second sub-device area I(b) arranged longitudinally. In other embodiments, the number of sub-device areas included in the device unit area may be greater than two, for example, three, four, etc.

[0031] In this embodiment, the first sub-device region I(a) is used to form a first type transistor, and the second sub-device region I(b) is used to form a second type transistor. The second type transistor and the first type transistor have different channel conductivity types.

[0032] As an example, the first type of transistor is a PMOS transistor, and the second type of transistor is an NMOS transistor. In other embodiments, the first type of transistor may be an NMOS transistor, and the second type of transistor may be a PMOS transistor.

[0033] In this embodiment, the protrusion 110 and the substrate 100 are integrally formed, and the material of the protrusion 110 is the same as that of the substrate 100, which is silicon. In other embodiments, the material of the protrusion may be different from that of the substrate. The material of the protrusion may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0034] In this embodiment, the protrusion 110 is a fin-type structure.

[0035] In this embodiment, the protrusion 110 extends along the lateral direction, and the plurality of protrusions 110 on the substrate 100 are arranged at intervals along the longitudinal direction, which is perpendicular to the lateral direction.

[0036] The semiconductor structure further includes an isolation structure 150 located on the substrate 100 on the side of the protrusion 110. In this embodiment, the top surface of the isolation structure 150 is flush with the top surface of the protrusion 110.

[0037] The isolation structure 150 is used to isolate adjacent protrusions 110 and also to isolate the gate structure 300 from the substrate 100.

[0038] In this embodiment, the material of the isolation structure 150 is silicon oxide. The isolation structure 150 can also be other suitable insulating materials.

[0039] The channel structure layer 120 is used to provide a conductive channel for the field-effect transistor.

[0040] In this embodiment, the extension direction of the channel structure layer 120 is the same as the extension direction of the protrusion 110, both extending laterally.

[0041] In this embodiment, to improve process compatibility, the channel layer 130 of the different sub-device regions I is made of the same material. As one embodiment, the channel layer 130 is made of silicon. In other embodiments, the channel layer material may also be SiGe. In still other embodiments, the channel layer material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0042] In other embodiments, the channel layer material can be different for different sub-device regions. For example, when adjacent sub-device regions are used to form transistors with different channel conductivity types, the channel layer material is Si for the sub-device region used to form an NMOS transistor, and SiGe for the sub-device region used to form a PMOS transistor.

[0043] As an example, there are multiple channel layers 130, which are arranged alternately from bottom to top. Specifically, in this embodiment, there are three channel layers 130. In other embodiments, the number of channel layers may be one, two, four, etc.

[0044] In this embodiment, the corners of the channel layer 130 surrounded by the gate structure 300 are rounded, that is, the top and bottom corners of the channel layer 130 surrounded by the gate structure 300 are smooth corners. As a result, the thickness of the end of the channel layer 130 along the longitudinal direction is correspondingly smaller than the thickness of the middle position of the channel layer 130. This makes the size of the channel layer 130 in contact with the dielectric wall 140 smaller than the maximum thickness of the channel layer 130. This further helps to reduce the resistance of the dielectric wall 140 to the stress in the channel layer 130, reduce the influence of the dielectric wall 140 on the stress applied by the source / drain doped layer 160 to the channel layer 130, and further improve the carrier mobility in the channel layer 130.

[0045] In other embodiments, depending on actual process requirements, the corners of the trench layer may not be rounded; the corners of the trench layer may be right angles or other angles.

[0046] The dielectric wall 140 serves to physically isolate the channel structure layer 120 and source / drain doped layer 160 of adjacent sub-device regions I, so as to achieve a smaller spacing between adjacent transistors.

[0047] In this embodiment, the dielectric wall 140 is used to isolate the channel structure layer 120 and the source / drain doped layer 160 of the first sub-device region I(a) and the second sub-device region I(b), thereby achieving a smaller spacing between the first type transistor and the second type transistor.

[0048] The top surface of the dielectric wall 140 is higher than the top surface of the channel structure layer 120 and the top surface of the source / drain doped layer 160, so that the dielectric wall 140 can isolate the channel structure layer 120 and the source / drain doped layer 150 of the adjacent sub-device region I.

[0049] In this embodiment, along the longitudinal direction, the dielectric wall 140 is located on the isolation structure 150 between adjacent channel structure layers 120.

[0050] The dielectric wall 140 is made of a dielectric material, which includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon carbonitride-boronide. As an example, the dielectric wall 140 is made of silicon nitride.

[0051] The dielectric wall protrusion 42 contacts the sidewall of the channel layer 130. Compared with the scheme where the dielectric wall does not have the dielectric wall protrusion or has a flush sidewall, in this embodiment, by providing the dielectric wall protrusion 42, the dielectric wall protrusion 42 is more likely to deform under stress, thereby helping to reduce the resistance of the dielectric wall 140 to stress in the channel layer. Correspondingly, it reduces the influence of the dielectric wall 140 on the stress applied by the source / drain doped layer 160 to the channel layer 130, which in turn helps to improve the carrier mobility in the channel layer 130 and improve the performance of the semiconductor structure.

[0052] In this embodiment, the bottom wall of the dielectric wall protrusion 42 is recessed relative to the bottom wall of the channel layer 130, and the top wall of the dielectric wall protrusion 42 is also recessed relative to the top wall of the channel layer 130. This allows the dielectric wall 140 to expose the top and bottom corners of the channel layer 130 near the dielectric wall 130, reducing the contact area between the dielectric wall 140 and the channel layer 130. The source / drain doped layer 160 applies stress to the channel layer 130 to improve carrier mobility in the channel region. The reduced contact area between the dielectric wall 140 and the channel layer 130 further reduces the hindering effect of the dielectric wall 140 on the stress within the channel layer 130, thus reducing the influence of the dielectric wall 140 on the stress applied by the source / drain doped layer 160 to the channel layer 130. This, in turn, helps to improve the carrier mobility within the channel layer 130 and optimizes the performance of the semiconductor structure.

[0053] In this embodiment, the dielectric wall main part 41 and the dielectric wall protrusion 42 are an integral structure, which is beneficial to improving the isolation effect of the dielectric wall 140 on adjacent sub-device regions I.

[0054] In this embodiment, the corners of the channel layer 130 are rounded because, during the formation of the semiconductor structure, the gate structure 300 is typically formed in the gate opening and the through-hole. After the gate opening and the through-hole are formed, the initial dielectric wall is isotropically etched to form the dielectric wall 140, thereby exposing the corners of the channel layer 130 near the end of the dielectric wall 140. After the dielectric wall 140 is formed, the corners of the channel layer 130 are rounded to make the corners of the channel layer 130 rounded.

[0055] It should be noted that the first indentation size is the size by which the bottom wall of the dielectric wall protrusion 42 is recessed relative to the bottom wall of the channel layer 130, or the size by which the top wall of the dielectric wall protrusion 42 is recessed relative to the top wall of the channel layer 130. This first indentation size should not be too small or too large. If the indentation size of the bottom wall of the dielectric wall protrusion 42 relative to the bottom wall of the channel layer 130 is too small, the reduction in the contact area between the channel layer 130 and the dielectric wall 140 will be insignificant. If the indentation size of the bottom wall of the dielectric wall protrusion 42 relative to the bottom wall of the channel layer 130 is too large, the contact area between the dielectric wall protrusion 42 and the channel layer 130 will be too small, potentially increasing process risks. Therefore, in this embodiment, the first indentation size is 7.5 nanometers to 15 nanometers. For example, the first indentation size is 8 nanometers, 9 nanometers, 10 nanometers, etc.

[0056] It should also be noted that, along the longitudinal direction, the dimension by which one sidewall of the dielectric wall main portion 41 is recessed relative to the same sidewall of the dielectric wall protrusion 42 is the second recess dimension. This second recess dimension should not be too small or too large. If the second recess dimension is too small, it can easily lead to the first recess dimension also being too small, and it can also easily lead to the exposed area of ​​the corner at the end of the channel layer 130 near the dielectric wall 140 being too small. During the corner rounding process of the channel layer 130, the arc of the corner at the end of the channel layer 130 near the dielectric wall 140 will be too small. Therefore, in this embodiment, along the longitudinal direction, one sidewall of the dielectric wall main portion 41 is recessed by 7.5 nanometers to 15 nanometers relative to the same sidewall of the dielectric wall protrusion 42.

[0057] The gate structure 300 located on each of the sub-device regions I is used to control the opening and closing of the conductive channel of the corresponding sub-device region I.

[0058] As an example, device cell region 100A includes a first sub-device region I(a) and a second sub-device region I(b). A gate structure 300 located on the first sub-device region I(a) serves as a first gate structure 300(a), and a gate structure 300 located on the second sub-device region I(b) serves as a second gate structure 300(b). The first gate structure 300(a) controls the opening and closing of the conductive channel in the first sub-device region I(a), and the second gate structure 300(b) controls the opening and closing of the conductive channel in the second sub-device region I(b).

[0059] As one embodiment, the gate structure 300 is a metal gate structure. The material of the gate structure 300 includes one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0060] The gate structure 300 may include a work function layer (not shown) and a gate electrode layer (not shown) located on the work function layer. The work function layer may or may not fill the space between adjacent channel layers 130 or between the protrusion 110 and adjacent channel layers 130.

[0061] In this embodiment, the first type transistor is a PMOS transistor, and the first gate structure 300(a) includes a first work function layer; the second type transistor is an NMOS transistor, and the second gate structure 300(b) includes a second work function layer.

[0062] The work function layer is used to adjust the work function of the transistor. Accordingly, the first work function layer is made of P-type work function material, and the second work function layer is made of N-type work function material.

[0063] In this embodiment, the first work function layer and the second work function layer are made of different materials. By setting the dielectric wall 140, it is beneficial to prevent the formation steps of the first work function layer and the second work function layer from affecting each other during the formation of the first gate structure 300(a) and the second gate structure 300(b), thereby improving the integrity of the first gate structure 300(a) and the second gate structure 300(b) and thus improving the performance of the semiconductor structure.

[0064] The gate electrode layer serves as an electrode to achieve electrical connection between the gate structure 300 and external circuits or other interconnect structures. In this embodiment, the gate electrode layers of the first gate structure 300(a) and the second gate structure 300(b) are made of the same material because the gate electrode layers of the first gate structure 300(a) and the second gate structure 300(b) are formed in the same step after the first work function layer and the second work function layer are formed.

[0065] In this embodiment, a metal gate structure 300 is used as an example for illustration. In other embodiments, based on actual process requirements, the gate structure can also be other types of gate structures, such as polycrystalline silicon gate structures or amorphous silicon gate structures.

[0066] In this embodiment, the gate structures 300 of adjacent sub-device regions I along the longitudinal direction are in contact with the top of the dielectric wall 140, so that the gate structures 300 of adjacent sub-device regions I can be electrically connected, so that the transistors of adjacent sub-device regions I can be used in conjunction.

[0067] In this embodiment, the first gate structure 300(a) and the second gate structure 300(b) are in contact on the top of the dielectric wall 140.

[0068] In this embodiment, along the lateral direction, the sidewall of the gate structure 300 is recessed relative to the sidewall of the same side of the channel layer 130; the portion of the gate structure 300 that spans the channel structure layer 120 is the first portion 300 (1), and the portion of the gate structure 300 located between adjacent channel layers 130, or between the protrusion and the channel layer 130 adjacent to the protrusion 110, is the second portion 300 (2).

[0069] In this embodiment, the semiconductor structure further includes: a gate dielectric layer 310 located between the surface of the channel layer 130 and the gate structure 300, and located between the dielectric wall 140 and the gate structure 300. In this embodiment, the gate dielectric layer 310 is also located between the gate structure 300 and the protrusion 110, and between the gate structure 300 and the isolation structure 150.

[0070] The gate dielectric layer 310 is used to achieve electrical isolation between the gate structure 300 and the channel. The material of the gate dielectric layer 310 includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3.

[0071] The gate dielectric layer 310 may be a gate oxide layer or a high-k gate dielectric layer, or the gate dielectric layer 310 may include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer.

[0072] The gate oxide layer can be made of silicon oxide or silicon oxynitride. The high-k gate dielectric layer is made of a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0073] As one embodiment, the gate dielectric layer 310 is a high-k gate dielectric layer.

[0074] In this embodiment, the semiconductor structure further includes: a gate sidewall 170 located on the sidewall of the first portion 300 (1); and an inner sidewall 180 located laterally between the second portion 300 (2) and the source / drain doped layer 160.

[0075] The gate sidewall 170 also spans a portion of the channel structure layer 120. The gate sidewall 170 is used to define the formation location of the source / drain doped layer 160 and to isolate the source / drain doped layer 160 from the gate structure 300. The gate sidewall 170 is also used to protect the sidewall of the first portion 300 (1).

[0076] In this embodiment, the material of the gate sidewall 170 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material, and the gate sidewall 170 is a single-layer or multi-layer structure. As an example, the gate sidewall 170 is a single-layer structure, and the material of the gate sidewall 170 is silicon nitride.

[0077] The inner wall 180 is used to isolate the source / drain doped layer 160 from the gate structure 300, and also to increase the distance between the source / drain doped layer 160 and the gate structure 300, so as to reduce the parasitic capacitance between the gate structure 300 and the source / drain doped layer 160.

[0078] In this embodiment, the inner sidewall 180 is made of an insulating material to achieve isolation between the source / drain doped layer 160 and the gate structure 300. In this embodiment, the material of the inner sidewall 180 includes silicon nitride, silicon oxide, silicon oxynitride, a low-k dielectric material, or an ultra-low-k dielectric material. As an example, the material of the inner sidewall 180 is silicon nitride.

[0079] The source / drain doped layer 160 is used as the source or drain of the field-effect transistor. When the field-effect transistor is working, the source / drain doped layer 160 is used to provide a source of charge carriers.

[0080] In this embodiment, the source / drain doped layer 160 includes a stress layer doped with ions. The stress layer is used to provide stress to the channel region, thereby improving the carrier mobility.

[0081] In this embodiment, when forming a PMOS transistor, the source / drain doped layer 160 includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe; when forming an NMOS transistor, the source / drain doped layer 160 includes a stress layer doped with N-type ions, and the material of the stress layer is Si or SiC.

[0082] In this embodiment, the first type transistor is a PMOS transistor, and the source / drain doped layer 160 of the first sub-device region I(a) includes a stress layer doped with P-type ions; the second type transistor is an NMOS transistor, and the source / drain doped layer 160 of the second sub-device region I(b) includes a stress layer doped with N-type ions.

[0083] The source / drain doped layers 160 of adjacent sub-device regions I are isolated by the dielectric wall 140, thereby avoiding mutual interference between the processes of forming source / drain doped layers 160 of different sub-device regions I when the materials and dopants of the source / drain doped layers 160 of adjacent sub-device regions I are different.

[0084] In this embodiment, the source / drain doped layer 160 is located on the protrusions 110 on both sides of the gate structure 300 and the gate sidewall 170. In this embodiment, the source / drain doped layer 160 covers the channel structure layer 120 and the sidewalls of the inner sidewall 180.

[0085] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 190, located on the substrate 100 on the side of the gate structure 300, and covering the source / drain doped layer 160. Specifically, the interlayer dielectric layer 190 is located on the isolation structure 150.

[0086] The interlayer dielectric layer 190 is used to isolate adjacent devices. In this embodiment, the material of the interlayer dielectric layer 190 is silicon oxide. The material of the interlayer dielectric layer 190 can also be other insulating materials.

[0087] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 4 to 19 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0088] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0089] refer to Figures 4 to 5 , Figure 4 This is a cross-sectional view at the location of the laminated structure along the direction perpendicular to the extension of the channel laminate. Figure 5 for Figure 4 A cross-sectional view along the B-B1 direction provides a substrate 100, including discrete device cell regions 100A, each device cell region 100A including a plurality of longitudinally arranged sub-device regions I, each sub-device region I having a laterally extending and protruding protrusion 110 formed on the substrate 100, the protrusion 110 having a stacked structure 200, the stacked structure 200 including one or more stacked channel stacks 210, an initial dielectric wall 230 formed between the longitudinal stacked structures 200 and in contact with the stacked structure 200.

[0090] The substrate 100 is used to provide a process platform for subsequent process fabrication.

[0091] In this embodiment, the substrate 100 is a silicon substrate, meaning the substrate material is single-crystal silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0092] The device unit area 100A is used to form device units.

[0093] The device unit area 100A includes a plurality of sub-device areas I arranged longitudinally. As one embodiment, the device unit area 100A includes two sub-device areas I, namely, a first sub-device area I(a) and a second sub-device area I(b) arranged longitudinally. In other embodiments, the number of sub-device areas included in the device unit area may be greater than two, for example, three, four, etc.

[0094] In this embodiment, the first sub-device region I(a) is used to form a first type transistor, and the second sub-device region I(b) is used to form a second type transistor. The second type transistor and the first type transistor have different channel conductivity types.

[0095] As an example, the first type of transistor is a PMOS transistor, and the second type of transistor is an NMOS transistor. In other embodiments, the first type of transistor may be an NMOS transistor, and the second type of transistor may be a PMOS transistor.

[0096] In this embodiment, the protrusion 110 and the substrate 100 are integrally formed, and the material of the protrusion 110 is the same as that of the substrate 100, which is silicon. In other embodiments, the material of the protrusion may be different from that of the substrate. The material of the protrusion may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0097] In this embodiment, the protrusion 110 extends along the lateral direction, and the plurality of protrusions 110 on the substrate 100 are arranged at intervals along the longitudinal direction, which is perpendicular to the lateral direction.

[0098] In this embodiment, an isolation structure 150 is also formed on the substrate 100 on the side of the protrusion 110.

[0099] The isolation structure 150 is used to isolate adjacent protrusions 110 and also to isolate the gate structure 300 from the substrate 100.

[0100] In this embodiment, the material of the isolation structure 150 is silicon oxide. The isolation structure 150 can also be other suitable insulating materials.

[0101] The channel stack 210 provides the technological basis for the subsequent formation of the channel layer 130 with a suspended arrangement. Specifically, the channel layer 130 is used to provide the conductive channel for the field-effect transistor, and the sacrificial layer 220 is used to support the channel layer 130, thereby providing the technological basis for the subsequent realization of the suspended arrangement of the channel layer 130. The sacrificial layer 220 is also used to occupy space for the subsequent formation of the gate structure.

[0102] As an example, the sidewalls of the stacked structure 200 and the protrusion 110 are flush, and the stacked structure 200 and the protrusion 110 are fin-type structures.

[0103] In this embodiment, in order to improve process compatibility, the channel layer 130 of different sub-device regions I is made of the same material, and the sacrificial layer 220 of different sub-device regions I is made of the same material.

[0104] In one embodiment, the channel layer 130 is made of Si, and the sacrificial layer 220 is made of SiGe. During the subsequent removal of the sacrificial layer 220, the etching selectivity of SiGe and Si is relatively high. Therefore, by setting the material of the sacrificial layer 220 to SiGe and the material of the channel layer 130 to Si, the impact of the sacrificial layer 220 removal process on the channel layer 130 can be effectively reduced, thereby improving the quality of the channel layer 130 and ultimately contributing to improved device performance.

[0105] In other embodiments, the channel layer may be made of SiGe, and the sacrificial layer may be made of Si. In still other embodiments, the channel layer may be made of one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0106] In other embodiments, the channel layer material can be different for different sub-device regions. For example, when adjacent sub-device regions are used to form transistors with different channel conductivity types, the channel layer material is Si for the sub-device region used to form an NMOS transistor, and SiGe for the sub-device region used to form a PMOS transistor.

[0107] As an example, there are multiple channel stacks 210, and the stacking direction of the multiple channel stacks 210 is perpendicular to the surface of the substrate 100.

[0108] Specifically, in this embodiment, the number of channel stacks 210 is three. In other embodiments, the number of channel stacks may be one, two, four, etc.

[0109] Along the longitudinal direction, the initial dielectric wall 230 is used to isolate the stacked structure 200 of adjacent sub-device regions I so that adjacent sub-device regions I can achieve a smaller spacing.

[0110] The top surface of the initial dielectric wall 230 is higher than the top surface of the stacked structure 200, so that the initial dielectric wall 230 can isolate the stacked structure 200 of the adjacent sub-device region I.

[0111] In this embodiment, along the longitudinal direction, the initial dielectric wall 230 is formed on the isolation structure 150 between adjacent stacked structures 200.

[0112] Therefore, the initial dielectric wall 230 is made of a dielectric material, such as one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon boron carbonitride, thereby ensuring that the initial dielectric wall 230 can function as an isolation barrier. In this embodiment, the initial dielectric wall 230 is made of silicon nitride.

[0113] As one embodiment, the steps of providing a substrate 100, a protrusion 110, a stacked structure 200, an isolation structure 150, and an initial dielectric wall 230 include: providing a substrate 100, a protrusion 110, and a stacked structure 200 located on the protrusion 110; forming an isolation structure 150 on the substrate 100 on the side of the protrusion 110; and forming an initial dielectric wall 230 between the stacked structures 200 of adjacent sub-device regions I along an extension direction perpendicular to the stacked structure 200.

[0114] The steps described above for providing the substrate 100, the protrusion 110, the stacked structure 200, the isolation structure 150, and the initial dielectric wall 230 are merely examples and are not limited thereto. For example, in other embodiments, after providing the substrate, the protrusion, and the stacked structure, an initial dielectric wall may be formed between adjacent protrusions and between adjacent stacked structures along an extension direction perpendicular to the stacked structure; an isolation structure may be formed on the substrate on the side of the protrusion, and the isolation structure may also cover a portion of the sidewall of the initial dielectric wall.

[0115] refer to Figure 6 and Figure 7 , Figure 6 This is a cross-sectional view along the extension direction of the pseudo-gate structure at its location. Figure 7 for Figure 6 A cross-sectional view along the B-B1 direction shows a dummy gate structure 240 formed on the substrate 100, spanning the stacked structure 200 and the initial dielectric wall 230. The dummy gate structure 240 is used to pre-reserve space for the subsequent formation of the gate structure.

[0116] The extension direction of the pseudo-gate structure 240 is perpendicular to the extension direction of the channel stack 200, that is, the pseudo-gate structure 240 extends longitudinally.

[0117] The pseudo-gate structure 240 includes a pseudo-gate layer, which can be a single layer or a stacked structure.

[0118] In this embodiment, the dummy gate structure 240 is a polycrystalline silicon gate or an amorphous silicon structure. The material of the dummy gate layer includes polycrystalline silicon or amorphous silicon.

[0119] In this embodiment, before forming the pseudo-gate structure 240, the forming method further includes forming a pseudo-gate oxide layer 165 on the top surface and sidewalls of the stacked structure 300 and the exposed top surface and sidewalls of the initial dielectric wall 230.

[0120] The dummy gate oxide layer 165 can serve as an etching stop layer when removing the dummy gate structure 240, thereby reducing the probability of damage to the channel layer 130 when removing the dummy gate structure 240.

[0121] In this embodiment, the material of the pseudo-gate oxide layer 165 can be silicon oxide or silicon oxynitride.

[0122] Accordingly, the pseudo-gate structure 240 covers a portion of the top and a portion of the sidewalls of the pseudo-gate oxide layer 165 located on the stacked structure 200 and the initial dielectric wall 230.

[0123] In this embodiment, the method for forming the semiconductor structure further includes forming a gate sidewall 170 on the sidewall of the pseudo-gate structure 240.

[0124] The gate sidewall 170 is used together with the dummy gate structure 240 as an etching mask for the subsequent etching process to form a trench, so as to define the formation location of the source and drain doped layers. The gate sidewall 170 is also used to protect the dummy gate structure 240 and the sidewalls of the subsequent gate structure.

[0125] In this embodiment, the material of the gate sidewall 170 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material, and the gate sidewall 170 is a single-layer or multi-layer structure. As an example, the gate sidewall 170 is a single-layer structure, and the material of the gate sidewall 170 is silicon nitride.

[0126] refer to Figures 8 to 11 Source / drain doped layers 160 are formed in the stacked structures 200 on both sides of the pseudo-gate structure 240. The source / drain doped layers 160 are used as the source or drain of the field-effect transistor. When the field-effect transistor is working, the source / drain doped layers 160 are used to provide a source of charge carriers.

[0127] In this embodiment, the source / drain doped layer 160 includes a stress layer doped with ions. The stress layer is used to provide stress to the channel region, thereby improving the carrier mobility.

[0128] In this embodiment, when forming a PMOS transistor, the source / drain doped layer 160 includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe; when forming an NMOS transistor, the source / drain doped layer 160 includes a stress layer doped with N-type ions, and the material of the stress layer is Si or SiC.

[0129] In this embodiment, the first type transistor is a PMOS transistor, and the source / drain doped layer 160 of the first sub-device region I(a) includes a stress layer doped with P-type ions; the second type transistor is an NMOS transistor, and the source / drain doped layer 160 of the second sub-device region I(b) includes a stress layer doped with N-type ions.

[0130] The source and drain doped layers 160 of adjacent sub-device regions I are isolated by the initial dielectric wall 230, thereby avoiding mutual interference between the processes of forming source and drain doped layers 160 of different sub-device regions I when the materials and dopants of the source and drain doped layers 160 of adjacent sub-device regions I are different.

[0131] In this embodiment, the source / drain doped layer 160 is formed in the stacked structure 200 on both sides of the dummy gate structure 240 and the gate sidewall 170.

[0132] In this embodiment, the step of forming the source / drain doped layer 160 includes: as follows Figure 8 As shown, the stacked structures 200 on both sides of the dummy gate structure 240 and the gate sidewall 170 are removed, and a groove 250 is formed in the stacked structure 200; as Figures 9 to 11As shown, the source / drain doped layer 160 is formed in the groove 250.

[0133] The groove 250 is used to provide space for the formation of source and drain doped layers.

[0134] In this embodiment, an epitaxial process is used to form a stress layer, and ions are self-doped in situ during the formation of the stress layer. The stress layer doped with ions is used as the source / drain doped layer 160.

[0135] In this embodiment, the ion doping type and material of the source / drain doped layers 160 of the first sub-device region I(a) and the second sub-device region I(b) are different. Therefore, in different steps, the corresponding source / drain doped layers 160 are formed in the groove 250 of the first sub-device region I(a) and the groove 250 of the second sub-device region I(b).

[0136] In this embodiment, the method for forming the semiconductor structure further includes: after forming the groove 250, and before forming the source / drain doped layer 160 in the groove 250, such as... Figure 9 As shown, along the transverse direction, a portion of the thickness of the sacrificial layer 220 on the sidewall of the groove 250 is etched to form a sidewall groove 175 on the sidewall of the groove 250; as Figure 10 As shown, the inner sidewall 180 is filled in the sidewall groove 175.

[0137] The sidewall groove 175 is used to provide space for the formation of the inner sidewall 180.

[0138] In this embodiment, a vapor etching process is used to etch a portion of the thickness of the sacrificial layer 220 on the sidewall of the groove 250 along the extension direction of the channel layer.

[0139] Specifically, in this embodiment, the sacrificial layer 220 is made of SiGe, and the channel layer 130 is made of Si. The sacrificial layer 220 on the sidewall of the groove 250 is etched using HCl vapor. The etching rate of HCl vapor on SiGe material is much greater than that on Si material, which can effectively reduce the probability of damage to the channel layer 130.

[0140] In other embodiments, when the channel layer is made of SiGe and the sacrificial layer is made of Si, a dry etching process can be used to etch a portion of the thickness of the sacrificial layer along the extension direction of the channel layer.

[0141] Subsequently, a gate structure is formed at the location of the sacrificial layer 220 and the pseudo-gate structure 240. The inner wall 180 is used to isolate the source / drain doped layer 160 from the gate structure and to increase the distance between the source / drain doped layer 160 and the gate structure, thereby reducing the parasitic capacitance between the gate structure and the source / drain doped layer 160.

[0142] Accordingly, the source / drain doped layer 160 covers the sidewalls of the channel layer 130 and the inner sidewall 180.

[0143] In this embodiment, the inner sidewall 180 is made of an insulating material to achieve isolation between the source / drain doped layer 160 and the gate structure. The material of the inner sidewall 180 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material. As an example, the material of the inner sidewall 180 is silicon nitride.

[0144] In this embodiment, the formation method further includes: forming an interlayer dielectric layer 190 on the substrate 100 on the side of the pseudo-gate structure 240 and the gate sidewall 170, covering the source and drain doped layer 160.

[0145] Specifically, the interlayer dielectric layer 190 is located on the isolation structure 150.

[0146] The interlayer dielectric layer 190 is used to isolate adjacent devices. In this embodiment, the material of the interlayer dielectric layer 190 is silicon oxide. The material of the interlayer dielectric layer 190 can also be other insulating materials.

[0147] In this embodiment, the interlayer dielectric layer 190 also exposes the top of the dummy gate structure 240 to facilitate subsequent removal of the dummy gate structure 240.

[0148] refer to Figures 12 to 13 , Figure 12 This is a cross-sectional view at the gate opening location along the direction perpendicular to the extension of the channel stack 210. Figure 13 for Figure 12 A cross-sectional view along the B-B1 direction shows the removal of the dummy gate structure 240, forming a gate opening 260, which exposes the stacked structure 200.

[0149] The gate opening 260 provides partial space for forming the gate structure. The gate opening 260 exposes the channel stack 210 to facilitate subsequent removal of the sacrificial layer 220 through the gate opening 260.

[0150] In this embodiment, the gate opening 260 spans the stacked structure 200, and the gate opening 260 is located in the interlayer dielectric layer 190 and is surrounded by the gate sidewall 170.

[0151] In this embodiment, the pseudo-gate oxide layer 165 is used as the etch stop layer to remove the pseudo-gate structure 240, thereby reducing the probability of damage to the channel layer 130 caused by removing the pseudo-gate structure 240.

[0152] In this process, after removing the pseudo-gate structure 240, the pseudo-gate oxide layer 165 exposed by the gate opening 260 is also removed.

[0153] The pseudo gate oxide layer 165 is thinner than the pseudo gate structure 240, so the process of removing the pseudo gate oxide layer 165 is simpler and the removal time is shorter. Removing the pseudo gate oxide layer 165 is less likely to damage the channel layer 130.

[0154] refer to Figures 14 to 15 , Figure 14 This is a cross-sectional view at the gate opening location along the direction perpendicular to the channel stack extension. Figure 15 for Figure 14 A cross-sectional view along the B-B1 direction shows the removal of the sacrificial layer 220 in the channel stack 210, forming a through-slot 270. The through-slot 270 is surrounded by the protrusion 110, the channel layer 130 adjacent to the protrusion 110, and the initial dielectric wall 230. Alternatively, the through-slot 270 is surrounded by the adjacent channel layer 130 and the initial dielectric wall 230. The through-slot 270 is connected to the gate opening 260.

[0155] The through-slot 270 and the gate opening 260 together provide space for the subsequent formation of the gate structure. The through-slot 270 is connected to the gate opening 260, so that after the gate structure is filled in the through-slot 270 and the gate opening 260, the gate structure can surround the channel layer 130.

[0156] The through-slot 270 and gate opening 260 also expose the top surface and sidewalls of the initial dielectric wall 230 that are not in contact with the channel layer 130, so that the exposed initial dielectric wall 230 can be etched subsequently.

[0157] The sacrificial layer 220 is removed after the source / drain doped layer 160 is formed. Therefore, after the sacrificial layer 220 is removed, the two ends of the channel layer 130 are connected to the source / drain doped layer 160 along the extension direction of the channel layer 130, and are suspended in the gate opening 260 so that the subsequent gate structure can surround the channel layer 130.

[0158] In this embodiment, after removing the sacrificial layer 220, one or more spaced-apart channel layers 130 are used to form a channel structure layer 120, which is spaced apart from the protrusion 110.

[0159] In this embodiment, a vapor etching process is used to remove the sacrificial layer 220. Specifically, the channel layer 130 is made of Si, and the sacrificial layer 30 is made of SiGe. Therefore, the sacrificial layer 30 exposed by the gate opening 260 is removed by HCl vapor.

[0160] refer to Figure 16The initial dielectric wall 230 is isotropically etched to form a dielectric wall 140. The dielectric wall 140 includes a main dielectric wall portion 41 protruding from the substrate 100 and a dielectric wall protrusion 42 protruding longitudinally from the main dielectric wall portion 41. The dielectric wall protrusion 42 is in contact with the sidewall of the channel layer 130.

[0161] The initial dielectric wall 230 is isotropically etched to form a dielectric wall 140, which includes a main dielectric wall portion 41 and a dielectric wall protrusion 42. The dielectric wall protrusion 42 contacts the sidewall of the channel layer 130. Compared with a dielectric wall without the dielectric wall protrusion or with flush sidewalls, this embodiment forms the dielectric wall protrusion 42, which is more prone to deformation under stress. This helps reduce the resistance of the dielectric wall 140 to stress in the channel layer 130, and correspondingly reduces the influence of the dielectric wall 140 on the stress applied to the channel layer 130 by the source / drain doped layer 160. This, in turn, helps improve the carrier mobility in the channel layer 130 and enhances the performance of the semiconductor structure.

[0162] In this embodiment, the bottom wall of the dielectric wall protrusion 42 is recessed relative to the bottom wall of the channel layer 130, and the top wall of the dielectric wall protrusion 42 is also recessed relative to the top wall of the channel layer 130. This allows the dielectric wall 140 to expose the top and bottom corners of the channel layer 130 near the dielectric wall 130, reducing the contact area between the dielectric wall 140 and the channel layer 130. The source / drain doped layer 160 applies stress to the channel layer 130 to improve the carrier mobility in the channel region. The reduced contact area between the dielectric wall 140 and the channel layer 130 further reduces the hindering effect of the dielectric wall 140 on the stress within the channel layer 130, thus reducing the influence of the dielectric wall 140 on the stress applied by the source / drain doped layer 160 to the channel layer 130. This, in turn, helps to improve the carrier mobility within the channel layer 130 and optimizes the performance of the semiconductor structure.

[0163] In this embodiment, the dielectric wall 140 is formed by isotropic etching of the initial dielectric wall 230, therefore, the dielectric wall 140 is a monolithic structure.

[0164] It should be noted that the first indentation size is the size by which the bottom wall of the dielectric wall protrusion 42 is recessed relative to the bottom wall of the channel layer 130, or the size by which the top wall of the dielectric wall protrusion 42 is recessed relative to the top wall of the channel layer 130. This first indentation size should not be too small or too large. If the indentation size of the bottom wall of the dielectric wall protrusion 42 relative to the bottom wall of the channel layer 130 is too small, the reduction in the contact area between the channel layer 130 and the dielectric wall 140 will be insignificant. If the indentation size of the bottom wall of the dielectric wall protrusion 42 relative to the bottom wall of the channel layer 130 is too large, the contact area between the dielectric wall protrusion 42 and the channel layer 130 will be too small, potentially increasing process risks. Therefore, in this embodiment, the first indentation size is 7.5 nanometers to 15 nanometers. For example, the first indentation size is 8 nanometers, 9 nanometers, 10 nanometers, etc.

[0165] It should also be noted that, along the longitudinal direction, the dimension by which one sidewall of the dielectric wall main portion 41 is recessed relative to the same sidewall of the dielectric wall protrusion 42 is the second recess dimension. This second recess dimension should not be too small or too large. If the second recess dimension is too small, it can easily lead to the first recess dimension also being too small, and it can also easily lead to the exposed area of ​​the corner at the end of the channel layer 130 near the dielectric wall 140 being too small, making it difficult to subsequently perform corner rounding processing on the channel layer 130. Therefore, in this embodiment, along the longitudinal direction, one sidewall of the dielectric wall main portion 41 is recessed by 7.5 nanometers to 15 nanometers relative to the same sidewall of the dielectric wall protrusion 42.

[0166] In this embodiment, the aforementioned step of removing the sacrificial layer 220 includes: performing a main etching process on the sacrificial layer 220; and performing an over etch process on the sacrificial layer 220 after the main etching process.

[0167] In the process of etching the sacrificial layer 220, the initial dielectric wall 230 is etched isotropically to form the dielectric wall 140. By using the process of removing the sacrificial layer 220 to etch the initial dielectric wall 230 isotropically, it is beneficial to improve process integration and process compatibility, as well as to simplify the process, save costs, and improve production efficiency.

[0168] Specifically, the sacrificial layer 220 is over-etched using a vapor etching process. The vapor etching process is an isotropic etching process, which enables isotropic etching of the initial dielectric wall 230.

[0169] In other embodiments, the initial dielectric wall may be isotropically etched separately. The isotropic etching process includes isotropic plasma etching. The isotropic etching process may also include wet etching.

[0170] refer to Figure 17 Optionally, the method for forming the semiconductor structure further includes: after isotropic etching of the initial dielectric wall 230, rounding the corners of the channel layer 130 exposed by the gate opening 260 and the through trench 270, so that the corners of the channel layer 130 are rounded.

[0171] The corners of the channel layer 130 are rounded to make the corners of the channel layer 130 arc-shaped. That is, the top and bottom corners of the channel layer 130 exposed by the gate opening 260 and the through slot 270 are smooth corners. As a result, the thickness of the end of the channel layer 130 along the longitudinal direction is correspondingly smaller than the thickness of the middle position of the channel layer 130. This makes the size of the channel layer 130 in contact with the dielectric wall 140 smaller than the maximum thickness of the channel layer 1310. This further helps to reduce the resistance of the dielectric wall 140 to the stress in the channel layer 130, reduce the influence of the dielectric wall 140 on the stress applied by the source / drain doped layer 160 to the channel layer 130, and further improve the carrier mobility in the channel layer 130.

[0172] In addition, the corners of the exposed channel layer 130 are rounded, that is, the surface of the exposed channel layer 130 is a smooth surface. In the subsequent process of forming the gate structure surrounding the channel layer 130, it is also beneficial to improve the thickness uniformity and film quality of the gate structure formed on the surface of the channel layer 130.

[0173] In other embodiments, depending on actual process requirements, the corners of the trench layer may not be rounded; the corners of the trench layer may be right angles or other angles.

[0174] In this embodiment, the corner rounding treatment of the channel layer 130 exposed by the gate opening 260 and the through-hole 270 includes: etching the surface of the channel layer 130 exposed by the gate opening 260 and the through-hole 270 using an isotropic plasma etching process; or annealing the surface of the channel layer 130 exposed by the gate opening 260 and the through-hole 270 in a hydrogen atmosphere; or oxidizing the surface of the channel layer 130 exposed by the gate opening 260 and the through-hole 270.

[0175] In particular, the isotropic plasma etching process has a higher etching rate for sharp corners or bends than for flat surfaces. Therefore, when the isotropic plasma etching process is used to etch the surface of the channel layer 130 exposed by the gate opening 260 and the through-hole 270, the etching rate of the corners of the exposed channel layer 130 is faster, making the corners of the exposed channel layer 130 rounded.

[0176] In a hydrogen atmosphere, the exposed surface of the channel layer 130 is annealed, which allows the channel layer 130 to reflow, softening the corners of the exposed channel layer 130 and forming rounded corners. Specifically, hydrogen can break silicon-silicon bonds, thereby softening the channel layer 130.

[0177] During the oxidation process on the surface of the channel layer 130 exposed by the gate opening 260 and the through-hole 270, the oxidation rate at the corner positions is greater than that on the flat surface, thus making it easier to round the corners of the exposed channel layer 130. Specifically, the oxidation process can be a thermal oxidation process. When the corner rounding process includes an oxidation process, the oxide on the surface of the channel layer 130 usually needs to be removed after the oxidation process.

[0178] refer to Figures 18 to 19 After the dielectric wall 140 is formed, a gate structure 300 is formed in the gate opening 260 and the through slot 270 of each of the sub-device regions I.

[0179] The gate structure 300 located on each of the sub-device regions I is used to control the opening and closing of the conductive channel of the corresponding sub-device region I.

[0180] As an example, the device cell region 100A includes a first sub-device region I(a) and a second sub-device region I(b), with a gate structure 300 located on the first sub-device region I(a) serving as a first gate structure 300(a) and a gate structure 300 located on the second sub-device region I(b) serving as a second gate structure 300(b).

[0181] The first gate structure 300(a) is used to control the opening and closing of the conductive channel of the first sub-device region I(a), and the second gate structure 300(b) is used to control the opening and closing of the conductive channel of the second sub-device region I(b).

[0182] As one embodiment, the gate structure 300 is a metal gate structure. The material of the gate structure 300 includes one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0183] The gate structure 300 may include a work function layer (not shown) and a gate electrode layer (not shown) located on the work function layer. The work function layer may or may not fill the space between adjacent channel layers 130 or between the protrusion 110 and adjacent channel layers 130.

[0184] In this embodiment, the first type transistor is a PMOS transistor, and the first gate structure 300(a) includes a first work function layer; the second type transistor is an NMOS transistor, and the second gate structure 300(b) includes a second work function layer.

[0185] The work function layer is used to adjust the work function of the transistor. Accordingly, the first work function layer is made of P-type work function material, and the second work function layer is made of N-type work function material.

[0186] In this embodiment, the first work function layer and the second work function layer are made of different materials. By setting the dielectric wall 140, it is beneficial to prevent the formation steps of the first work function layer and the second work function layer from affecting each other during the formation of the first gate structure 300(a) and the second gate structure 300(b), thereby improving the integrity of the first gate structure 300(a) and the second gate structure 300(b) and thus improving the performance of the semiconductor structure.

[0187] The gate electrode layer serves as an electrode to achieve electrical connection between the gate structure 300 and external circuits or other interconnect structures. In this embodiment, the gate electrode layers of the first gate structure 300(a) and the second gate structure 300(b) are made of the same material because the gate electrode layers of the first gate structure 300(a) and the second gate structure 300(b) are formed in the same step after the first work function layer and the second work function layer are formed.

[0188] In this embodiment, a metal gate structure 300 is used as an example for illustration. In other embodiments, based on actual process requirements, the gate structure can also be other types of gate structures, such as polycrystalline silicon gate structures or amorphous silicon gate structures.

[0189] In this embodiment, the gate structures 300 of adjacent sub-device regions I along the longitudinal direction are in contact with the top of the dielectric wall 140, so that the gate structures 300 of adjacent sub-device regions I can be electrically connected, so that the transistors of adjacent sub-device regions I can be used in conjunction.

[0190] In this embodiment, the first gate structure 300(a) and the second gate structure 300(b) are in contact on the top of the dielectric wall 140.

[0191] In this embodiment, along the lateral direction, the sidewall of the gate structure 300 is recessed relative to the sidewall of the same side of the channel layer 130; the portion of the gate structure 300 that spans the channel structure layer 120 is the first portion 300 (1), and the portion of the gate structure 300 located between adjacent channel layers 130, or between the protrusion and the channel layer 130 adjacent to the protrusion 110, is the second portion 300 (2).

[0192] In this embodiment, after forming the dielectric wall 140 and before forming the gate structure 300, the method for forming the semiconductor structure further includes forming a gate dielectric layer 310 on the bottom and sidewalls of the gate opening 260, the top and sidewalls of the dielectric wall 140, and the surface of the exposed channel layer 130 of the dielectric wall 140.

[0193] The gate dielectric layer 310 is used to achieve electrical isolation between the gate structure 300 and the channel. The material of the gate dielectric layer 310 includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3.

[0194] The gate dielectric layer 310 may be a gate oxide layer or a high-k gate dielectric layer, or the gate dielectric layer 310 may include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer.

[0195] The gate oxide layer can be made of silicon oxide or silicon oxynitride. The high-k gate dielectric layer is made of a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0196] As one embodiment, the gate dielectric layer 310 is a high-k gate dielectric layer.

[0197] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes discrete device unit regions, each device unit region comprising a plurality of sub-device regions arranged longitudinally; A protrusion protrudes from the substrate of the sub-device area, and the protrusion extends laterally; A channel structure layer is located on the protrusion and spaced apart from the protrusion. The channel structure layer includes one or more channel layers spaced apart from bottom to top. A dielectric wall is located on a substrate between adjacent sub-device regions along the longitudinal direction. The dielectric wall includes a main portion of the dielectric wall protruding from the substrate and a dielectric wall protrusion protruding from the main portion of the dielectric wall along the longitudinal direction. The dielectric wall protrusion is in contact with the sidewall of the channel layer. The main portion of the dielectric wall and the dielectric wall protrusion are an integral structure. A gate structure is located on each sub-device region, spanning the top of the channel structure layer of the sub-device region and surrounding the exposed channel layer of the dielectric wall. The source and drain doped layers are located on the protrusions on both sides of the gate structure and are in contact with the channel structure layer.

2. The semiconductor structure as described in claim 1, characterized in that, The substrate material includes one or more of single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The material of the protrusion includes one or more of single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The material of the channel layer includes one or more of single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The dielectric wall material includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon carbonitride.

3. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: an isolation structure located on the substrate on the side of the protrusion; and along the longitudinal direction, the dielectric wall is located on the isolation structure between adjacent channel structure layers.

4. The semiconductor structure as described in claim 1, characterized in that, Along the lateral direction, the sidewalls of the gate structure are recessed relative to the sidewalls on the same side of the channel layer; the portion of the gate structure that spans the channel structure layer is designated as a first portion, and the portion of the gate structure located between adjacent channel layers, or between a protrusion and a channel layer adjacent to the protrusion, is designated as a second portion. The semiconductor structure further includes: a gate sidewall located on the sidewall of the first portion; and an inner sidewall located along the lateral direction between the second portion and the source / drain doped layer. The source and drain doped layers are located on the protrusions on both sides of the gate structure and the gate sidewall; The semiconductor structure further includes an interlayer dielectric layer located on the substrate on the side of the gate structure and covering the source / drain doped layer.

5. The semiconductor structure as described in claim 1, characterized in that, The corners of the channel layer surrounded by the gate structure are rounded.

6. The semiconductor structure as described in claim 1, characterized in that, The bottom wall of the dielectric wall protrusion is recessed relative to the bottom wall of the channel layer, and the top wall of the dielectric wall protrusion is recessed relative to the top wall of the channel layer.

7. The semiconductor structure as described in claim 6, characterized in that, The bottom wall of the dielectric wall protrusion is recessed by 7.5 nanometers to 15 nanometers relative to the bottom wall of the channel layer; the top wall of the dielectric wall protrusion is recessed by 7.5 nanometers to 15 nanometers relative to the top wall of the channel layer; along the longitudinal direction, the side wall of one side of the main portion of the dielectric wall is recessed by 7.5 nanometers to 15 nanometers relative to the same side wall of the dielectric wall protrusion.

8. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a gate dielectric layer located between the surface of the channel layer and the gate structure, and a dielectric wall located between the gate structure; The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3; The material of the gate structure includes one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

9. The semiconductor structure as described in claim 1, characterized in that, The device unit region includes a first sub-device region and a second sub-device region arranged longitudinally; the first sub-device region is used to form a first type transistor, and the second sub-device region is used to form a second type transistor, wherein the second type transistor and the first type transistor have different channel conductivity types.

10. The semiconductor structure as described in claim 1 or 9, characterized in that, The gate structures of adjacent sub-device regions along the longitudinal direction are in contact at the top of the dielectric wall.

11. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including discrete device cell regions, each device cell region including a plurality of longitudinally arranged sub-device regions, wherein a laterally extending and protruding protrusion is formed on the substrate of the sub-device regions, and a stacked structure is formed on the protrusion, the stacked structure including one or more stacked channel stacks, wherein an initial dielectric wall is formed between the stacked structures along the longitudinal direction and in contact with the stacked structure; A pseudo-gate structure is formed on the substrate, spanning the stacked structure and the initial dielectric wall; Source and drain doped layers are formed in the stacked structures on both sides of the pseudo-gate structure; Remove the pseudo-gate structure to form a gate opening and expose the stacked structure; The sacrificial layer in the channel stack is removed to form a through-slot, which is surrounded by the protrusion, the channel layer adjacent to the protrusion, and the initial dielectric wall; or, the through-slot is surrounded by the adjacent channel layer and the initial dielectric wall; the through-slot is connected to the gate opening. The initial dielectric wall is isotropically etched to form a dielectric wall, which includes a main part of the dielectric wall protruding on the substrate and a dielectric wall protrusion protruding longitudinally from the main part of the dielectric wall. The dielectric wall protrusion is in contact with the sidewall of the channel layer. The dielectric wall is a monolithic structure. After the dielectric wall is formed, a gate structure is formed in the gate opening and through slot of each of the sub-device regions.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The step of removing the sacrificial layer includes: performing a main etching process on the sacrificial layer; performing an over-etching process on the sacrificial layer after the main etching process; wherein, during the over-etching process of the sacrificial layer, the initial dielectric wall is subjected to an isotropic etching process to form the dielectric wall.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of providing the substrate, an isolation structure is also formed on the substrate on the side of the protrusion; along the longitudinal direction, the initial dielectric wall is formed on the isolation structure between adjacent stacked structures; After forming the dummy gate structure and before forming the source / drain doped layer, the method for forming the semiconductor structure further includes: forming a gate sidewall on the sidewall of the dummy gate structure; the source / drain doped layer is formed in a stacked structure on both sides of the dummy gate structure and the gate sidewall. The step of forming the source / drain doped layer includes: removing the dummy gate structure and the stacked structure on both sides of the gate sidewall, forming a groove in the stacked structure; and forming the source / drain doped layer in the groove. The method for forming the semiconductor structure further includes: after forming the trench and before forming the source / drain doped layer in the trench, etching a portion-thickness sacrificial layer along the lateral direction to form a sidewall trench in the trench sidewall; and filling the sidewall trench with inner sidewalls. After forming the source / drain doped layer and before removing the dummy gate structure, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer on the substrate of the dummy gate structure and the sidewall side to cover the source / drain doped layer.

14. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of isotropically etching the initial dielectric wall to form a dielectric wall, the bottom wall of the dielectric wall protrusion is recessed relative to the bottom wall of the channel layer, and the top wall of the dielectric wall protrusion is recessed relative to the top wall of the channel layer.

15. The method for forming a semiconductor structure as described in claim 11, characterized in that, The method for forming the semiconductor structure further includes: after isotropic etching of the initial dielectric wall, before forming the gate structure, rounding the corners of the channel layer exposed by the gate opening and the through-hole, so that the corners of the channel layer are arc-shaped.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The corner rounding treatment of the channel layer exposed by the gate opening and the through-hole includes: etching the surface of the channel layer exposed by the gate opening and the through-hole using an isotropic plasma etching process; or, annealing the surface of the channel layer exposed by the gate opening and the through-hole in a hydrogen atmosphere; or, oxidizing the surface of the channel layer exposed by the gate opening and the through-hole.

17. The method for forming a semiconductor structure as described in claim 11, characterized in that, After forming the dielectric wall and before forming the gate structure, the method for forming the semiconductor structure further includes forming a gate dielectric layer at the bottom and sidewalls of the gate opening, the top and sidewalls of the dielectric wall, and the exposed channel layer surface of the dielectric wall.

18. The method for forming a semiconductor structure as described in claim 11, characterized in that, The device unit area includes a first sub-device area and a second sub-device area arranged longitudinally; the first sub-device area is used to form a first type device, and the second sub-device area is used to form a second type device, wherein the second type device and the first type device have different channel conductivity types.

19. The method for forming a semiconductor structure as described in claim 11 or 18, characterized in that, Along the longitudinal direction, the gate structures located in adjacent sub-device regions are in contact with the top of the dielectric wall.

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