p-channel metal-oxide-semiconductor field-effect transistor based on InN / AlGaN / GaN heterostructure and its fabrication method

Abstract

This invention discloses a p-channel metal-oxide-semiconductor field-effect transistor based on an InN / AlGaN / GaN heterojunction and its fabrication method, mainly addressing the problems of low hole mobility and low two-dimensional hole gas concentration in existing p-channel MOSFET devices. From bottom to top, it comprises: a substrate layer (1), a GaN buffer layer (2), an AlGaN barrier layer (3), a p-type layer (5), and a SiO2 gate dielectric layer (6). The dielectric layer has a source (7) and a drain (8) at its left and right ends, respectively, and a gate groove is etched in the middle, with a gate electrode (9) located at the gate groove. The key feature is that an undoped InN channel layer (4) is added between the AlGaN barrier layer and the p-type layer to improve the two-dimensional hole gas concentration and hole mobility. Furthermore, the p-type layer uses InN material to enhance hole mobility. This invention improves the device's operating frequency and output power, and can be used in GaN-based power integrated circuits and complementary logic circuits.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, and specifically relates to a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET), which can be used to fabricate GaN-based power integrated circuits and complementary logic circuits. Technical Background

[0002] Compared to traditional silicon and gallium arsenide (GaAs) materials, gallium nitride (GaN) materials possess superior properties such as a wide bandgap, high electron drift velocity, high thermal conductivity, and high breakdown electric field, making them suitable for fabricating high-voltage, high-frequency, and high-power electronic devices. With the development of new energy vehicles, 5G communications, aerospace, and other fields, GaN-based power devices and power modules have been widely applied. However, in currently used GaN power modules, the peripheral drive circuits and logic units are still constructed from traditional silicon materials. This approach increases the size of the GaN power module and introduces parasitic inductance, significantly limiting the system's operating frequency and output power. The ideal solution is to fabricate the peripheral drive circuits and logic units using GaN materials, achieving monolithic integration of GaN power devices and GaN complementary logic circuits. In recent years, GaN-based complementary logic circuits have been extensively studied; however, current GaN complementary logic circuits have very low operating frequencies and output power, failing to meet the requirements of power integration. This is because the p-channel MOSFETs constituting these circuits have low channel mobility, high on-resistance, and low carrier concentration, severely limiting circuit performance.

[0003] Existing p-channel metal-oxide-semiconductor field-effect transistor structures based on GaN / AlGaN / GaN heterojunctions, such as Figure 1 As shown, from bottom to top, it includes: a Si substrate layer, a GaN buffer layer, an AlGaN barrier layer, a p-type GaN layer, and a gate dielectric layer. The gate dielectric layer has source and drain electrodes at its left and right ends, respectively, and a gate groove is etched in the middle, with the gate electrode located at the groove. This device has two main drawbacks: first, due to the use of GaN material as the p-type layer and conductive channel, the hole mobility is extremely low, severely limiting the device's operating speed; second, ionized impurity scattering and etching damage reduce the two-dimensional hole gas concentration and hole mobility, leading to a decrease in device output power. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of the prior art by proposing a p-channel metal-oxide-semiconductor field-effect transistor based on an InN / AlGaN / GaN heterojunction and its fabrication method, so as to effectively improve hole mobility and two-dimensional hole gas concentration, thereby increasing the device's operating frequency and output power.

[0005] The technical solution for achieving the objective of this invention is as follows:

[0006] 1. A p-channel metal-oxide-semiconductor field-effect transistor based on an InN / AlGaN / GaN heterojunction, comprising, from bottom to top: a substrate layer, a GaN buffer layer, an AlGaN barrier layer, a p-type layer, and a gate dielectric layer, wherein a source and a drain are respectively disposed at the left and right ends of the gate dielectric layer, and a gate groove is etched in the middle, with a gate electrode disposed at the gate groove, characterized in that:

[0007] The p-type layer is made of InN material to improve hole mobility;

[0008] The gate dielectric layer is made of SiO2 material to reduce gate leakage current;

[0009] An undoped InN channel layer is added between the AlGaN barrier layer and the p-type layer to improve the two-dimensional hole gas concentration and hole mobility.

[0010] Furthermore, the substrate layer uses <111> Si substrate with crystal orientation or c-plane sapphire substrate;

[0011] Furthermore, the InN channel layer has a thickness of 20-30 nm; the p-type InN layer has a thickness of 60-70 nm and a doping concentration of 2 × 10⁻⁶. 19 cm -3 ~4×10 19 cm -3 The SiO2 gate dielectric layer has a thickness of 5-10 nm.

[0012] Furthermore, the GaN buffer layer has a thickness of 4000-5000 nm; the AlGaN barrier layer has a thickness of 20-30 nm and an Al composition of 0.2-0.3; the source and drain electrodes each have a thickness of 25-40 nm; and the gate electrode has a thickness of 65-90 nm.

[0013] 2. A method for fabricating a p-channel metal-oxide-semiconductor field-effect transistor based on an InN / AlGaN / GaN heterojunction, characterized by comprising the following steps:

[0014] 1) Clean and dry the substrate;

[0015] 2) A GaN buffer layer with a thickness of 4000-5000 nm was grown on the dried substrate using MOCVD process;

[0016] 3) An AlGaN barrier layer with a thickness of 20-30 nm was grown on the GaN buffer layer using MOCVD process, with the Al composition adjusted in the range of 0.2-0.3.

[0017] 4) An InN channel layer with a thickness of 20-30 nm was grown on the AlGaN barrier layer using MOCVD process;

[0018] 5) A p-type InN layer with a thickness of 60-70 nm was grown on the InN channel layer using MOCVD process. The doping element was Mg, and the doping concentration was 2×10⁻⁶. 19 cm -3 ~4×10 19 cm -3 ;

[0019] 6) Use a low-power plasma etching process to etch a gate trench with a depth of 40-50 nm in the center of the p-type InN layer;

[0020] 7) Electron beam evaporation technology is used to evaporate a mixture of titanium, aluminum, nickel and gold on the left and right sides of the p-type InN layer, depositing source and drain electrodes with a thickness of 25-40 nm each;

[0021] 8) A SiO2 gate dielectric layer with a thickness of 5-10 nm was grown in the groove of the p-type InN layer using MOCVD process;

[0022] 9) Electron beam evaporation is used on the gate dielectric layer to evaporate a mixed metal of titanium, aluminum, nickel and gold, depositing a gate with a thickness of 70-100nm to complete the device fabrication.

[0023] Compared with the prior art, the present invention has the following advantages:

[0024] First, this invention uses InN material as the p-type layer and the channel layer. Since InN material has a high hole mobility, the operating frequency of the device can be improved.

[0025] Secondly, by using SiO2 material as the gate dielectric layer, this invention can reduce gate leakage current and improve device reliability.

[0026] Third, by inserting an undoped InN channel layer between the AlGaN barrier layer and the p-type layer, this invention can, on the one hand, enhance the polarization electric field of the device, increase the two-dimensional hole concentration, and improve the output power of the device; on the other hand, it can effectively reduce the influence of ionized impurity scattering and etching damage on the channel, accelerate the hole migration rate, and improve the device operating speed. Attached Figure Description

[0027] Figure 1 This is a diagram of the existing p-channel metal-oxide-semiconductor field-effect transistor structure of GaN / AlGaN / GaN heterojunction;

[0028] Figure 2 This is a structural diagram of the p-channel metal-oxide-semiconductor field-effect transistor based on the InN / AlGaN / GaN heterojunction of this invention;

[0029] Figure 3 This invention is made Figure 2 A schematic diagram of the p-channel metal-oxide-semiconductor field-effect transistor structure. Detailed Implementation

[0030] The present invention will be further described in detail below with reference to the accompanying drawings.

[0031] Reference Figure 2 The device structure of this invention includes: a substrate 1, a GaN buffer layer 2, an AlGaN barrier layer 3, an InN channel layer 4, a p-type InN layer 5, a gate dielectric layer 6, a source 7, a drain 8, and a gate 9. Wherein:

[0032] The substrate 1 adopts <111> Si substrate with crystal orientation or c-plane sapphire substrate;

[0033] The GaN buffer layer 2 is located on the substrate 1 and has a thickness of 4000-5000 nm.

[0034] The AlGaN barrier layer 3 is located on top of the GaN buffer layer 2, and its thickness is 20-30 nm. The Al composition is adjusted within the range of 0.2-0.3.

[0035] The InN channel layer 4, located above the AlGaN barrier layer 3, has a thickness of 20-30 nm and is used to improve the two-dimensional hole gas concentration and hole mobility.

[0036] The p-type InN layer 5 is located above the InN channel layer 4, with a thickness of 60-70 nm and a doping concentration of 2 × 10⁻⁶ nm. 19 cm -3 ~4×10 19 cm -3 The p-type InN layer 5 has a gate trench with a depth of 40-50nm etched in the middle, and a SiO2 gate dielectric layer 6 with a thickness of 5-10nm deposited on the trench; a gate 9 with a thickness of 70-100nm is provided on the gate dielectric layer.

[0037] The source electrode 7 and drain electrode 8 are located on the left and right sides of the p-type InN layer 5, respectively, and their thicknesses are both 25-40nm.

[0038] Reference Figure 3 The fabrication method of p-channel metal-oxide-semiconductor field-effect transistors based on InN / AlGaN / GaN heterojunctions is presented in the following three embodiments.

[0039] Example 1, the substrate is fabricated as follows <111> The Si crystal orientation has a buffer layer thickness of 4000 nm, a barrier layer thickness of 20 nm, an Al composition of 0.2, a channel layer thickness of 20 nm, a p-type layer thickness of 60 nm, and a doping concentration of 2 × 10⁻⁶. 19 cm -3A p-channel metal-oxide-semiconductor field-effect transistor with a gate dielectric layer thickness of 5nm, source and drain thicknesses of 25nm, and gate thickness of 70nm.

[0040] Step 1: Pretreatment of the Si substrate by cleaning and drying.

[0041] 1.1) Place the Si substrate 1 in an acetone solution and perform ultrasonic cleaning for 5 min;

[0042] 1.2) Immerse the cleaned substrate in an ethanol solution for 5 minutes;

[0043] 1.3) Remove the soaked substrate and place it in a drying oven for drying at 100°C.

[0044] Step two, grow a GaN buffer layer using MOCVD process, such as... Figure 3 (a).

[0045] The pretreated Si substrate was placed in the MOCVD reaction chamber, the temperature of the reaction chamber was adjusted to 950℃, and ammonia gas with a flow rate of 2500 sccm and a gallium source with a flow rate of 150 sccm were introduced at the same time. Under the condition of maintaining a pressure of 20 Torr, a GaN buffer layer 2 with a thickness of 4000 nm was grown on the substrate.

[0046] Step 3: Grow an AlGaN barrier layer using MOCVD technology, such as... Figure 3 (b)

[0047] The temperature of the MOCVD reaction chamber was adjusted to 1100℃, and ammonia gas with a flow rate of 2000 sccm, a gallium source with a flow rate of 250 sccm, and an aluminum source with a flow rate of 100 sccm were introduced simultaneously. Under the condition of maintaining a pressure of 20 Torr, an AlGaN barrier layer 3 with a thickness of 20 nm and an Al composition of 0.2 was grown on the GaN buffer layer.

[0048] Step four: Grow the InN channel layer using MOCVD process, such as... Figure 3 (c)

[0049] The temperature of the MOCVD reaction chamber was adjusted to 600℃, and ammonia gas with a flow rate of 1800 sccm and an indium source with a flow rate of 100 sccm were introduced simultaneously. Under the condition of maintaining a pressure of 15 Torr, an InN channel layer with a thickness of 20 nm was grown on the AlGaN barrier layer.

[0050] Step 5: Grow a p-type InN layer using MOCVD process, such as... Figure 3 (d)

[0051] The MOCVD reaction chamber temperature was adjusted to 600℃, and ammonia gas at a flow rate of 1800 sccm, a magnesium source at a flow rate of 100 sccm, and an indium source at a flow rate of 100 sccm were simultaneously introduced. Under a pressure of 15 Torr, a 60 nm thick layer with a doping concentration of 2 × 10⁻⁶ was grown on the InN channel layer. 19 cm -3 5. p-type InN layer.

[0052] Step six: Etch the gate grooves using a low-power plasma etching process, such as... Figure 3 (e).

[0053] The etching power of the equipment was adjusted to 30W, and a gate trench with a depth of 40nm was etched in the center of the p-type InN layer using Cl2 and BCl3.

[0054] Step 7, deposit the source and drain electrodes, as follows: Figure 3 (f).

[0055] Electron beam evaporation technology was used to evaporate a mixture of titanium, aluminum, nickel and gold metals on the left and right sides of a p-type InN layer, depositing source electrode 7 and drain electrode 8, each with a thickness of 25 nm.

[0056] Step 8: Grow a SiO2 gate dielectric layer using MOCVD process, such as... Figure 3 (g)

[0057] The temperature of the MOCVD reaction chamber was adjusted to 900℃, and silane with a flow rate of 1000 sccm and oxygen with a flow rate of 160 sccm were introduced simultaneously. Under the condition of maintaining a pressure of 20 Torr, a SiO2 gate dielectric layer 6 with a thickness of 5 nm was grown on the groove of the p-type InN layer.

[0058] Step nine, deposit the gate, as follows Figure 3 (h).

[0059] Electron beam evaporation technology was used to evaporate a mixture of titanium, aluminum, nickel and gold metals on the gate dielectric layer, depositing a gate 9 with a thickness of 70 nm to complete the device fabrication.

[0060] Example 2: The substrate was c-plane sapphire. The buffer layer thickness was 4500 nm, the barrier layer thickness was 25 nm, the Al composition was 0.25, the channel layer thickness was 25 nm, and the p-type layer thickness was 65 nm with a doping concentration of 3 × 10⁻⁶. 19 cm -3 A p-channel metal-oxide-semiconductor field-effect transistor with a gate dielectric layer thickness of 7nm, source and drain thicknesses of 35nm, and gate thickness of 87nm.

[0061] Step A: Clean and dry the sapphire substrate.

[0062] A1) Place the sapphire substrate 1 in an acetone solution and perform ultrasonic cleaning for 15 minutes;

[0063] B1) Immerse the cleaned substrate in an ethanol solution for 8 minutes;

[0064] C1) Remove the soaked substrate and place it in a drying oven for drying at 110°C.

[0065] Step B involves growing a GaN buffer layer using MOCVD technology, such as... Figure 3 (a).

[0066] The pretreated sapphire substrate was placed in the MOCVD reaction chamber, and a GaN buffer layer 2 with a thickness of 4500 nm was grown on the substrate.

[0067] The growth process conditions are as follows: the reaction chamber temperature is 1050℃, the reaction chamber pressure is 40 Torr, and the gas introduced at the same time is ammonia gas with a flow rate of 2700 sccm and gallium source with a flow rate of 170 sccm.

[0068] Step C, an AlGaN barrier layer is grown using MOCVD technology, such as... Figure 3 (b)

[0069] An AlGaN barrier layer 3 with a thickness of 25 nm and an Al composition of 0.25 was grown on the GaN buffer layer.

[0070] The growth process conditions are as follows: the MOCVD reaction chamber temperature is 1120℃, the reaction chamber pressure is 40 Torr, and the gases introduced are ammonia gas with a flow rate of 2100 sccm, gallium source gas with a flow rate of 260 sccm, and aluminum source gas with a flow rate of 130 sccm.

[0071] Step D: Growing the InN channel layer using MOCVD process, such as... Figure 3 (c)

[0072] An InN channel layer with a thickness of 25 nm was grown on the AlGaN barrier layer.

[0073] The growth process conditions are as follows: the MOCVD reaction chamber temperature is 700℃, the reaction chamber pressure is 30 Torr, and the gases introduced are ammonia gas with a flow rate of 1900 sccm and indium source with a flow rate of 130 sccm.

[0074] Step E: Growing a p-type InN layer using MOCVD process, such as... Figure 3 (d)

[0075] A 65 nm thick layer with a doping concentration of 3 × 10⁻⁶ was grown on the InN channel layer. 19 cm -35. p-type InN layer.

[0076] The growth process conditions are as follows: the MOCVD reaction chamber temperature is 700℃, the reaction chamber pressure is 30 Torr, and the gases introduced are ammonia gas with a flow rate of 1900 sccm, magnesium source with a flow rate of 200 sccm, and indium source with a flow rate of 130 sccm.

[0077] Step F involves etching the gate grooves using a low-power plasma etching process, such as... Figure 3 (e).

[0078] The etching power of the equipment was adjusted to 40W, and a gate trench with a depth of 45nm was etched in the center of the p-type InN layer using Cl2 and BCl3.

[0079] Step G, deposit the source and drain, as follows Figure 3 (f).

[0080] Electron beam evaporation technology was used to evaporate a mixture of titanium, aluminum, nickel and gold metals on the left and right sides of a p-type InN layer, depositing source 7 and drain 8, each with a thickness of 35 nm.

[0081] Step H involves growing a SiO2 gate dielectric layer using MOCVD technology, such as... Figure 3 (g)

[0082] A 7 nm thick SiO2 gate dielectric layer 6 is grown on the groove of the p-type InN layer.

[0083] The growth process conditions are as follows: the MOCVD reaction chamber temperature is 1050℃, the reaction chamber pressure is 40 Torr, and the gases introduced are silane with a flow rate of 1050 sccm and oxygen with a flow rate of 190 sccm.

[0084] Step I, deposit the gate, as follows Figure 3 (h).

[0085] Electron beam evaporation technology was used to evaporate a mixed metal of titanium, aluminum, nickel and gold on the gate dielectric layer to deposit a gate 9 with a thickness of 87nm, thus completing the device fabrication.

[0086] Example 3, the substrate is fabricated as <111> The Si crystal orientation has a buffer layer thickness of 5000 nm, a barrier layer thickness of 30 nm, an Al composition of 0.3, a channel layer thickness of 30 nm, a p-type layer thickness of 70 nm, and a doping concentration of 4 × 10⁻⁶. 19 cm -3 A p-channel metal-oxide-semiconductor field-effect transistor with a gate dielectric layer thickness of 10 nm, source and drain thicknesses of 40 nm, and gate thickness of 100 nm.

[0087] Step 1: Pre-treat the Si substrate.

[0088] Si substrate 1 was ultrasonically cleaned in acetone solution for 20 min; the cleaned substrate was then immersed in ethanol solution for 10 min; the immersed substrate was then removed and placed in a drying oven for drying at 120°C.

[0089] Step 2: Grow a GaN buffer layer using MOCVD technology, such as... Figure 3 (a).

[0090] The pretreated Si substrate was placed in the MOCVD reaction chamber, and the reaction chamber temperature was maintained at 1100℃ and the pressure at 60 Torr. At the same time, ammonia gas with a flow rate of 3000 sccm and a gallium source with a flow rate of 180 sccm were introduced to grow a GaN buffer layer 2 with a thickness of 5000 nm on the substrate.

[0091] Step 3: Grow an AlGaN barrier layer using MOCVD technology, such as... Figure 3 (b)

[0092] The MOCVD reaction chamber was kept at a temperature of 1150℃ and a pressure of 60 Torr. Ammonia gas with a flow rate of 2200 sccm, a gallium source with a flow rate of 270 sccm, and an aluminum source with a flow rate of 150 sccm were introduced to grow an AlGaN barrier layer 3 with a thickness of 30 nm and an Al composition of 0.3 on the GaN buffer layer.

[0093] Step 4: Grow the InN channel layer using MOCVD process, such as... Figure 3 (c)

[0094] The MOCVD reaction chamber was kept at a temperature of 800℃ and a pressure of 40 Torr. Ammonia gas with a flow rate of 2000 sccm and an indium source with a flow rate of 150 sccm were introduced simultaneously to grow an InN channel layer with a thickness of 30 nm on the AlGaN barrier layer.

[0095] Step 5: Grow a p-type InN layer using MOCVD process, such as... Figure 3 (d)

[0096] The MOCVD reaction chamber was maintained at 800℃ and 40 Torr, while ammonia gas (flow rate 2000 sccm), a magnesium source (flow rate 300 sccm), and an indium source (flow rate 150 sccm) were simultaneously introduced to grow a 70 nm thick layer with a doping concentration of 4 × 10⁻⁶ on the InN channel layer. 19 cm -3 5. p-type InN layer.

[0097] Step 6: Etch the gate grooves using a low-power plasma etching process, such as... Figure 3 (e).

[0098] The etching power of the equipment was adjusted to 50W, and a gate trench with a depth of 50nm was etched in the center of the p-type InN layer 5 using Cl2 and BCl3.

[0099] Step 7, deposit the source and drain electrodes, as follows: Figure 3 (f).

[0100] Electron beam evaporation technology was used to evaporate a mixture of titanium, aluminum, nickel and gold metals on the left and right sides of a p-type InN layer, depositing source 7 and drain 8, each with a thickness of 40 nm.

[0101] Step 8: Grow a SiO2 gate dielectric layer using MOCVD process, such as... Figure 3 (g)

[0102] The MOCVD reaction chamber was kept at a temperature of 1200℃ and a pressure of 60 Torr. Simultaneously, silane with a flow rate of 1100 sccm and oxygen with a flow rate of 210 sccm were introduced to grow a SiO2 gate dielectric layer 6 with a thickness of 10 nm on the groove of the p-type InN layer.

[0103] Step 9, deposit the gate, as follows Figure 3 (h).

[0104] Electron beam evaporation technology was used to evaporate a mixture of titanium, aluminum, nickel and gold metals on the gate dielectric layer, depositing a gate 9 with a thickness of 100 nm to complete the device fabrication.

[0105] The above descriptions are merely three specific examples of the present invention and do not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and detail without departing from the principles and structure of the present invention. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A p-channel metal-oxide-semiconductor field-effect transistor based on an InN / AlGaN / GaN heterojunction, comprising, from bottom to top: The structure comprises a substrate layer (1), a GaN buffer layer (2), an AlGaN barrier layer (3), a p-type layer (5), and a gate dielectric layer (6). The gate dielectric layer has a source (7) and a drain (8) at its left and right ends, respectively, and a gate groove is etched in the middle. A gate electrode (9) is located in the groove. The structure is characterized by: The p-type layer (5) is made of InN material to improve hole mobility; The gate dielectric layer (6) is made of SiO2 material to reduce gate leakage current; An undoped InN channel layer (4) is added between the AlGaN barrier layer (3) and the p-type layer (5) to improve the two-dimensional hole gas concentration and hole mobility.

2. The field-effect transistor according to claim 1, characterized in that: The substrate layer (1) uses <111> Si substrate with crystal orientation or c-plane sapphire substrate.

3. The field-effect transistor according to claim 1, characterized in that: The InN channel layer (4) has a thickness of 20-30 nm; The p-type InN layer (5) has a thickness of 60-70 nm and a doping concentration of 2 × 10⁻⁶. 19 cm -3 -4×10 19 cm -3 ; The SiO2 gate dielectric layer (6) has a thickness of 5-10 nm.

4. The field-effect transistor according to claim 1, characterized in that: The GaN buffer layer (2) has a thickness of 4000-5000 nm; The AlGaN barrier layer (3) has a thickness of 20-30 nm and an Al composition of 0.2-0.

3. The source (7) and drain (8) mentioned above both have a thickness of 25-40 nm; The gate (9) has a thickness of 70-100 nm.

5. A method for fabricating a p-channel metal-oxide-semiconductor field-effect transistor based on an InN / AlGaN / GaN heterojunction, characterized in that, Includes the following steps: 1) Clean and dry the substrate (1); 2) A GaN buffer layer with a thickness of 4000-5000 nm was grown on the dried substrate using MOCVD process (2). 3) An AlGaN barrier layer (3) with a thickness of 20-30 nm is grown on the GaN buffer layer (2) using MOCVD process, and the Al composition is adjusted in the range of 0.2-0.3; 4) An InN channel layer (4) with a thickness of 20-30 nm was grown on the AlGaN barrier layer (3) using MOCVD process. 5) A p-type InN layer (5) with a thickness of 60-70 nm was grown on the InN channel layer (4) using MOCVD process. The doping element was Mg, and the doping concentration was 2×10⁻⁶. 19 cm -3 ~ 4×10 19 cm -3 ; 6) Using a low-power plasma etching process, a gate trench with a depth of 40-50 nm is etched in the center of the p-type InN layer (5); 7) Electron beam evaporation technology is used to evaporate a mixture of titanium, aluminum, nickel and gold on the left and right sides of the p-type InN layer (5) to deposit source (7) and drain (8) with a thickness of 25-40nm. 8) A SiO2 gate dielectric layer (6) with a thickness of 5-10 nm was grown on the groove of the p-type InN layer (5) using MOCVD process. 9) Electron beam evaporation is used to evaporate a mixture of titanium, aluminum, nickel and gold metals on the gate dielectric layer to deposit a gate with a thickness of 70-100nm (9) to complete the device fabrication.

6. The method according to claim 5, characterized in that, Step 1) involves cleaning and drying the substrate using a standard cleaning process, as follows: 1a) Place the substrate in an acetone solution and perform ultrasonic cleaning for 5-20 minutes; 1b) Immerse the cleaned substrate in an ethanol solution for 5-10 minutes; 1c) Remove the soaked substrate and place it in a drying oven for drying at 100-120°C.

7. The method according to claim 5, characterized in that, Step 2) uses the MOCVD process, with the following conditions and parameters set for the reaction chamber: The reaction chamber temperature is 950-1100℃. Maintain the reaction chamber pressure at 20-60 Torr. Ammonia gas with a flow rate of 2500-3000 sccm and gallium source gas with a flow rate of 150-180 sccm are introduced into the reaction chamber.

8. The method according to claim 5, characterized in that, Step 3) uses the MOCVD process, with the following conditions and parameters set for the reaction chamber: The reaction chamber temperature is 1100-1150℃. Maintain the reaction chamber pressure at 20-60 Torr. Ammonia gas with a flow rate of 2000-2200 sccm, gallium source gas with a flow rate of 250-270 sccm, and aluminum source gas with a flow rate of 100-150 sccm are introduced into the reaction chamber.

9. The method according to claim 5, characterized in that, Step 4) uses the MOCVD process, with the following conditions and parameters set for the reaction chamber: The reaction chamber temperature is 600-800℃. Maintain the reaction chamber pressure at 15-40 Torr. Ammonia gas with a flow rate of 1800-2000 sccm and indium source gas with a flow rate of 100-150 sccm are introduced into the reaction chamber.

10. The method according to claim 5, characterized in that, Step 5) uses the MOCVD process, with the following conditions and parameters set for the reaction chamber: The reaction chamber temperature is 600-800℃. Maintain the reaction chamber pressure at 15-40 Torr. Ammonia gas with a flow rate of 1800-2000 sccm, magnesium source gas with a flow rate of 100-300 sccm, and indium source gas with a flow rate of 100-150 sccm are introduced into the reaction chamber.

11. The method according to claim 5, characterized in that, Step 6) employs a low-power plasma etching process, which involves setting the following equipment parameters: The etching gases are Cl2 and BCl3. The etching power is 30-50W.

12. The method according to claim 5, characterized in that, Step 8) uses the MOCVD process, with the following conditions set for the reaction chamber: The reaction chamber temperature is 900-1200℃. Maintain the reaction chamber pressure at 20-60 Torr. Two gases, silane at a flow rate of 1000-1100 sccm and oxygen at a flow rate of 160-210 sccm, are simultaneously introduced into the reaction chamber.

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