Thin film transistor and manufacturing method thereof, display panel

Abstract

The application discloses a thin film transistor and a manufacturing method thereof and a display panel. The thin film transistor comprises a heat preservation layer, the heat preservation layer comprises a groove; a crystalline active pattern, at least part of the crystalline active pattern is located in the groove; a source-drain electrode, the source-drain electrode comprises a source electrode and a drain electrode which are arranged at intervals, and the source electrode and the drain electrode are connected with the crystalline active pattern; and a gate electrode which is arranged corresponding to the crystalline active pattern.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a thin film transistor, a manufacturing method thereof and a display panel. BACKGROUND

[0002] At present, one of the user's requirements for display devices is high-frequency display fluency, which requires the thin film transistor to have high mobility. However, the mobility of the traditional thin film transistor cannot meet the requirement of high-frequency display fluency.

[0003] Therefore, it is necessary to provide a technical solution to improve the mobility of the thin film transistor. SUMMARY

[0004] The present application aims to provide a thin film transistor, a manufacturing method thereof and a display panel, which are beneficial to improve the mobility of the thin film transistor.

[0005] To achieve the above-mentioned purpose, the technical solution is as follows:

[0006] A thin film transistor, comprising:

[0007] A heat preservation layer, comprising a groove;

[0008] A crystalline active pattern, at least part of which is located in the groove;

[0009] A source-drain electrode, comprising a source and a drain arranged at intervals, both of which are connected with the crystalline active pattern;

[0010] A gate electrode, which is arranged corresponding to the crystalline active pattern.

[0011] In some embodiments of the thin film transistor, the opening size of the groove is less than or equal to 200 nanometers in the direction perpendicular to the thickness of the heat preservation layer.

[0012] In some embodiments of the thin film transistor, the crystalline active pattern is a single crystal grain.

[0013] In some embodiments of the thin film transistor, the opening size of the groove is greater than 200 nanometers in the direction perpendicular to the thickness of the heat preservation layer.

[0014] In some embodiments of the thin film transistor, the crystalline active pattern is located in the groove, and the crystalline active pattern comprises at least two crystal lattices, there is a grain boundary between two adjacent crystal lattices, and the extension direction of the grain boundary is the same as the extension direction of the crystalline active pattern.

[0015] In some embodiments of the thin film transistor, the depth of the groove is less than or equal to the thickness of the heat preservation layer.

[0016] In some embodiments of the thin film transistor, the thickness of the heat preservation layer is greater than or equal to 3000 angstroms and less than or equal to 10000 angstroms.

[0017] A method for manufacturing a thin film transistor, the method comprising the steps of:

[0018] forming a heat preservation layer, the heat preservation layer comprising a groove;

[0019] forming a crystalline active pattern, at least a portion of the crystalline active pattern being located in the groove;

[0020] forming a source-drain electrode, the source-drain electrode comprising a source and a drain arranged in a spaced manner, the source and the drain both being connected with the crystalline active pattern; and

[0021] forming a gate corresponding to the crystalline active pattern.

[0022] In some embodiments of the method for manufacturing a thin film transistor, the step of forming a crystalline active pattern comprises the steps of:

[0023] forming an amorphous silicon semiconductor layer in at least the groove;

[0024] annealing the amorphous silicon semiconductor layer by a quasi-molecular laser annealing process to obtain a crystalline silicon semiconductor layer;

[0025] performing a patterning process on the crystalline silicon semiconductor layer to obtain the crystalline active pattern.

[0026] A display panel, the display panel comprising the thin film transistor.

[0027] Beneficial effects: The present application provides a thin film transistor and a manufacturing method thereof, and a display panel. At least a portion of the crystalline active pattern is formed in the groove of the heat preservation layer. The heat preservation layer reduces the cooling rate during the crystallization process of forming the crystalline active pattern, so as to increase the grain size in the crystalline active pattern and improve the mobility of the thin film transistor. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 FIG. 1 is a schematic diagram of a thin film transistor according to an embodiment of the present application;

[0029] Figure 2 FIG. 2 is a plan view of the thin film transistor shown in FIG. 1; Figure 1

[0030] Figure 3 FIG. 3 is a schematic diagram of a thin film transistor according to another embodiment of the present application;

[0031] Figure 4 FIG. 4 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present application; ​

[0032] Figures 5A to 5G A process flow for manufacturing a thin film transistor of an embodiment of the present application;

[0033] Figure 6 A plan view of a display panel of an embodiment of the present application. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0035] Please refer to Figure 1 which is a schematic view of a thin film transistor substrate of an embodiment of the present application. The thin film transistor 100 includes a substrate 110, a heat preservation layer 120, a crystalline active pattern 130, a gate insulating layer 140, a source-drain electrode 150, and a gate 160.

[0036] The substrate 110 is a glass substrate, but is not limited thereto, and the substrate 110 can also be a flexible substrate.

[0037] The heat preservation layer 120 plays a heat preservation role to reduce the temperature drop rate. The heat preservation layer 120 is formed on the substrate 110. The preparation material of the heat preservation layer 120 includes but is not limited to silicon oxide. The thickness of the heat preservation layer 120 is greater than or equal to 3000 angstroms and less than or equal to 10000 angstroms, for example, 4000 angstroms, 5000 angstroms, 6000 angstroms, 7000 angstroms, 8000 angstroms, and 10000 angstroms.

[0038] The heat preservation layer 120 includes at least one groove 120a. The number of the grooves 120a can be one, two, or more than two. The size of one groove 120a can be related to the size of one thin film transistor, so that one thin film transistor is arranged in the area where one groove 120a is located. The size of one groove 120a can also be related to the size of a plurality of thin film transistors, so that a plurality of thin film transistors are arranged in the area where one groove 120a is located.

[0039] The shape of one groove 120a can be circular, square, triangular, rectangular, or other patterns. Specifically, the shape of one groove 120a is circular.

[0040] The depth of the recess 120a is less than or equal to the thickness of the thermal insulation layer 120. Specifically, the depth of the recess 120a is equal to the thickness of the thermal insulation layer 120, that is, the recess 120a penetrates the thermal insulation layer 120 in the thickness direction of the thermal insulation layer 120. It can be understood that the depth of the recess 120a can also be less than the thickness of the thermal insulation layer 120.

[0041] In the direction perpendicular to the thickness of the thermal insulation layer 120, the opening size d of the recess 120a is greater than 200 nanometers. For example, in the direction perpendicular to the thickness of the thermal insulation layer 120, the opening size d of the recess 120a can be 500 nanometers, 800 nanometers, 1000 nanometers, 1500 nanometers, 3000 nanometers, 1 micrometer, 2 micrometers, 4 micrometers, or 6 micrometers.

[0042] Please refer to Figure 1 and Figure 2 , Figure 2 for Figure 1 the planar schematic diagram of the thin film transistor. The crystalline active pattern 130 is located in the recess 120a. The crystalline active pattern 130 is a polysilicon active pattern, but is not limited thereto, and the crystalline active pattern 130 can also be a crystalline metal oxide semiconductor, and the crystalline active pattern 130 can also be a single crystal silicon active pattern.

[0043] It should be noted that when the crystalline active pattern 130 is a polysilicon active pattern or a single crystal silicon active pattern, during the crystallization process of forming the crystalline active pattern 130, it is necessary to use laser to perform annealing treatment on amorphous silicon, and the temperature of the amorphous silicon is raised and melted. Due to the heat preservation effect of the thermal insulation layer, when the amorphous silicon located in the recess 120a is subjected to laser annealing treatment, the cooling rate of the melted amorphous silicon is slow, and the slow cooling rate is conducive to increasing the size of the crystal lattice in the polysilicon active pattern or the single crystal silicon active pattern during the conversion of the amorphous silicon into the polysilicon active pattern or the single crystal silicon active pattern. Similarly, when the crystalline active pattern 130 is a metal oxide semiconductor, due to the heat preservation effect of the thermal insulation layer 120 during the annealing crystallization process of the metal oxide semiconductor, it is also conducive to increasing the size of the crystal lattice in the crystalline active pattern 130.

[0044] Therefore, the thin film transistor of the embodiment of the present application is formed by at least part of the crystalline active pattern in the recess of the thermal insulation layer, the thermal insulation layer reduces the cooling rate in the crystallization process of forming the crystalline active pattern, so as to increase the grain size in the crystalline active pattern, improve the mobility of the crystalline active pattern, and thus make the thin film transistor suitable for high mobility.

[0045] As shown in Figure 2 , the crystalline active pattern 130 is in the shape of a semicircular ring, but is not limited thereto, and the crystalline active pattern 130 can also be in the shape of a circular arc, for example, the crystalline active pattern 130 can also be in the shape of a quarter circular ring; the crystalline active pattern 130 can also be in the shape of a rectangle.

[0046] The crystalline active pattern 130 includes at least two lattices 1301, and a first grain boundary 130a between two adjacent lattices 1301, the extension direction of the first grain boundary 130a is the same as the extension direction of the crystalline active pattern 130, that is, the extension direction of the first grain boundary 130a is the same as the extension direction of the arc-shaped edge of the semi-circular ring-shaped crystalline active pattern 130.

[0047] It can be understood that when the crystalline active pattern 130 is rectangular, the extension direction of the first grain boundary 130a is the same as the length direction of the crystalline active pattern 130.

[0048] In the prior art, the active pattern includes multiple grain boundaries and the multiple grain boundaries are irregularly distributed, which leads to a low mobility of the conventional thin film transistor. In the embodiment of the present application, the grain boundaries of the active pattern are the same as the extension direction of the crystalline active pattern, the distribution of the grain boundaries is more regular, the extension direction of the grain boundaries of the active pattern is the same as the transmission direction of the carriers, the grain boundaries and grain boundary defects in the carrier transmission process are less, and the carriers can be transmitted faster in the active pattern, thereby further improving the mobility of the thin film transistor including the crystalline active pattern of the present application.

[0049] The crystalline active pattern 130 includes a channel 1302 and two contact portions 1303, and the extension direction of the channel 1302 of the crystalline active pattern 130 is the same as the extension direction of the first grain boundary 130a. The two opposite contact portions 1303 of the semi-circular ring-shaped crystalline active pattern 130 are formed by a heavy doping process, and the two contact portions 1303 are located at opposite ends of the channel 1302. It can be understood that the semi-circular ring-shaped crystalline active pattern 130 can also be subjected to a light doping process to form a transition portion between each contact portion 1303 and the channel 1302.

[0050] The gate insulating layer 140 covers the crystalline active pattern 130 and the substrate 110. The gate insulating layer 140 includes a first contact hole 140a and a second contact hole 140b, and the first contact hole 140a and the second contact hole 140b are both arranged corresponding to the crystalline active pattern 130. The thickness of the gate insulating layer 140 is greater than or equal to 1000 angstroms and less than or equal to 3000 angstroms. The preparation material of the gate insulating layer 140 includes but is not limited to at least one of silicon nitride or silicon oxide.

[0051] The source-drain electrode 150 is located on the gate insulating layer 140. The source-drain electrode 150 includes a source electrode 1501 and a drain electrode 1502. The source electrode 1501 is arranged corresponding to the first contact hole 140a and connected with one contact part 1303 of the crystalline active pattern 130 through the first contact hole 140a. The drain electrode 1502 is arranged corresponding to the second contact hole 140b and connected with another contact part 1303 of the crystalline active pattern 130 through the second contact hole 140b. The material of the source-drain electrode 150 includes at least one of molybdenum, aluminum, titanium, copper and silver.

[0052] The gate electrode 160 is located on the gate insulating layer 140. The gate electrode 160 is arranged corresponding to the crystalline active pattern 130. The material of the gate electrode 160 includes at least one of molybdenum, aluminum, titanium, copper and silver.

[0053] In the embodiment, the heat preservation layer 120, the crystalline active pattern 130, the gate insulating layer 140, the source-drain electrode 150 and the gate electrode 160 constitute a thin film transistor. The crystalline active pattern 130 is arranged in the groove 120a of the heat preservation layer 120, which increases the lattice size of the crystalline active pattern 130 and is beneficial to improve the mobility of the thin film transistor. The extension direction of the grain boundary of the crystalline active pattern 130 is the same as the extension direction of the crystalline active pattern 130, which improves the regularity of the grain boundary and further improves the mobility of the thin film transistor, so that the thin film transistor can be used for high-frequency display.

[0054] Please refer to Figure 3 which is a schematic diagram of another embodiment of the thin film transistor. Figure 3 The thin film transistor shown in Figure 1 is basically similar to the thin film transistor shown in Figure 3 , and the same parts will not be described again, Figure 1 The difference between the thin film transistor 100 shown in and the thin film transistor 100 shown in comprises that, along the direction perpendicular to the thickness of the heat preservation layer 120, the opening size d of the groove 120a is less than or equal to 200 nanometers. A part of the crystalline active pattern 130 is located in the groove 120a, and another part of the crystalline active pattern 130 is located on the heat preservation layer 120. In addition, the crystalline active pattern 130 is a single crystal grain, in other words, the crystalline active pattern 130 is a single crystal grain without grain boundary.

[0055] For example, the opening size of the groove 120a can be 180 nanometers, 150 nanometers, 120 nanometers, 100 nanometers, 80 nanometers, 60 nanometers, 40 nanometers or 20 nanometers.

[0056] The opening size d of the groove 120a in the direction perpendicular to the thickness of the heat insulation layer 120 is less than or equal to 200 nm, so that the size of the groove 120a is small, the heat insulation effect of the heat insulation layer 120 is matched, the crystalline active pattern obtained through the crystallization and patterning process is more likely to be a single crystal grain, and the mobility of the thin film transistor is greatly improved.

[0057] The difference of the thin film transistor of the present application also includes that the interlayer insulation layer 170 is arranged between the gate 160 and the source 1501 and the drain 1502, and the interlayer insulation layer 170 is located on the side of the gate insulation layer 140 away from the substrate 110.

[0058] At least part of the crystalline active pattern of the thin film transistor of the embodiment of the present application is formed in the groove of the heat insulation layer with an opening size less than or equal to 200 nm, which is beneficial to form a single crystal grain in the crystalline active pattern, greatly improves the mobility of the thin film transistor, and ensures that the thin film transistor is used for high-frequency display.

[0059] Please refer to Figure 4 which is a flowchart of manufacturing the thin film transistor of an embodiment of the present application. The process of manufacturing the thin film transistor includes the following steps:

[0060] S100: forming a heat insulation layer, the heat insulation layer including a groove.

[0061] Specifically, a substrate 110 is provided, a heat insulation layer 120 is formed on the substrate 110 by chemical vapor deposition, and the heat insulation layer 120 is patterned by photolithography and etching process, at least one groove 120a is formed on the heat insulation layer 120, and the opening size d of each groove 120a in the direction perpendicular to the thickness of the heat insulation layer 120 is greater than 200 nm, as shown in Figure 5A The preparation material of the heat insulation layer 120 includes but is not limited to silicon oxide, and the thickness of the heat insulation layer 120 is greater than or equal to 3000 angstroms and less than or equal to 10000 angstroms.

[0062] As shown in Figure 5B , the shape of the groove 120a is circular, but is not limited thereto, and the shape of the groove 120a can also be rectangular, triangular or other patterns. The number of grooves 120a can be one, two or more.

[0063] S200: forming a crystalline active pattern, at least part of the crystalline active pattern being located in the groove.

[0064] Specifically, a full-surface amorphous silicon semiconductor layer is formed on the groove 120a and the surface of the heat insulation layer 120 away from the substrate 110 by chemical vapor deposition, and the amorphous silicon semiconductor layer is annealed by a quasi-molecular laser annealing process to obtain a crystalline silicon semiconductor layer 180, as shown in Figure 5C Figure 5D ​As shown, under the heat preservation effect of excimer laser annealing and heat preservation layer 120, the crystalline silicon semiconductor layer 180 in the groove 120a includes a plurality of second grain boundaries 180a arranged radially along the circular groove 120a. The spacing between two adjacent second grain boundaries 180a is smaller along the position away from the center of the circular groove 120a.

[0065] Next, as Figure 5E and Figure 5F As shown, the crystalline silicon semiconductor layer 180 in the groove 120a is patterned using photolithography and etching processes, and then a doping process is performed to obtain a semi-circular active crystalline pattern 130 located in the groove 120a. The extension direction of the active crystalline pattern 130 is the same as the extension direction of the second grain boundary 180a. The active crystalline pattern 130 includes at least two lattices 1301, and there is a first grain boundary 130a between two adjacent lattices 1301. The first grain boundary 130a is a part of the second grain boundary 180a. The extension direction of the first grain boundary 130a is the same as the extension direction of the active crystalline pattern 130, that is, the extension direction of the first grain boundary 130a is the same as the extension direction of the arc-shaped edge of the semi-circular active crystalline pattern 130.

[0066] The active crystal pattern 130 includes a channel 1302 and two contact portions 1303. The extension direction of the channel 1302 of the active crystal pattern 130 is the same as the extension direction of the first grain boundary 130a. The two opposing contact portions 1303 of the semi-circular active crystal pattern 130 are formed by a heavy doping process, and the two contact portions 1303 are located at opposite ends of the channel 1302. It is understood that the semi-circular active crystal pattern 130 can also be lightly doped to form a transition portion between each contact portion 1303 and the channel 1302.

[0067] It should be noted that under excimer laser irradiation, the amorphous silicon semiconductor layer becomes molten. The molten amorphous silicon at the center of the circular groove 120a dissipates heat relatively slowly and has a high temperature, while the molten amorphous silicon near the sidewalls of the groove 120a dissipates heat relatively quickly and has a low temperature. The molten amorphous silicon in the groove 120a has a decreasing temperature gradient along the radial direction of the circular groove 120a. The molten amorphous silicon expands due to heat and exerts a force on the insulation layer 120. The compressive force between the groove 120a and the molten amorphous silicon pushes in the opposite direction towards the center of the groove 120a. Under the combined action of the expansion force and the reverse force, a layer is formed as shown in the figure. Figure 5D The groove 120a shown has a plurality of crystalline silicon semiconductor layers 180 with second grain boundaries 180a, making the grain boundaries of the crystalline silicon semiconductor layers 180 in the groove 120a controllable.

[0068] In addition, when the crystalline silicon semiconductor layer 180 in the groove 120a is patterned by using a mask, the extending direction of the crystalline active pattern 130 is the same as the extending direction of the second crystal boundary 180a, so that the crystalline active pattern 130 with the crystal boundary extending in a specific direction can be obtained, and the crystal boundary in the channel 1302 of the crystalline active pattern 130 is reduced, and the mobility of the thin film transistor including the crystalline active pattern 130 is improved.

[0069] S300: forming a source-drain electrode and a gate electrode, the source-drain electrode including a source electrode and a drain electrode arranged in a spaced manner, and the source electrode and the drain electrode are connected with the crystalline active pattern, and the gate electrode is arranged corresponding to the crystalline active pattern.

[0070] Specifically, the gate insulating layer 140 covering the crystalline active pattern 130 and the substrate 110 is formed by using chemical vapor deposition, and the gate electrode 160 arranged corresponding to the crystalline active pattern 130 is formed on the surface of the gate insulating layer 140 away from the substrate 110; then, the first contact hole 140a and the second contact hole 140b arranged corresponding to the crystalline active pattern 130 are formed on the gate insulating layer 140 by using a photolithography process and an etching process, and the source-drain electrode 150 is formed on the gate insulating layer 140, the source-drain electrode 150 includes the source electrode 1501 and the drain electrode 1502, the source electrode 1501 is arranged corresponding to the first contact hole 140a and connected with one contact part 1303 of the crystalline active pattern 130 through the first contact hole 140a, and the drain electrode 1502 is arranged corresponding to the second contact hole 140b and connected with another contact part 1303 of the crystalline active pattern 130 through the second contact hole 140b, as shown in FIG. 6. Figure 5G

[0071] The crystalline active pattern of the thin film transistor in the embodiment is crystallized in the groove of the heat preservation layer by using the quasi-molecular laser crystallization and the common action of the heat preservation layer, and then formed by using a specific patterning process, so that the crystal lattice size of the crystalline active pattern is large, the crystal boundary of the crystalline active pattern is less and controllable.

[0072] It should be noted that the manufacturing method of the thin film transistor in the embodiment can be used to manufacture the thin film transistor including the special-shaped active layer (non-linear active layer) to be applied to the special-shaped area of the special-shaped display panel, for example, the round corner of the display panel with the round corner, to adapt to the special-shaped corner edge of the special-shaped display panel; and can also be applied to the normal display area of the conventional display panel, for example, the thin film transistor including the strip-shaped active layer to be applied to the normal display area of the conventional display panel, for example, the rectangular display area of the conventional display panel.

[0073] ​This application also provides a display panel. The display panel can be applied to mobile phones, displays, automotive displays, and electronic watches, etc. The display panel can be a liquid crystal display panel, an organic light-emitting diode display panel, a micro-light-emitting diode display panel, a quantum dot display panel, or a micro-light-emitting diode display panel, etc. The display panel includes the aforementioned thin-film transistors.

[0074] Please see Figure 6 This is a plan view of a display panel according to an embodiment of the present application. The display panel 200 has four arc-shaped corner edges 200a, two opposing first straight edges 200b, and two opposing second straight edges 200c. An arc-shaped corner edge 200a connects an adjacent first straight edge 200b and a second straight edge 200c.

[0075] The above Figure 1 and Figure 2 The thin-film transistor shown can be positioned along four curved corner edges 200a, or along two first straight edges 200b and two opposing second straight edges 200c.

[0076] In this embodiment of the application, at least a portion of the crystalline active pattern of the thin-film transistor in the display panel is formed in the groove of the heat insulation layer. The heat insulation layer reduces the cooling rate during the crystallization process of forming the crystalline active pattern, thereby increasing the grain size in the crystalline active pattern and improving the mobility of the thin-film transistor, enabling the display panel to achieve high-frequency display.

[0077] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A thin-film transistor, characterized in that, include: The insulation layer is located on the substrate and has grooves. A crystalline active pattern, wherein at least a portion of the crystalline active pattern is located in the groove; A gate insulating layer is located in the groove and covers the surface of the crystalline active pattern and the surface of the substrate, the gate insulating layer being spaced from the sidewall of the groove; The source and drain electrodes are located on the gate insulating layer and include a source and a drain electrode spaced apart. Both the source and the drain electrode are connected to the crystal active pattern through vias in the gate insulating layer. The gate is configured corresponding to the crystal active pattern.

2. The thin-film transistor according to claim 1, characterized in that, Along the direction perpendicular to the thickness of the insulation layer, the opening size of the groove is less than or equal to 200 nanometers.

3. The thin-film transistor according to claim 2, characterized in that, The active crystal pattern is a single crystal grain.

4. The thin-film transistor according to claim 1, characterized in that, Along the direction perpendicular to the thickness of the insulation layer, the opening size of the groove is greater than 200 nanometers.

5. The thin-film transistor according to claim 4, characterized in that, The active crystallization pattern is located in the groove. The active crystallization pattern includes at least two crystal lattices, and there is a grain boundary between two adjacent crystal lattices. The extension direction of the grain boundary is the same as the extension direction of the active crystallization pattern.

6. The thin-film transistor according to any one of claims 1-5, characterized in that, The depth of the groove is less than or equal to the thickness of the insulation layer.

7. The thin-film transistor according to any one of claims 1-5, characterized in that, The thickness of the insulation layer is greater than or equal to 3000 angstroms and less than or equal to 10000 angstroms.

8. A method for manufacturing a thin-film transistor, characterized in that, The method includes the following steps: A heat insulation layer is formed on a substrate, and the heat insulation layer is provided with grooves; A crystalline active pattern is formed, at least a portion of which is located in the groove; A gate insulating layer is formed, the gate insulating layer being located in the groove and covering the surface of the crystalline active pattern and the surface of the substrate, the gate insulating layer being spaced from the sidewall of the groove; A source / drain electrode and a gate are formed. The source / drain electrode is located on the gate insulating layer and includes a source and a drain that are spaced apart. The source and the drain are connected to the crystal active pattern through vias in the gate insulating layer. The gate is configured corresponding to the crystal active pattern.

9. The method for manufacturing a thin-film transistor according to claim 8, characterized in that, The formation of the crystalline active pattern includes the following steps: At least an amorphous silicon semiconductor layer is formed in the groove; The amorphous silicon semiconductor layer is annealed using an excimer laser annealing process to obtain a crystalline silicon semiconductor layer; The crystalline silicon semiconductor layer is patterned to obtain the crystalline active pattern.

10. A display panel, characterized in that, The display panel includes a thin-film transistor as described in any one of claims 1-7.

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