Semiconductor device and electronic device

Abstract

The application provides a semiconductor device and an electronic device. The semiconductor device comprises: an insulating substrate; a non-planar layer, the non-planar layer being located on the insulating substrate, the non-planar layer comprising a non-planar structure, the non-planar structure comprising a sidewall; and an active pattern, at least part of the active pattern being located on the sidewall of the non-planar structure, the active pattern comprising a channel located on the sidewall; wherein a ratio of a dimension of the non-planar structure in a thickness direction of the non-planar layer to a thickness of the active pattern is less than or equal to 7.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a semiconductor device and an electronic device. BACKGROUND

[0002] Integrating integrated circuits (Integrated Circuit) on a glass substrate (System On Glass, SOG) can greatly improve the integration of display panels and reduce the manufacturing cost of display panels. However, realizing the integration of integrated circuits on a glass substrate requires improving the mobility of traditional thin film transistors.

[0003] Therefore, how to provide the mobility of the thin film transistor is a technical problem to be solved. SUMMARY

[0004] The purpose of the present application is to provide a semiconductor device and an electronic device to provide conditions for improving the mobility of the semiconductor device.

[0005] To achieve the above purpose, the technical scheme is as follows:

[0006] A semiconductor device, comprising:

[0007] An insulating substrate;

[0008] A non-flat layer, the non-flat layer is located on the insulating substrate, the non-flat layer comprises a non-flat structure, the non-flat structure comprises a sidewall;

[0009] An active pattern, at least part of the active pattern is located on the sidewall of the non-flat structure, the active pattern comprises a channel located on the sidewall;

[0010] Wherein, the ratio of the size of the non-flat structure in the thickness direction of the non-flat layer to the thickness of the active pattern is less than or equal to 7.

[0011] In some embodiments of the semiconductor device, the ratio of the size of the non-flat structure in the thickness direction of the non-flat layer to the thickness of the active pattern is greater than or equal to 2.

[0012] In some embodiments of the semiconductor device, the thickness of the active pattern is greater than or equal to 350 angstroms and less than or equal to 600 angstroms.

[0013] In some embodiments of the semiconductor device, the slope angle of the sidewall on the insulating substrate is greater than or equal to 45 degrees and less than or equal to 90 degrees.

[0014] In some embodiments of the semiconductor device, the channel is at least part of a single crystal grain.

[0015] In some embodiments of the semiconductor device, the single die has a size greater than or equal to 0.25 microns.

[0016] In some embodiments of the semiconductor device, the channel comprises a plurality of grains.

[0017] In some embodiments of the semiconductor device, the active pattern comprises a plurality of grains.

[0018] In some embodiments of the semiconductor device, the active pattern is a low-temperature polysilicon active pattern.

[0019] In some embodiments of the semiconductor device, the semiconductor device further comprises a gate located on a side of the active pattern distal to the sidewall, the gate overlapping a footprint of the channel on the substrate.

[0020] In some embodiments of the semiconductor device, the semiconductor device further comprises a gate insulating layer disposed between the gate and the active pattern, the gate insulating layer comprising an inclined portion covering a portion of the active pattern on the sidewall, the gate comprising a gate sidewall on the inclined portion, a slope angle of the gate sidewall on the inclined portion being greater than or equal to 30 degrees and less than or equal to 60 degrees.

[0021] In some embodiments of the semiconductor device, the active pattern further comprises a first contact portion and a second contact portion connected to opposite sides of the channel.

[0022] The semiconductor device further comprises:

[0023] an interlayer insulating layer located on a side of the gate insulating layer distal to the insulating substrate, the interlayer insulating layer covering the gate and the gate insulating layer;

[0024] a first contact hole penetrating through the interlayer insulating layer and the gate insulating layer and disposed corresponding to the first contact portion;

[0025] a second contact hole penetrating through the interlayer insulating layer and the gate insulating layer, the second contact hole disposed corresponding to the second contact portion;

[0026] a source electrode in contact with the first contact portion through the first contact hole; and

[0027] a drain electrode in contact with the second contact portion through the second contact hole.

[0028] In some embodiments of the semiconductor device, the sidewall comprises an insulating sidewall in contact with the channel.

[0029] In some embodiments of the semiconductor device, the non-planar structure includes a protrusion structure or a groove structure, and the sidewall is the sidewall of the protrusion structure or the sidewall of the groove structure.

[0030] An electronic device, the electronic device comprising the aforementioned semiconductor device.

[0031] Beneficial Effects: This application provides a semiconductor device and an electronic device in which the ratio of the dimension of the non-planar structure in the thickness direction of the non-planar layer to the thickness of the active pattern is less than or equal to 7. This results in a smaller dimension of the non-planar structure in the thickness direction of the non-planar layer, which in turn leads to a smaller sidewall dimension and a shorter channel length for the active pattern located on the sidewall of the non-planar structure. Furthermore, during crystallization to form the active pattern, seed crystals are more easily formed at the corners adjacent to the sidewalls of the non-planar structure. When the seed crystal grows along the sidewall to form a single grain, the shorter channel length on the sidewall provides conditions for the channel on the sidewall to be composed of single grains. Since there are no grain boundaries in the single grain, this provides conditions for forming a semiconductor device with high mobility, including single grain channels, thereby providing conditions for integrating an integrated chip onto an insulating substrate. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of a traditional thin-film transistor array substrate;

[0033] Figure 2 This is a plan view of a semiconductor device according to an embodiment of this application;

[0034] Figure 3 For along Figure 2 A schematic diagram of the cross-section of the semiconductor device shown, with the AA tangent line as indicated.

[0035] Figure 4 For along Figure 2 A schematic diagram of the cross-section of the BB tangent of the semiconductor device shown;

[0036] Figure 5 for Figure 3 A partially enlarged schematic diagram of the gate on the inclined portion of the gate insulating layer;

[0037] Figure 6 This is a plan view of a semiconductor device according to another embodiment of this application;

[0038] Figure 7 along Figure 6 A schematic diagram of the cross-section of the CC tangent of the semiconductor device shown.

[0039] Figures 8A-8J A schematic diagram illustrating the process of manufacturing a semiconductor device according to an embodiment of this application. Detailed Implementation

[0040] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0041] Please see Figure 1 This is a schematic diagram of a traditional thin-film transistor array substrate. Combined with... Figure 1 As can be seen, the active layer 10 of a traditional thin-film transistor is located on a plane. Due to the limitations of exposure and etching precision in the display panel manufacturing process, the length L of the channel 101 of the active layer 10 is often greater than 2 micrometers. The channel 101 with a length greater than 2 micrometers has more grain boundaries, resulting in a lower mobility of the thin-film transistor.

[0042] To address the problems in conventional technologies, this application provides a semiconductor device in which the ratio of the dimension of the non-planar structure in the thickness direction of the non-planar layer to the thickness of the active pattern is less than or equal to 7. This results in a smaller dimension of the non-planar structure in the thickness direction of the non-planar layer, leading to smaller sidewall dimensions and shorter channel lengths for the active patterns located on the sidewalls of the non-planar structure. Furthermore, during crystallization to form the active pattern, seed crystals are more easily formed at the corners adjacent to the sidewalls of the non-planar structure. When the seed crystals grow along the sidewalls to form single grains, the shorter channel length on the sidewalls provides conditions for the sidewall channels to consist of single grains. Since there are no grain boundaries in the single grains, this provides conditions for forming a semiconductor device with high mobility and single-grain channels, thereby providing conditions for integrating an integrated chip onto an insulating substrate.

[0043] Please see Figure 2 , Figure 3 as well as Figure 4 , Figure 2 This is a plan view of a semiconductor device according to an embodiment of this application. Figure 3 For along Figure 2 A schematic diagram of the cross-section of the semiconductor device shown, with line AA as the tangent. Figure 4 For along Figure 2 A schematic diagram of the cross-section of the BB tangent of the semiconductor device shown.

[0044] In this embodiment, the semiconductor device 100 is a vertical thin-film transistor. The semiconductor device 100 includes an insulating substrate 21, a light-shielding pattern 22, a buffer layer 23, a non-planar layer 24, an active pattern 25, a gate insulating layer 26, a gate 27, an interlayer insulating layer 28, and source / drain electrodes.

[0045] In the present embodiment, the insulating substrate 21 is a glass substrate, but is not limited thereto, and the insulating substrate 21 can also be a flexible substrate.

[0046] In the present embodiment, the light-shielding pattern 22 plays a role of shielding ambient light incident to the portion of the active pattern 25. The light-shielding pattern 22 is disposed on the insulating substrate 21. The light-shielding pattern 22 is made of a metal material, which includes, but is not limited to, at least one of molybdenum, aluminum, titanium, copper, and silver; and the light-shielding pattern 22 can also be made of a black matrix or the like.

[0047] In the present embodiment, the buffer layer 23 covers the insulating substrate 21 and the light-shielding pattern 22. The buffer layer 23 is made of at least one of silicon nitride or silicon oxide. The thickness of the buffer layer 23 is greater than or equal to 2500 angstroms and less than or equal to 3500 angstroms, for example, 2500 angstroms, 2800 angstroms, 3000 angstroms, 3200 angstroms, or 3500 angstroms.

[0048] In the present embodiment, the non-flat layer 24 is disposed on the buffer layer 23. The non-flat layer 24 is not flat. The non-flat layer 24 includes a non-flat structure 241, which is a convex structure, and portions of the non-flat layer 24 other than the non-flat structure 241 are removed.

[0049] The non-flat structure 241 can be at least one of a convex quadrangular prism structure, a convex cube structure, or a convex cuboid structure. The non-flat structure 241 can be formed by one film layer, two film layers, or more than two film layers stacked together, and the film layers constituting the non-flat structure 241 include an insulating layer, which includes at least one of an inorganic insulating layer and an organic insulating layer, the inorganic insulating layer being made of a material including, but not limited to, silicon oxide or silicon nitride, and the organic insulating layer being made of a material including, but not limited to, polyimide, polyacrylate, and organic silicon or the like.

[0050] The non-flat structure 241 has a side wall 243 and a top surface 242 connected to the side wall 243. The side wall 243 is located at a side of the non-flat structure 241 and is not coplanar with the buffer layer 23, the side wall 243 of the non-flat structure 241 being a side wall of the convex structure, and the side wall 243 overlaps the light-shielding pattern 22. The side wall 243 includes at least one of a plane and a curved surface, and the curved surface includes a convex curved surface and / or a concave curved surface. The top surface 242 is located at a side of the non-flat structure 241 away from the insulating substrate 21.

[0051] It should be noted that when the film layers constituting the non-flat structure 241 are insulating layers, the side wall 243 of the non-flat structure 241 includes insulating side walls. It can be understood that the film layers constituting the non-flat structure 241 can also include conductive film layers.

[0052] In the present embodiment, the active pattern 25 extends from the buffer layer 23 to the top surface 242 of the non-flat structure 241 via the sidewall 243 of the non-flat structure 241.

[0053] The active pattern 25 includes a plurality of grains, in other words, a plurality of grain boundaries are included in the active pattern 25. Specifically, the active pattern 25 is a low-temperature polysilicon active pattern, but is not limited thereto, and the active pattern 25 can also be a crystalline metal oxide active pattern.

[0054] The active pattern 25 includes a channel 251 and a first contact portion 252 and a second contact portion 253 connected to opposite sides of the channel 251, at least a portion of the channel 251 of the active pattern 25 is located on the sidewall 243, the first contact portion 252 is located on the buffer layer 23, and the second contact portion 253 is located on the top surface 242 of the non-flat structure 241.

[0055] Among them, at least a portion of the channel 251 of the active pattern 25 located on the sidewall 243 means that the channel 251 of the active pattern 25 is entirely located on the sidewall 243; or a portion of the channel 251 of the active pattern 25 is located on the sidewall 243, and another portion of the channel 251 of the active pattern 25 is located on the buffer layer 23 of the insulating substrate 21; or a portion of the channel 251 of the active pattern 25 is located on the sidewall 243, and another portion of the channel 251 of the active pattern 25 is located on the top surface 242 of the non-flat structure 241; or a portion of the channel 251 of the active pattern 25 is located on the sidewall 243, and another portion of the channel 251 of the active pattern 25 is located on the buffer layer 23 of the insulating substrate 21 and the top surface 242 of the non-flat structure 241.

[0056] It should be noted that the channel 251 is designed to be located on the sidewall 243, but due to process deviation, the channel 251 may not be completely on the sidewall 243.

[0057] The active pattern 25 further includes a first lightly doped portion 254 and a second lightly doped portion 255, the first lightly doped portion 254 is connected between the first contact portion 252 and the channel 251, and the first lightly doped portion 254 is located on the buffer layer 23, the second lightly doped portion 255 is connected between the second contact portion 253 and the channel 251, and the second lightly doped portion 255 is located on the top surface 242 of the non-flat structure 241.

[0058] The first lightly doped portion 254, the second lightly doped portion 255, and the channel 251 are located in the orthographic projection of the light-shielding pattern 22 on the insulating substrate 21, in other words, the light-shielding pattern 22 shields the light incident to the first lightly doped portion 254, the second lightly doped portion 255, and the channel 251.

[0059] It is also to be noted that the first contact portion 252, the second contact portion 253, the first lightly doped portion 254 and the second lightly doped portion 255 are all doped with ions, and the doping concentration of the ions in the first contact portion 252 and the second contact portion 253 is greater than the doping concentration of the ions in the first lightly doped portion 254 and the second lightly doped portion 255.

[0060] The thickness of the active pattern 25 is greater than or equal to 350 angstroms and less than or equal to 600 angstroms, for example, 350 angstroms, 380 angstroms, 400 angstroms, 420 angstroms, 440 angstroms, 460 angstroms, 480 angstroms, 500 angstroms, 520 angstroms, 540 angstroms, 560 angstroms or 600 angstroms.

[0061] In the present embodiment, the ratio of the dimension H of the non-planar structure 241 in the thickness direction of the non-planar layer 24 to the thickness of the active pattern 25 is less than or equal to 7, and in the case where the non-planar structure 241 is a convex structure, i.e., the ratio of the thickness of the non-planar structure 241 to the thickness of the active pattern 25 is less than or equal to 7, correspondingly, the thickness of the non-planar structure 241 is less than 4200 angstroms, so that the length of the sidewall 243 of the non-planar structure 241 is small, and the length L1 of the channel 251 of the active pattern 25 located on the sidewall 243 is less than 1 micron, which is less than the length of the channel in the conventional technology which is more than 2 microns. In addition, during the crystallization to form the active pattern 25, the active pattern 25 before crystallization is more likely to form a seed crystal at the corner between the buffer layer 23 and the sidewall 243, and when the seed crystal grows along the sidewall 243 to form a single crystal grain, the length L1 of the channel 251 located on the sidewall 243 is less than 1 micron, which provides a condition for the channel 251 on the sidewall 243 to be composed of a single crystal grain, and the single crystal grain does not have a grain boundary, thereby providing a condition for forming a semiconductor device including a single crystal grain channel and having high mobility.

[0062] In addition, the ratio of the dimension H of the non-planar structure 241 in the thickness direction of the non-planar layer 24 to the thickness of the active pattern 25 is greater than or equal to 2, which ensures that the channel 251 of the active pattern 25 is composed of a single crystal grain while avoiding the thickness of the non-planar structure 241 being too thin to cause the length L1 of the channel 251 to be too small, thereby requiring a corresponding large adjustment of other structures such as the gate insulating layer of the semiconductor device 100. In addition, the thickness of the non-planar structure 241 being too thin will affect the thickness uniformity of the non-planar structure 241, and further affect the thickness uniformity of the active pattern 25 located on the non-planar structure 241.

[0063] The ratio of the size H of the non-flat structure 241 in the thickness direction of the non-flat layer 24 to the thickness of the active pattern 25 can be greater than or equal to 2.5 and less than or equal to 6, or the ratio of the size H of the non-flat structure 241 in the thickness direction of the non-flat layer 24 to the thickness of the active pattern 25 can be greater than or equal to 3 and less than or equal to 5, or the ratio of the size H of the non-flat structure 241 in the thickness direction of the non-flat layer 24 to the thickness of the active pattern 25 can be greater than or equal to 3 and less than or equal to 4.

[0064] For example, the ratio of the size H of the non-flat structure 241 in the thickness direction of the non-flat layer 24 to the thickness of the active pattern 25 can be 2, 2.2, 2.5, 2.8, 3, 3.2, 3.5, 3.8, 4.0, 4.2, 4.4, 4.6, 4.8, 5.0, 5.2, 5.5, 5.8, 6.0, 6.2, 6.5, 6.8, or 7.0.

[0065] Specifically, in the thickness direction of the non-flat layer 24, the size H of the non-flat structure 241 can be greater than or equal to 800 angstroms and less than or equal to 3000 angstroms, or greater than or equal to 1200 angstroms and less than or equal to 2700 angstroms, or greater than or equal to 1500 angstroms and less than or equal to 2400 angstroms.

[0066] For example, in the thickness direction of the non-flat layer 24, the size H of the non-flat structure 241 can be 1000 angstroms, 1200 angstroms, 1400 angstroms, 1600 angstroms, 1800 angstroms, 2000 angstroms, 2200 angstroms, 2400 angstroms, 2600 angstroms, 2800 angstroms, or 3000 angstroms.

[0067] In the present embodiment, the first slope angle a of the sidewall 243 on the insulating substrate 21 is greater than or equal to 45 degrees and less than or equal to 90 degrees, and the ratio of the size H of the non-flat structure 241 in the thickness direction of the non-flat layer 24 to the thickness of the active pattern 25 is greater than or equal to 2 and less than or equal to 7, so that the length L1 of the channel 251 can be reduced to 0.01 microns to 1 micron, and the width of the channel 251 can be controlled to 0.3 microns to 10 microns. In addition, the first slope angle a is greater than or equal to 45 degrees and less than or equal to 90 degrees, which is conducive to more easily forming a seed crystal at the corner between the buffer layer 23 and the sidewall 243 of the non-flat structure 241, the seed crystal grows along the sidewall 243, and the channel 251 with a length L1 of 0.01 microns to 1 micron, so that the channel 251 is more likely to be composed of a single grain.

[0068] The first slope angle a can be greater than or equal to 45 degrees and less than or equal to 90 degrees, or the first slope angle a can be greater than or equal to 50 degrees and less than or equal to 80 degrees, or the first slope angle a can be greater than or equal to 60 degrees and less than or equal to 70 degrees. For example, the first slope angle a can be 50 degrees, 55 degrees, 60 degrees, 65 degrees, 70 degrees, 75 degrees, 80 degrees or 90 degrees.

[0069] In the embodiment, by controlling the size of the non-flat structure 241 in the thickness direction of the non-flat layer 24 to control the first slope angle a of the matching sidewall 243, the size of the sidewall 243 is small, the length L1 of the channel 251 on the sidewall 243 is 0.01 microns to 1 microns, so that the channel 251 is at least part of a single grain, in other words, the channel 251 is a single grain, or the channel 251 is part of a single grain.

[0070] In the embodiment, the channel 251 of the active pattern of the semiconductor device 100 is at least part of a single grain, so that there is no grain boundary in the channel 251, the mobility of the carrier in the channel 251 is improved, and the mobility of the semiconductor device is improved, which is beneficial to realize the integration of the integrated chip on the insulating substrate, so as to reduce the manufacturing cost of the display panel.

[0071] In the embodiment, the size of the single grain constituting the channel 251 is greater than or equal to 0.25 microns, so as to adapt to the size of the grain formed by crystallizing amorphous silicon by the excimer laser annealing process. For example, the size of the single grain is 0.28 microns, 0.29 microns, 0.30 microns, 0.32 microns, 0.35 microns, 0.36 microns, 0.38 microns or 0.4 microns.

[0072] It should be noted that the size of the grain obtained by crystallizing amorphous silicon by the excimer laser annealing process is small, and the difference between the length of the current channel and 2 microns is also large, which cannot make the channel consist of a single grain. The present application controls the size of the non-flat structure in the thickness direction of the non-flat layer to control the first slope angle of the matching sidewall, so as to reduce the length of the channel, and then make the length of the channel tend to be the same as the size of the single grain of the current laser annealing process. Moreover, the design of the non-flat structure makes it easier to form a seed crystal near the corner of the sidewall, which provides conditions for the seed crystal to grow into a single grain along the sidewall, and then provides conditions for the channel with a small length on the sidewall to consist of a single grain.

[0073] It is understood that in other embodiments, the channel 251 may also include polycrystalline materials; in other words, the channel 251 includes multiple grain boundaries. After the channel 251 is disposed on the sidewall 243, the length L1 of the channel 251 is reduced to 0.01 micrometers to 1 micrometer. When the channel 251 includes polycrystalline materials, the grain boundaries of the channel 251 are correspondingly reduced, which is beneficial for improving the mobility of semiconductor devices and for enabling the integration of integrated chips onto a glass insulating substrate, thereby reducing the manufacturing cost of the display panel.

[0074] In this embodiment, the gate insulating layer 26 covers the active pattern 25, the non-planar structure 241, and the buffer layer 23. The gate insulating layer 26 includes an inclined portion 261, which is inclined relative to the insulating substrate 21. The inclined portion 261 covers the portion of the active pattern 25 located on the sidewall 243. In other words, the inclined portion 261 is located above the portion of the active pattern 25 located on the sidewall 243. The orthographic projection of the inclined portion 261 on the insulating substrate 21 is located within the orthographic projection of the light-shielding pattern 22 on the insulating substrate 21.

[0075] The gate insulating layer 26 is made of at least one of silicon nitride or silicon oxide. The thickness of the gate insulating layer 26 is greater than or equal to 500 angstroms and less than or equal to 1500 angstroms. For example, the thickness of the gate insulating layer 26 is 600 angstroms, 800 angstroms, 1000 angstroms, 1200 angstroms, 1400 angstroms, or 1500 angstroms.

[0076] In this embodiment, the gate 27 is located on the side of the active pattern 25 away from the sidewall 243. A portion of the gate 27 is located on the inclined portion 261 of the gate insulating layer 26, and another portion of the gate 27 is located on the surface of the gate insulating layer 26 above and away from the non-planar structure 241. It can be understood that the gate 27 may also be located between the non-planar structure 241 and the insulating substrate 21.

[0077] The orthographic projection of the gate 27 on the insulating substrate 21 overlaps with the orthographic projection of the channel 251 on the insulating substrate 21, so as to adapt to the process of forming the channel 251, the first lightly doped portion 254 and the second lightly doped portion 255 by doping with the gate 27 as a mask.

[0078] Specifically, in this embodiment, such as Figure 2 As shown, the orthographic projection of the gate 27 on the insulating substrate 21 completely overlaps with the orthographic projection of the channel 251 on the insulating substrate 21. In other words, the outer contour of the orthographic projection of the gate 27 on the insulating substrate 21 completely coincides with the outer contour of the orthographic projection of the channel 251 on the insulating substrate 21, and the area of ​​the orthographic projection of the gate 27 on the insulating substrate 21 is equal to the area of ​​the orthographic projection of the channel 251 on the insulating substrate 21.

[0079] It is understood that in other embodiments, the orthographic projection of the channel 251 on the insulating substrate 21 is located within the orthographic projection of the gate 27 on the insulating substrate 21. Correspondingly, the outer contour of the orthographic projection of the gate 27 on the insulating substrate 21 is located outside the outer contour of the orthographic projection of the channel 251 on the insulating substrate 21, and the area of ​​the orthographic projection of the gate 27 on the insulating substrate 21 is larger than the area of ​​the orthographic projection of the channel 251 on the insulating substrate 21.

[0080] like Figure 5 As shown, it is Figure 3 The diagram shows a partially enlarged view of the gate on the inclined portion of the gate insulating layer. The gate 27 includes a gate sidewall 271 located on the inclined portion 261. The gate sidewall 271 is located on the side of the gate 27 and connected to the inclined portion 261. The second slope angle β of the gate sidewall 271 on the inclined portion 261 is greater than or equal to 30 degrees and less than or equal to 60 degrees to adapt to the manufacturing process of the gate 27.

[0081] The second slope angle β can be greater than or equal to 40 degrees and less than or equal to 55 degrees, or the second slope angle β can be greater than or equal to 45 degrees and less than or equal to 50 degrees. For example, the second slope angle β is 30 degrees, 40 degrees, 45 degrees, 48 ​​degrees, 50 degrees, 52 degrees, 55 degrees, 58 degrees, or 60 degrees.

[0082] The orthogonal projection of the gate 27 onto the sidewall 243 covers a portion of the orthogonal projection of the channel 251 onto the sidewall 243.

[0083] The material used to fabricate gate 27 is selected from at least one of molybdenum, aluminum, titanium, copper, and silver.

[0084] In this embodiment, as Figure 3 As shown, the interlayer insulating layer 28 covers the gate 27 and the gate insulating layer 26. The material used to fabricate the interlayer insulating layer 28 is selected from at least one of silicon nitride or silicon oxide. The thickness of the interlayer insulating layer 28 is greater than or equal to 5000 angstroms and less than or equal to 6500 angstroms, for example, 5200 angstroms, 5400 angstroms, 5500 angstroms, 5600 angstroms, or 5800 angstroms.

[0085] In this embodiment, the source and drain electrodes include a source electrode 291 and a drain electrode 292. The source electrode 291 contacts the first contact portion 252 of the active pattern 25 through a first contact hole 100a that penetrates the interlayer insulating layer 28 and the gate insulating layer 26 and corresponds to the first contact portion 252; the drain electrode 292 contacts the second contact portion 253 of the active pattern 25 through a second contact hole 100b that penetrates the interlayer insulating layer 28 and the gate insulating layer 26 and corresponds to the second contact portion 253. The source electrode 291 and the drain electrode 292 are made of at least one material selected from molybdenum, aluminum, titanium, copper, and silver.

[0086] like Figure 6and Figure 7 as shown, Figure 6 is a plan view of another embodiment of the semiconductor device of the present application, Figure 7 is a cross-sectional view along the C-C line of the semiconductor device shown in Figure 6 The semiconductor device of the present embodiment is basically similar to the semiconductor device shown in Figure 2 The semiconductor device of the present embodiment is basically similar to the semiconductor device shown in Figure 6 and Figure 7 The orthogonal projection of the channel 251 of the semiconductor device 100 shown in Figure 6 and Figure 7 The non-planar layer 24 of the semiconductor device shown in is a buffer layer 23, the non-planar structure 241 is located on the buffer layer 23, the non-planar structure 241 is a groove 23a on the buffer layer 23, the sidewall 243 of the non-planar structure 241 is the sidewall of the groove 23a, the size H of the non-planar structure 241 in the thickness direction of the non-planar layer 24 is the depth of the groove 23a, the depth of the groove 23a is less than the thickness of the buffer layer 23, and correspondingly, the size H of the non-planar structure 241 in the thickness direction of the non-planar layer 24 is less than the thickness of the buffer layer 23; and the first lightly doped portion 254 and the first contact portion 252 are located in the groove 23a, the channel 251 is located on one sidewall of the groove 23a, and the second lightly doped portion 255 and the second contact portion 253 are located on the surface of the buffer layer 23 away from the insulating substrate 21.

[0087] The non-planar structure of the semiconductor device of the present embodiment is a groove provided on the buffer layer, which is beneficial to avoid adding a new film layer on the semiconductor device to prepare the non-planar structure, thereby simplifying the process.

[0088] The present application also provides a manufacturing method of a semiconductor device, the manufacturing method of the semiconductor device comprising the following steps:

[0089] S101: forming a non-planar layer on an insulating substrate, the non-planar layer comprising a non-planar structure, the non-planar structure having a sidewall.

[0090] Specifically, as shown in Figure 8A An insulating substrate 21 is provided, and a light shielding pattern 22 is formed on the insulating substrate 21.

[0091] Next, as shown in Figure 8BAs shown, a buffer layer 23 is formed covering the light-shielding pattern 22 and the insulating substrate 21. A non-planar layer 24 is formed on the buffer layer 23. The non-planar layer 24 includes a non-planar structure 241, which is a raised structure. All parts of the non-planar layer 24 except for the non-planar structure 241 are removed. The non-planar structure 241 has a sidewall 243 and a top surface 242 connected to the sidewall 243. The sidewall 243 is located on the side of the non-planar structure 241. The first slope angle α of the sidewall 243 is greater than or equal to 45 degrees and less than or equal to 90 degrees. The top surface 242 is located on the side of the non-planar structure 241 away from the insulating substrate 21.

[0092] S102: Form an active pattern at least partially located on the sidewall of the non-planar structure, and form a gate on the side of the active pattern away from the sidewall.

[0093] Specifically, such as Figure 8C As shown, a full-surface amorphous silicon semiconductor layer 301 is formed on the buffer layer 23 and the non-planar structure 241.

[0094] Next, as Figure 8D As shown, the amorphous silicon semiconductor layer 301 is annealed and crystallized using an excimer laser annealing process. During this process, seed crystals 3011 easily form at the corner between the buffer layer 23 and the sidewall 243. The seed crystals 3011 grow into single grains along the sidewall 243. When the length of the sidewall 243 is small, the single grain can be located on the entire sidewall 243. Figure 8E As shown, after the amorphous silicon semiconductor layer 301 is processed by excimer laser annealing, a low-temperature polycrystalline silicon semiconductor layer 302 is obtained.

[0095] Then, as Figure 8F As shown, a patterning process is used to pattern the low-temperature polysilicon semiconductor layer 302 to obtain a low-temperature polysilicon pattern 303. The low-temperature polysilicon pattern 303 extends from the buffer layer 23 through the sidewall 243 of the non-planar structure 241 to the top surface 242 of the non-planar structure 241. The low-temperature polysilicon pattern 303 has a first contact region 303a, a second contact region 303b, a first transition region 303c, a second transition region 303d, and a channel region 303e. At least a portion of the channel region 303e is located on the sidewall 243. The first contact region 303a and the second contact region 303b are respectively connected to opposite sides of the channel region 303e. The first transition region 303c is connected between the first contact region 303a and the channel region 303e. The second transition region 303d is connected between the second contact region 303b and the channel region 303e.

[0096] Next, as Figure 8GAs shown, the first contact region 303a and the second contact region 303b of the low-temperature polysilicon pattern 303 are processed by a heavy doping process to obtain a heavily doped low-temperature polysilicon pattern 304. The heavily doped low-temperature polysilicon pattern 304 includes a first contact portion 252 located in the first contact region 303a and a second contact portion 253 located in the second contact region 303b. The first contact portion 252 is located on the buffer layer 23, and the second contact portion 253 is located on the top surface 242 of the non-planar structure 241.

[0097] Finally, as Figure 8H As shown, a gate insulating layer 26 is formed covering a heavily doped low-temperature polysilicon pattern 304 and a buffer layer 23. A gate 27 is formed on the surface of the gate insulating layer 26 away from the sidewall 243 of the non-planar structure 241. Using the gate 27 as a mask, the first transition region 303c and the second transition region 303d of the heavily doped low-temperature polysilicon pattern 304 are lightly doped to obtain an active pattern 25. The active pattern 25 includes a first lightly doped portion 254 located in the first transition region 303c, a second lightly doped portion 255 located in the second transition region 303d, and a channel 251 located in the channel region 303e. The channel 251 is located on the sidewall 243. The first lightly doped portion 254 is connected between the first contact portion 252 and the channel 251 and is located on the buffer layer 23. The second lightly doped portion 255 is connected between the second contact portion 253 and the channel 251 and is located on the top surface 242 of the non-planar structure 241.

[0098] S103: Forms the source and drain electrodes that are in contact with the active pattern.

[0099] Specifically, such as Figure 8I As shown, an interlayer insulating layer 28 is formed covering the gate 27 and the gate insulating layer 26. A patterning process is used to process the interlayer insulating layer 28 and the gate insulating layer 26 to obtain a first contact hole 100a and a second contact hole 100b that both penetrate the interlayer insulating layer 28 and the gate insulating layer 26. The first contact hole 100a is disposed corresponding to the first contact portion 252, and the second contact hole 100b is disposed corresponding to the second contact portion 253. Figure 8J As shown, a source electrode 291 is formed on the surface of the interlayer insulating layer 28 and in the first contact hole 100a, and a drain electrode 292 is formed on the surface of the interlayer insulating layer 28 and in the second contact hole 100b. The source electrode 291 contacts the first contact portion 252 through the first contact hole 100a, and the drain electrode 292 contacts the second contact portion 253 through the second contact hole 100b.

[0100] In this embodiment, the thickness of the active pattern 25 is greater than or equal to 350 angstroms and less than or equal to 600 angstroms, for example, 350 angstroms, 380 angstroms, 400 angstroms, 420 angstroms, 440 angstroms, 460 angstroms, 480 angstroms, 500 angstroms, 520 angstroms, 540 angstroms, 560 angstroms or 600 angstroms.

[0101] In the embodiment, the ratio of the size of the non-flat structure 241 in the thickness direction of the non-flat layer 24 to the thickness of the active pattern 25 is less than or equal to 7, and in the case that the non-flat structure 241 is a convex structure, the ratio of the thickness of the non-flat structure 241 to the thickness of the active pattern 25 is less than or equal to 7, corresponding to the thickness of the non-flat structure 241 being less than 4200 angstroms, so that the length of the sidewall 243 of the non-flat structure 241 is small, and the length of the channel 251 of the active pattern 25 on the sidewall 243 is less than 1 micron, which is less than the length of the channel in the conventional technology which is more than 2 microns. In addition, during the annealing crystallization process of the amorphous silicon semiconductor layer 301, the seed crystal 3011 is easily formed at the corner between the buffer layer 23 and the sidewall 243, and when the seed crystal grows along the sidewall 243 to form a single crystal grain, the length of the channel 251 formed on the sidewall 243 is less than 1 micron, which provides the forming condition for the channel 251 on the sidewall 243 to be composed of a single crystal grain, and there is no grain boundary in the single crystal grain, thereby providing the forming condition for the semiconductor device including the single crystal channel and having high mobility.

[0102] In addition, the ratio of the size of the non-flat structure 241 in the thickness direction of the non-flat layer 24 to the thickness of the active pattern 25 is greater than or equal to 2, which ensures that the channel 251 of the active pattern 25 is composed of a single crystal grain, while avoiding the thickness of the non-flat structure 241 being too thin to cause the length of the channel 251 to be too small, thereby making other structures such as the gate insulating layer of the semiconductor device 100 need to be adjusted correspondingly.

[0103] In the embodiment, the first slope angle a of the sidewall 243 on the insulating substrate 21 is greater than or equal to 45 degrees and less than or equal to 90 degrees, which, in combination with the ratio of the size of the non-flat structure 241 in the thickness direction of the non-flat layer 24 to the thickness of the active pattern 25 being greater than or equal to 2 and less than or equal to 7, makes the length of the channel 251 be reduced to 0.01 micron to 1 micron, and the width of the channel 251 be controlled to 0.3 micron to 10 micron. In addition, the first slope angle a is greater than or equal to 45 degrees and less than or equal to 90 degrees, which is beneficial to more easily form a seed crystal at the corner between the buffer layer 23 and the sidewall 243 of the non-flat structure 241, and the seed crystal grows along the sidewall 243 in combination with the channel 251 having a length of 0.01 micron to 1 micron, so that the channel 251 is more likely to be composed of a single crystal grain.

[0104] The application also provides an electronic device comprising the semiconductor device. The electronic device can comprise a circuit of an integrated chip integrated on an insulating substrate. The electronic device can also be a display panel integrated with the integrated chip, and the display panel can be any one of a liquid crystal display panel, an organic light-emitting diode display panel, a quantum dot display panel, a micro light-emitting diode display panel, and a sub-millimeter light-emitting diode display panel.

[0105] The above description of the embodiments is only used to help understand the technical solutions of the present application and the core ideas thereof; it should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features thereof can be replaced equivalently; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: Insulating substrate; A non-planar layer, the non-planar layer being located on the insulating substrate, the non-planar layer including a non-planar structure, the non-planar structure including sidewalls; An active pattern, at least a portion of which is located on the sidewall of the non-planar structure, the active pattern including a channel located on the sidewall, the channel having a length of less than 1 micrometer; wherein the ratio of the dimension of the non-planar structure in the thickness direction of the non-planar layer to the thickness of the active pattern is less than or equal to 4. A gate is located on the side of the active pattern away from the sidewall; and A gate insulating layer is located between the gate and the active pattern.

2. The semiconductor device according to claim 1, characterized in that, The ratio of the dimension of the non-planar structure in the thickness direction of the non-planar layer to the thickness of the active pattern is greater than or equal to 2.

3. The semiconductor device according to claim 1 or 2, characterized in that, The thickness of the active pattern is greater than or equal to 350 angstroms and less than or equal to 600 angstroms.

4. The semiconductor device according to claim 1, characterized in that, The slope angle of the sidewall on the insulating substrate is greater than or equal to 45 degrees and less than or equal to 90 degrees.

5. The semiconductor device according to claim 1, characterized in that, The channel is at least a portion of a single grain.

6. The semiconductor device according to claim 5, characterized in that, The size of the individual crystal grain is greater than or equal to 0.25 micrometers.

7. The semiconductor device according to claim 1, characterized in that, The channel comprises polycrystalline grains.

8. The semiconductor device according to claim 1, characterized in that, The active pattern includes polycrystalline materials.

9. The semiconductor device according to claim 1, characterized in that, The active pattern is a low-temperature polycrystalline silicon active pattern.

10. The semiconductor device according to claim 1, characterized in that, The orthogonal projection of the gate on the substrate overlaps with the orthogonal projection of the channel on the substrate.

11. The semiconductor device according to claim 10, characterized in that, The gate insulating layer includes a sloped portion that covers a portion of the active pattern located on the sidewall. The gate includes a gate sidewall located on the sloped portion, and the slope angle of the gate sidewall on the sloped portion is greater than or equal to 30 degrees and less than or equal to 60 degrees.

12. The semiconductor device according to claim 1, characterized in that, The active pattern also includes a first contact portion and a second contact portion connected to opposite sides of the channel; The semiconductor device further includes: An interlayer insulating layer is located on the side of the gate insulating layer away from the insulating substrate, and the interlayer insulating layer covers the gate and the gate insulating layer; The first contact hole penetrates the interlayer insulating layer and the gate insulating layer, and is disposed corresponding to the first contact portion; The second contact hole penetrates the interlayer insulating layer and the gate insulating layer, and the second contact hole is provided corresponding to the second contact portion; The source electrode contacts the first contact portion through the first contact hole; and The drain electrode contacts the second contact portion through the second contact hole.

13. The semiconductor device according to claim 1, characterized in that, The sidewall includes an insulating sidewall that contacts the channel.

14. The semiconductor device according to claim 1, characterized in that, The non-flat structure includes a protruding structure or a grooved structure, and the sidewall is the sidewall of the protruding structure or the sidewall of the grooved structure.

15. An electronic device, characterized in that, The electronic device includes the semiconductor device as described in any one of claims 1-14.

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