Interleaved Boost Converter with Hold Time

Abstract

The present disclosure relates to interleaved boost converters having a hold-up time. A power factor correction device for providing tolerance for fault conditions in an input power supply may include a first boost circuit, a second boost circuit, and a controller circuit. When the input power supply is received by the power factor correction device, the controller circuit may interleave the operation of the first boost circuit and the operation of the second boost circuit to generate an output voltage. The controller circuit may route a stored power supply of the second boost circuit to an input of the first boost circuit in response to the fault condition. The controller circuit may control the first boost circuit to maintain the output voltage.

Description

[0001] This application is a divisional application of the invention patent application with the application date of December 20, 2018, application number 201811562719.9, and invention title "Interleaved Boost Converter with Hold Time". Technical Field

[0002] This document generally but not limited to electronic power supplies, and more specifically, relates to power factor correction circuits. Background Art

[0003] Power supplies typically convert an AC power supply into a DC power supply for use by electronic devices. The structure and operation of a power supply can introduce harmonics and cause a difference between the phase of the voltage provided by an AC source and the phase of the current drawn from the AC power supply, thereby reducing the power factor and thus the efficiency of the power supply. A power factor correction circuit, such as a boost converter, can be used to correct or improve the power factor of a power supply by reducing these phase differences and canceling the effects of harmonics. For example, an inductor in a boost converter circuit can switch between a charged state and a discharged state at a frequency and has a modulated duty cycle that is selected to cause the power supply to produce a substantially constant output voltage while aligning or matching the average current flowing through the inductor with an expected inductor current (e.g., a current in phase with the AC power supply voltage). Since the current through the inductor is drawn from the AC power supply, aligning the average inductor current with the AC power supply voltage can align the AC power supply current with the AC power supply voltage, thereby improving the power factor of the power supply. By interleaving the operation of, for example, two boost converters, the power factor and overall efficiency of the power supply can be further improved.

[0004] Industrial regulations and equipment requirements may require a power supply to maintain a regulated output voltage for a threshold time period (e.g., a hold time interval) during a fault condition in the AC source (e.g., a loss in the AC power supply voltage). Techniques to meet these requirements can include adding an energy storage device (e.g., a capacitor) to the power supply to extend the hold time during an input power supply fault. However, the added energy storage device can increase the size and cost of the power supply. Additionally, the added energy storage device can reduce the power supply efficiency by reducing the power factor of its power supply. For example, a storage capacitor added to the power supply output to extend the hold time can contribute to a phase difference between the AC power supply voltage provided to the power supply and the AC power supply current drawn by the power supply. Summary of the Invention

[0005] The present disclosure is based on the following recognition: A power factor correction device for providing tolerance for fault conditions in an input power supply may include a first boost circuit, a second boost circuit, and a controller circuit. The controller circuit may be configured to, when the input power supply is received by the power factor correction device, stagger the operations of the first boost circuit and the second boost circuit to generate an output voltage. The controller circuit may also be configured to route the stored power of the second boost circuit to the input of the first boost circuit in response to the fault condition. The controller circuit may additionally be configured to control the first boost circuit to maintain the output voltage.

[0006] The present disclosure is also based on the following recognition: A system configured to provide tolerance for fault conditions in an input power supply may include an input power supply and a power factor correction circuit. The power factor correction circuit may include a first boost circuit, a second boost circuit, and a controller circuit. The controller circuit may be configured to, when the input power supply is received by the power factor correction device, stagger the operations of the first boost circuit and the second boost circuit to generate an output voltage. The controller circuit may also be configured to route the stored power of the second boost circuit to the input of the first boost circuit in response to the fault condition. The controller circuit may additionally be configured to control the first boost circuit to maintain the output voltage.

[0007] The present disclosure is additionally based on the following recognition: A method for operating a power factor correction device to provide tolerance for fault conditions in an input power supply may include staggering the operations of a first boost circuit and a second boost circuit to generate an output voltage from the input power supply. The method may also include detecting a fault condition of the input power supply. The method may additionally include routing the stored power of the second boost circuit to the input of the first boost circuit in response to the detected fault condition to maintain the output voltage.

[0008] This summary is intended to provide an overview of the subject matter of this patent application. Its purpose is not to provide an exclusive or exhaustive interpretation of the invention. The detailed description is included to provide further information about this patent application. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A block diagram depicting an example system having a power factor correction circuit configured with an integrated hold time extension circuit is shown.

[0010] Figure 2 A block diagram depicting an example of a power factor correction circuit having interleaved boost converters and an integrated hold time extension circuit is shown.

[0011] Figure 3 A block diagram depicting a control circuit of a power factor correction circuit having interleaved boost converters and an integrated hold time extension circuit is shown.

[0012] Figure 4 An example of a schematic diagram of a system having a power factor correction circuit and an integrated hold time extension circuit configured to operate in an interleaved mode is depicted, where the power factor correction circuit has interleaved boost converters.

[0013] Figure 5 An example of a schematic diagram of a system having a power factor correction circuit and an integrated hold time extension circuit configured to operate in a hold time extension mode is depicted, where the power factor correction circuit has interleaved boost converters.

[0014] Figure 6 An example of a schematic diagram of a system having a power factor correction circuit with interleaved boost converters and an integrated hold time extension circuit having semiconductor switches and a control circuit is depicted.

[0015] Figure 7 A set of operations for operating a power factor correction circuit having interleaved boost converters and an integrated hold time extension circuit is depicted.

[0016] In the figures, which are not necessarily drawn to scale, the same numbers may describe similar components in different views. The same numbers with different letter suffixes may represent different instances of similar components. The figures illustrate, by way of example and not limitation, various embodiments discussed in this document. Detailed Description

[0017] The present disclosure is based on the recognition that a power factor correction apparatus for providing tolerance for fault conditions in an input power supply may include a first boost circuit, a second boost circuit, and a controller circuit. The controller circuit may be configured to interleave the operation of the first boost circuit and the operation of the second boost circuit to produce an output voltage when the input power supply is received by the power factor correction apparatus. The controller circuit may also be configured to route a stored power supply of the second boost circuit to an input of the first boost circuit in response to the fault condition. The controller circuit may additionally be configured to control the first boost circuit to maintain the output voltage.

[0018] The present technology can be understood in the context of extending the hold-up time of an output voltage generated by a power supply (e.g., a linear power supply configured to convert an input power supply (e.g., an AC line voltage) into a DC power supply for operating an electronic device). Such electronic devices can include security systems, electronic medical devices, industrial machines, consumer electronics, and computing systems. Integrating a hold-up time extension circuit into a interleaved boost converter used as a power factor correction circuit can extend the hold-up time at a lower cost and size during a fault condition of the power supply compared to other solutions. Existing output capacitors in each of a pair of boost converters of the interleaved boost converter circuit can operate respectively as a primary energy storage device for maintaining the output voltage to hold the output voltage and as a secondary energy storage device for recharging the primary energy storage device to extend the hold-up time. For example, during a power supply fault, the secondary energy storage device can operate as an input to a boost converter having the primary energy storage device, such that the energy stored in the secondary energy storage device is discharged through the boost converter to the primary energy storage device. By extending the hold-up time using existing components of a power factor correction circuit, the present technology can provide a power system capable of meeting or exceeding industrial and product requirements, including power supply, such as efficiency and hold-up time, e.g., reducing cost and size.

[0019] For ease of discussion, the term hold-up time is used herein; however, it should be understood that the present technology is also useful for meeting other input power supply or power supply fault tolerance requirements.

[0020] Referring now to the drawings, Figure 1 FIG. 1 depicts a block diagram of an example of a system 100 having a power factor correction circuit 110 configured with an integrated hold-up time extension circuit. The system 100 can include an input power supply 105, a power factor correction circuit 110, a load 120, and a control circuit 125. The system 100 can represent a general application of a power system, where the input power supply 105 (e.g., an AC power supply) is regulated by the power factor correction circuit 110 under the control of the control circuit 125 to provide an output voltage to the load 120.

[0021] The input power supply 105 can be any circuit configured to provide a rectified AC power supply or any portion of a rectified AC power supply. For example, the input power supply 105 can be configured to provide a rectified root mean square voltage between 93 and 264 volts. A phase shift between the voltage provided by the AC power supply and the current drawn from the AC power supply can reduce the power factor of the input power supply 105, thereby reducing efficiency (e.g., the ratio of the portion of power that the input power supply provides useful work to the total power provided by the input power supply). Harmonics in the AC source can similarly reduce the power factor of the input power supply 105.

[0022] Throughout this disclosure, the terms input power supply fault, input power supply fault condition, and fault condition in the input power supply can be used and can be used to indicate an interruption or abnormal condition of the AC power supply and / or rectified AC power supply provided by the input power supply 105. For example, an input power supply fault can be a partial or complete attenuation or loss of one or more cycles of the rectified AC power supply. Other input power supply faults are applicable to this disclosure.

[0023] The power factor correction circuit 110 can include passive or active electrical components that can be configured to condition or regulate the input power supply 105 (e.g., the rectified AC power supply provided by the input power supply) to counteract a reduction in the power factor caused by AC source phase variations and harmonics. For example, conditioning the input power supply 105 can include adjusting (e.g., modulating) the current flowing through the interleaved boost converters of the power factor correction circuit 110 such that the average current drawn from the input power supply 105 is phase-aligned or phase-matched with the voltage provided by the input power supply. The power factor correction circuit 110 can also include circuitry for extending the hold-up time of the output voltage in response to an input power supply fault, e.g., using techniques described herein.

[0024] The control circuit 125 can include one or more circuits for monitoring the power supply in the system 100, e.g., activating one or more components of the power factor correction circuit 110 to improve the power factor of the input power supply 105. The control circuit 125 can monitor the AC power supply powering the input power supply 105, the current flowing through the power factor correction circuit 110, and the output of the electric power factor correction circuit to determine how and whether to modulate the current drawn by the power factor correction circuit to improve the power factor of the input power supply. The control circuit 125 can also include circuitry for controlling the hold-up time extension circuit integrated in the power factor correction circuit 110, e.g., as described herein.

[0025] The load 120 can include a power conversion device, e.g., a DC-DC converter, that can be configured to convert the output voltage provided by the power factor correction circuit 110 into a voltage that can be used by another electronic device or system. For example, the system 100 or the load 120 can require that the output voltage provided by the power correction circuit be at a threshold voltage level (e.g., at or above a minimum voltage level) to support efficient operation of the load. The system 100 or the load 120 can also specify hold-up time requirements. The term "hold-up time" as used herein generally refers to the length of time that the output voltage provided by the power factor correction circuit 110 remains at or above a threshold voltage level during an input power supply fault condition. Generally, the hold-up time can indicate the tolerance of the input power supply fault condition.

[0026] Figure 2A block diagram depicting an example of a power factor correction circuit 200 with interleaved boost converter circuits 205 and 215 and an integrated hold time extension circuit 210 is shown. Although the hold time extension circuit 210 is depicted as being separable from the boost converter circuit 205 and the boost converter circuit 215, the hold time extension circuit can be integrated with one or more boost converter circuits and can include one or more components of one or more of the boost converter circuits. The power correction circuit 200 can be an example of the power factor correction circuit 110( Figure 1 ), and is generally used to correct or counteract a reduction in the power factor of an input power supply, such as the input power supply 105( Figure 1 ). A control circuit, such as the control circuit 125( Figure 1 ), can interleave the operation of the boost converter circuit 205 and operate the boost converter circuit 215 such that the power factor correction circuit 200 produces an output voltage having a high power factor (e.g., a power factor close to 1), such as in response to receiving an input power supply.

[0027] As used herein, the term interleaved or interleaving refers to alternately operating at least two circuits (e.g., operating two switching circuits to switch between two states at opposite times or 180 degrees out of phase) to produce an output. For example, the operation of the boost converter circuit 205 and the operation of the boost converter circuit 215 can be interleaved by causing the boost converter circuit 205 to discharge for a first period of time while the boost converter circuit 215 is charging. Then, the interleaved operation can continue by causing the boost converter circuit 205 to charge for a second period of time while the boost converter circuit 215 discharges.

[0028] As used herein, the term interleaved or interleaving can also refer to at least partially overlapping operating modes of two or more electronic circuits to produce an output. For example, the operation of the boost converter circuit 205 and the operation of the boost converter circuit 215 can be interleaved by causing the boost converter circuit 205 to discharge for a first period of time while the boost converter circuit 215 is at least partially charging and discharging. Then, the interleaved operation can continue by causing the boost converter circuit 205 to be at least partially charging and discharging for a second period of time while the boost converter circuit 215, for example, discharges.

[0029] When the power factor correction circuit 200 operates in an interleaved mode (e.g., an operating mode in which the AC power supply of the power factor conversion circuit 200 powering the input power supply does not have a fault condition), the control circuit can cause the boost converter circuit 205 and the boost converter circuit 215 to alternately store energy received from the input power supply and supply it to, for example, a load 120( Figure 1) or a load such as a boost converter 215. Under such conditions, at least a portion of the hold time extension circuit 210 may provide a path for the energy stored in the boost converter 215 to be discharged through the load.

[0030] During an input power fault condition (e.g., when the AC power source of the power factor conversion circuit 200 that powers the input power source drops out), the hold-up time extension circuit 210 may be initiated (e.g., by the control circuit 125) to route the stored energy of the boost converter circuit 215 to the input of the boost converter circuit 205. The boost converter circuit 205 may then use the input of the boost converter circuit 215 to replace the failed input power source.

[0031] During an input power fault condition, for example, after the output voltage generated by the power factor correction circuit 200 drops to or below a threshold voltage level, the hold-up time extension circuit can be activated. The boost converter circuit 205 can use the stored energy of the boost converter circuit 215 to maintain the output voltage of the power factor correction circuit 200 at or above the threshold voltage level for a period of time, for example, to extend the duration of the power factor correction circuit 200.

[0032] Figure 3 A block diagram of a control circuit 300 for a power factor correction circuit with interleaved boost converters and an integrated hold-up time extension circuit is depicted. The control circuit 300 may implement the control circuit 125 ( Figure 1 ), and can be used to operate the power factor correction circuit 200 ( Figure 2 ) to generate an output voltage when an input power is received at the power factor correction circuit. The control circuit 300 can, for example, control the operation of the boost converter circuit 205 and the boost converter circuit 215 ( Figure 2 ) operation. The control circuit 300 may actuate the hold time extension circuit 210 ( Figure 2 ) to route the stored power of boost converter circuit 215 to the input of boost converter circuit 205 in response to an input power fault condition ( Figure 2 ) For example, the power factor correction circuit output voltage is maintained at or above a threshold voltage level. The control circuit 300 may include a sensing circuit 305, a boost converter control circuit 310, and a hold time extension control circuit 315.

[0033] The sensing circuit 305 may include circuits and electronic components to monitor, for example, the input power 105 ( Figure 1 ) of the AC power supply voltage and current, the current flowing through the boost converter in the power factor correction circuit 200, and the output voltage of the power factor correction circuit. Generally, the sensing circuit 305 may include active and passive electronic components for monitoring, for example, the system 100 (Figure 1 ) one or more physical characteristics (e.g., amplitude, frequency, and phase), such as voltage and current.

[0034] The boost converter control circuit 310 may include circuitry for interleaving the operation of, for example, the boost converter circuit 205 and the operation of the boost converter circuit 215, as described herein. The boost converter control circuit 310 may use the output of the sensing circuit 305, for example, to determine whether to adjust the current drawn by the power factor correction circuit 200 in order to modify the power factor of the input power supply to the power factor correction circuit. For example, the boost converter control circuit 310 may use the output of the sensing circuit 305 to determine frequency and duty cycle modulation, for example, for alternating between the charging and discharging states of the boost converter circuit 205 and the boost converter circuit 215.

[0035] The hold time extension control circuit 315 may include circuitry for operating the hold time extension circuit 210 to route the stored power of the boost converter circuit 215 to the input terminal of the boost converter circuit 205 in response to an input power supply fault condition. For example, the hold time extension control circuit 315 may control the boost converter circuit 205 to maintain the output voltage of the power factor correction circuit 200, for example, using the stored energy of the boost converter circuit 215 as the input power supply. The boost converter control circuit 310 may control the boost converter circuit 205 to maintain the output voltage of the power factor correction circuit 200, for example, using the stored energy of the boost converter circuit 215 as the input power supply.

[0036] Although the sensing circuit 305, the boost converter control circuit 310, and the hold time extension control circuit 315 are shown as separate circuits, one or more of these circuits may be integrated with other circuits and may include components of other circuits.

[0037] Figure 4 An example of a schematic diagram of a system 400 having a power factor correction circuit (with interleaved boost converters) and an integrated hold time extension circuit (configured to operate in an interleaved mode) is depicted. The system 400 may implement the system 100 using a control circuit 125 (not shown). The system 400 may include an input power supply circuit 410 (e.g., an input power supply) formed by semiconductor devices 415 and a switch S1, boost converter circuits 405 and 425, a load 420, and a hold time extension circuit. The hold time extension circuit may also include an energy storage device, such as a capacitor C2.

[0038] The boost converter circuit 405 and the boost converter circuit 425 may be the boost converter circuit 205 ( Figure 2 ) and the boost converter 215 ( Figure 2) Example. The boost converter circuit 405 and the boost converter circuit 425 can be configured with substantially the same components and can operate according to the same electrical principles, except that the operation of the boost converters can generally be interleaved, for example resulting in one boost converter charging while the other boost converter discharges. For example, each of the boost converter circuit 405 and the boost converter circuit 425 can generally include a charging or input energy storage device (e.g., inductor L1 or inductor L2), a discharging or output energy storage device (e.g., capacitor C1 or capacitor C2), a switching device (e.g., switches S2 and S3), and a biased semiconductor device (e.g., a diode, such as diode D1 or diode D3, or a diode-connected transistor).

[0039] During one interleaved mode operation phase of the power factor correction circuit formed by the boost converter circuit 405 and the boost converter circuit 425, switch S2 is closed while switches S1 and S3 are open. In such a phase, diode D1 is reverse biased, and current can flow from the bridge rectifier formed by diodes D4, D5, D6, and D7 through inductor L1 and switch S2. Current L1 charges the inductor (e.g., causes inductor L1 to store energy in a magnetic field), while the reverse bias of diode D1 causes capacitor C1 to discharge through load 420. During the same operating phase, inductor L2 discharges through capacitor C2 and load 420, charging capacitor C2 in the process. In a second interleaved phase, switch S3 is closed while switches S2 and S1 are open. During this second interleaved phase, the operation of the boost converter circuits 405 and 425 is interchanged (e.g., inductor L2 and capacitor C1 are charged while inductor L1 and capacitor C2 are discharged).

[0040] In the interleaved mode, when diode D2 is forward biased (e.g., biased to allow current flow), capacitors C1 and C2 generally form a single energy storage device. The combined stored energy of capacitors C1 and C2 can maintain the output voltage generated by the power factor correction circuit, for example by filtering the ripples that cause the charging and discharging of inductors L1 and L2 while the input power supply 410 is available (e.g., no fault condition in the AC power supply powering the input power supply).

[0041] One or more of switches S1, S2, and S3 can be an electronic switch (e.g., a semiconductor device such as a transistor) or an electro-mechanical switch controlled by electricity.

[0042] Figure 5 An example of a schematic diagram of a system 500 having a power factor correction circuit (with interleaved boost converters) and an integrated hold time extension circuit (configured to operate in a hold time extension mode) is depicted. System 500 can be related to system 400 ( Figure 4) are substantially the same, but switch S1 is closed and the AC source is unavailable (e.g., there is an AC source fault condition).

[0043] When the system 500 is in the hold mode (e.g., the operating mode of the system 500 when there is a fault in the AC source), switch S1 is initially open, and diode D2 is forward biased, connecting capacitor C1 and capacitor C2. Capacitor C1 and capacitor C2 can discharge, for example, until the output voltage of the power factor correction circuit reaches a threshold voltage level. The threshold voltage level can be determined by, for example, a specified voltage reference. A control circuit, such as control circuit 300( Figure 3 ), can monitor the voltage at the output of the power factor correction circuit and can compare it with a reference voltage to determine when capacitor C1 and capacitor C2 have discharged to the threshold voltage level. The threshold voltage level can be specified as the normal interleaved mode output voltage of the power factor correction circuit (e.g., the average interleaved mode output voltage) or a percentage or fraction of the normal operating voltage of the load 420. For example, the threshold voltage level can be specified as the minimum voltage for the load to operate effectively. For example, the threshold voltage can be specified as at least 80% of the normal interleaved mode operating voltage.

[0044] The hold time can represent the time it takes for capacitor C1 and capacitor C2 to fully discharge so that the output voltage of the power factor correction circuit reaches the threshold voltage level. The hold time can be extended by closing switch S1 and controlling switch S2 (e.g., switching or cycling switch S2 at a specific frequency and specific duty cycle) in order to operate the boost converter circuit 405 and the system 500 in the hold time extension mode.

[0045] During the hold time extension mode, diode D2 becomes reverse biased (e.g., configured to inhibit the flow of current), decoupling capacitor C2 from the load 420 (e.g., removing the coupling). Closing switch S2 when switch S1 is closed causes current to flow from capacitor C2 through switch S1, inductor L1, and switch S2, charging inductor L1 using the stored energy of capacitor C2. Subsequently, inductor L1 discharges through capacitor C1 and load 420, and opening switch S2 charges capacitor C1 using the previously stored energy of capacitor C2. Repeating the process of closing and opening switch S2 as described above can transfer the stored energy of capacitor C2 to capacitor C1. Transferring the stored energy from capacitor C2 to capacitor C1 in this way can enable capacitor C1 to maintain the output voltage of the power factor conversion circuit at or above the threshold voltage level.

[0046] The amount of time that capacitor C2 can maintain the output voltage of the power factor conversion circuit at the threshold voltage level can be referred to as the hold extension time. Generally, the hold time and the hold extension time can be determined at least in part by the capacitance values of capacitors C1 and C2, the threshold voltage level of the power factor correction circuit, and the amount of current drawn by load 420.

[0047] Figure 6 An example schematic diagram of system 600 is depicted. System 600 includes a power factor correction circuit having interleaved boost converters and an integrated hold time extension circuit having semiconductor switches and control circuitry. System 600 can implement system 400( Figure 4 ), where transistors (e.g., semiconductor devices) M1, M2, and M3 replace switches S1, S2, and S3, respectively. System 600 can also include a regulation circuit 605, a comparison circuit 610 (e.g., an amplifier), and a boost converter control circuit 615.

[0048] Although transistors M1, M2, and M3 are shown as N-channel field effect transistors (FETs), switches S1, S2, and S3 can be replaced with other switching devices, including, for example, bipolar junction transistors or other types of field effect transistors (e.g., P-channel FETs).

[0049] Regulation circuit 605 and comparison circuit 610 can be examples of at least a portion of hold time extension control circuit 315 and sensing circuit 305, e.g., Figure 3 as shown. Comparison circuit 610 can compare the output of the power factor correction circuit to a reference voltage. The output of comparison circuit 610 can be regulated (e.g., amplified, attenuated, or otherwise converted to a different voltage or signal), e.g., by regulation circuit 605, and can be used to control transistor M1 (e.g., Figure 5 switch S1 in

[0050] ), as described herein. The reference voltage can be a function or version of the threshold voltage level at which the power factor correction circuit provides power to load 420. Figure 3 Boost converter control circuit 615 can implement boost converter control circuit 310, as Figure 4 and 5 shown. Boost converter control circuit 615 can use one or more feedback signals (e.g., a measurement or indication of the current or voltage provided by the AC source, the current through inductor L1 or L2, and the output voltage of the power factor correction circuit), which can be provided by one or more sensing circuits, to control the operation of transistors M2 and M3 (e.g.,

[0051] Figure 7 switches S2 and S3 in

[0051] Figure 7 ), as described herein.Depicts an example of a set of operations 700 for operating a power factor correction circuit with a staggered (e.g., alternating operation) boost converter, which has an integrated hold time extension circuit. Operations 700 can be performed to, for example, provide tolerance to the power factor correction circuit for input power supply fault conditions. The power factor correction circuit can include any power factor correction circuit described in the discussion of Figures 1-6 . Operations 700 can be performed by a control circuit, such as control circuit 125 ( Figure 1 ) or control circuit 300 ( Figure 3 ).

[0052] At 705, the operation of the primary boost circuit and the operation of the secondary boost circuit in the power factor conversion circuit can be alternated or staggered to cause the power factor correction circuit to generate an output voltage from the input power supply. Such staggering can include monitoring the current drawn from the AC power supply powering the input power supply, the voltage provided by the input power supply, the current through each boost converter circuit, and the output voltage of the power factor conversion circuit. Such staggering can also include controlling the frequency or duty cycle or both of the charging and discharging of energy storage devices (e.g., inductors) in the boost converter circuits, as described herein.

[0053] At 710, the output voltage of the power factor correction circuit can be monitored to detect a fault condition in the input power supply. The fault condition can include, for example, a loss of the input power supply voltage, or another anomaly in the input power supply. At 715, it can be determined whether a fault condition has been detected at 710. Operations 705, 710, and 715 can be repeated in the absence of a detected fault condition.

[0054] If a fault condition is detected, then at 720, the stored power supply of the secondary boost converter circuit can be routed to the input of the primary boost converter circuit to maintain the output voltage of the power factor conversion circuit. Routing the stored power supply can include electrically isolating the energy storage device (e.g., capacitor) of the secondary boost converter circuit from the output of the power factor conversion circuit. For example, such isolation can include reverse biasing a semiconductor device (e.g., diode) that couples the energy storage device to the output of the boost converter circuit. Routing the stored power supply can also include electrically coupling the isolated energy storage device to the input of the primary boost converter circuit. The isolated energy storage device can be coupled to the input of the primary boost converter circuit, for example, by closing an electrical switch, or forward biasing a semiconductor device (e.g., transistor) to create a closed path for current to flow between the energy storage device and the primary boost converter.

[0055] At 725, the stored power supply of the second boost circuit can be used to operate the first boost circuit to maintain the output voltage of the power factor correction circuit, as described herein.

[0056] At 730, it can be determined whether a fault condition is still detected. Operation 725 can be repeated while a fault condition is still detected. If a fault condition is not detected (e.g., there is an input power supply), then at 735, the stored power supply of the secondary boost converter circuit can be disconnected from the primary boost converter circuit. Then, the execution of operation 700 can continue at operation 705.

[0057] Each non-limiting aspect or example described herein can exist independently, or can be in various permutations and combinations or combined with one or more other examples.

[0058] The detailed description above includes references to the accompanying drawings, which form a part of the detailed description. The drawings illustrate, by way of example, specific embodiments in which the invention can be implemented. These embodiments are also referred to herein as "examples". These examples can include elements other than those shown or described. However, the inventors also contemplate examples that provide only those elements shown or described. In addition, the inventors also contemplate examples using any combination or permutation of those elements (or one or more aspects thereof), with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0059] If there is any inconsistency in the usage between this document and any document incorporated by reference, the usage in this document shall prevail.

[0060] In this document, the terms "a" or "an" are common in patent documents and include one or more than one, independent of any other instance or usage of "at least one" or "one or more". In this document, the term "or" is used to mean non-exclusive, such that "A or B" includes "A but not B", "B but not A", "A and B", unless otherwise indicated. In this document, the terms "comprising" and "wherein" are used as equivalents of the corresponding terms "including" and "wherein". In addition, in the following claims, the terms "comprising" and "including" are open-ended, i.e., a system, apparatus, article, composition, formulation, or process that includes elements other than those listed after this term in the claim is still considered to be within the scope of the claim. In addition, in the following claims, the terms "first", "second", "third", etc. are used only as labels and are not intended to impose a numerical requirement on their objects.

[0061] The method examples described herein can be at least partially machine or computer-implemented. Some examples can include a computer-readable medium or machine-readable medium encoded with instructions that are operable to configure an electronic device to perform the methods described in the above examples. Implementations of such methods can include code, such as microcode, assembly language code, higher-level language code, etc. Such code can include computer-readable instructions for performing various methods. The code can form part of a computer program product. Additionally, in an example, the code can be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of such tangible computer-readable media can include, but are not limited to, hard disks, removable disks, removable optical disks (e.g., compact discs and digital video discs), magnetic tapes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), etc.

[0062] The foregoing description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) can be used in combination with each other. After reading the above description, other embodiments can be used by, for example, a person of ordinary skill in the art. The abstract is provided to comply with 37 C.F.R.§1.72(b) and allows the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above detailed description, various features can be combined together to simplify the disclosure. This should not be construed as intending that the disclosed features for which there is no claim are essential to any claim. Instead, the inventive subject matter can lie in less than all of the features of a particular disclosed embodiment. Thus, the following claims are incorporated into the detailed description as examples or embodiments, where each claim stands on its own as a separate embodiment, and it is contemplated that these embodiments can be combined with each other in various combinations or permutations. The scope of the present invention should be determined with reference to the appended claims and the full scope of equivalents to which those claims are entitled.

[0063] In one embodiment, wherein the semiconductor device is a diode, and wherein decoupling includes reverse biasing the diode.

[0064] In one embodiment, wherein controlling the first boost circuit to maintain the output voltage includes operating the first boost circuit as a boost converter using the stored power as an input.

[0065] In one embodiment, wherein routing the stored power includes using the first boost circuit to transfer at least a portion of the energy of the stored power from the second energy storage device to the first energy storage device.

[0066] In one embodiment, where the routing includes controlling the first boost circuit to maintain the output voltage includes causing the first boost circuit to alternate between charging a third energy storage device using a stored power source in the first boost circuit and discharging the third energy storage device through the first energy storage device.

Claims

1. A power factor correction device with an integrated hold time extension circuit for providing tolerance for fault conditions in an input power supply having a bridge rectifier, the device comprising: A first boost circuit having an input configured to receive a rectified output from the bridge rectifier and including a first energy storage device coupled to an output of the power factor correction device; A second boost circuit having an input configured to receive a rectified output from the bridge rectifier and including a second energy storage device coupled to the first energy storage device; And A controller circuit configured to: When there is no fault condition in the input power supply, interleaving the operation of the first boost circuit and the operation of the second boost circuit to generate an output voltage, In response to a fault condition in the input power supply, routing the stored power of the second energy storage device from the second boost circuit to the input of the first boost circuit, wherein routing includes decoupling the second energy storage device from the first energy storage device and includes coupling the second energy storage device to the input of the first boost circuit by closing a switch, and Controlling the first boost circuit to maintain the output voltage; Wherein the integrated hold time extension circuit includes: A semiconductor device for decoupling the second energy storage device from the first energy storage device; and The switch, Wherein the semiconductor device is connected to a second electrical terminal of the first energy storage device and a second electrical terminal of the second energy storage device, Wherein, A first electrical terminal of the first energy storage device is directly connected to a first electrical terminal of the second energy storage device, The switch is a field effect transistor, and The controller circuit further includes: A comparison circuit configured to detect the fault condition by detecting that the output voltage drops below a threshold level; and An adjustment circuit configured to: Receive an output signal from the comparison circuit; Adjust the output signal; and Control the field effect transistor using the adjusted output signal applied to the gate of the field effect transistor.

2. The device according to claim 1, wherein: The second energy storage device is coupled to the first energy storage device through the semiconductor device; and Decoupling includes biasing the semiconductor device to inhibit current flow through the semiconductor device.

3. The device according to claim 2, wherein the semiconductor device is a diode, and wherein decoupling includes reverse biasing the diode.

4. The device according to claim 1, wherein routing the stored power includes using the first boost circuit to transfer at least a portion of the energy of the stored power from the second energy storage device to the first energy storage device.

5. The device according to claim 1, wherein at least one of the first energy storage device and the second energy storage device includes a capacitor.

6. The device according to claim 1, wherein the second energy storage device is coupled to the input of the first boost circuit through a transistor controlled by the controller circuit.

7. The apparatus according to claim 1, wherein controlling the first boost circuit to maintain the output voltage includes causing the first boost circuit to alternate between charging a third energy storage device in the first boost circuit using a stored power supply and discharging the third energy storage device through the first energy storage device.

8. The apparatus according to claim 7, wherein the third energy storage device is an inductor configured at an input of the first boost circuit to receive the routed stored power supply of the second boost circuit.

9. The apparatus according to claim 1, wherein controlling the first boost circuit to maintain the output voltage includes operating the first boost circuit as a boost converter using the stored power supply as an input.

10. A system configured to provide tolerance to fault conditions in an input power supply, the system comprising: an input power supply; and a power factor correction device according to any one of claims 1-9.

11. A method for operating a power factor correction device having an integrated hold time extension circuit to provide tolerance to fault conditions in an input power supply having a bridge rectifier, the method comprising: interleaving the operation of a first boost circuit and the operation of a second boost circuit to generate an output voltage from the input power supply, the first boost circuit having an input configured to receive a rectified output from the bridge rectifier and including a first energy storage device coupled to an output of the power factor correction device, the second boost circuit having an input configured to receive a rectified output from the bridge rectifier and including a second energy storage device coupled to the first energy storage device, and wherein a first electrical terminal of the first energy storage device is directly connected to a first electrical terminal of the second energy storage device; detecting a fault condition in the input power supply; and in response to the detected fault condition, routing the stored power supply of the second energy storage device from the second boost circuit to an input of the first boost circuit to maintain the output voltage; wherein routing includes decoupling the second energy storage device from the first energy storage device and includes coupling the second energy storage device to the input of the first boost circuit by closing a switch, the integrated hold time extension circuit comprising: a semiconductor device for decoupling the second energy storage device from the first energy storage device; and the switch, wherein the semiconductor device is connected to a second electrical terminal of the first energy storage device and a second electrical terminal of the second energy storage device, wherein the switch is a field effect transistor, and the method further comprises: providing a comparison circuit to detect the fault condition by detecting that the output voltage drops below a threshold level; receiving an output signal from the comparison circuit by an adjustment circuit; adjusting the output signal by the adjustment circuit; and controlling the field effect transistor by the adjustment circuit using the adjusted output signal applied to a gate of the field effect transistor.

12. The method according to claim 11, wherein: the second energy storage device is coupled to the first energy storage device through the semiconductor device; and the decoupling includes biasing the semiconductor device to inhibit current flow through the semiconductor device.

13. The method according to claim 11, wherein said routing includes controlling said first boost circuit to maintain said output voltage, including causing said first boost circuit to alternate between charging a third energy storage device in the first boost circuit using a stored power source and discharging the third energy storage device through said first energy storage device.

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