Pulse width fraction adjustment operator

Abstract

The present application provides a pulse width fraction adjustment operator, comprising: a pulse width fraction adjuster, a state controller, an integer frequency divider and a pulse width operator connected together; input signals include a frequency divided clock signal, a reference clock signal, integer frequency division values N1, N2 and a fraction frequency division value F; output signals include comparison results UP and DW signals. It can help phase-locked loop to realize fraction frequency division, theoretically without fraction spurious problem, and at the same time, the phase-locked loop loop bandwidth can be close to or even exceed the resolution frequency of the phase-locked loop.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of digital fractional divider, and particularly relates to a pulse width fractional adjustment operator. BACKGROUND

[0002] Traditional digital fractional divider circuits all have fractional spur problems, and in order to eliminate the fractional spur, the system bandwidth must be reduced, causing the dynamic characteristics to be poor. SUMMARY

[0003] In order to make up for the blank and deficiency of the prior art, the application aims to provide a pulse width fractional adjustment operator. The pulse width fractional adjustment operator can help a phase-locked loop to realize fractional division, theoretically without fractional spur problems, and at the same time, the phase-locked loop loop bandwidth can be close to or even exceed the resolution frequency of the phase-locked loop.

[0004] The application solves the technical problems by adopting the technical scheme that:

[0005] The pulse width fractional adjustment operator comprises a pulse width fractional adjuster, a state controller, an integer divider and a pulse width operator which are connected.

[0006] The input signals comprise a fractional clock signal, a reference clock signal, integer division values N1 and N2 and a fractional division value F, and the output signals comprise comparison results UP and DW signals.

[0007] The fractional clock signal is input into a CKIN port of the pulse width fractional adjuster, a CLK port of the state controller and a CKI port of the integer divider respectively.

[0008] The reference clock signal is input into an IN1 port of the state controller and a CKB2 port of the pulse width operator respectively.

[0009] The integer division value N1 is input into an N port of the pulse width fractional adjuster.

[0010] The integer division value N2 is input into an N port of the integer divider.

[0011] The fractional division value F is input into an F port of the pulse width fractional adjuster.

[0012] SOA and SOB ports of the pulse width fractional adjuster are connected to CKA1 and CKB1 ports of the pulse width operator respectively.

[0013] ST1 ports of the state controller are connected to an ST port of the pulse width fractional adjuster, an ST1 port of the pulse width operator and an ST port of the integer divider respectively, and an ST2 port is connected to an ST2 port of the pulse width operator.

[0014] The CKO port of the integer frequency divider is connected to the IN2 port of the state controller and the CKA2 port of the pulse width operator respectively;

[0015] The QA and QB ports of the pulse width operator are used to output the comparison results UP and DW signals respectively, and are connected to the UP and DW ports of the state controller respectively.

[0016] Further, the pulse width fraction regulator is composed of a sequential clock generator, a time constant generating circuit, a time constant variable time register 1 and a time constant variable time register 2 connected in sequence; the input end of the pulse width fraction regulator includes a clock signal CKIN, a state signal ST, a frequency division value N and F; and the output end includes a pulse width regulation result SOA and SOB.

[0017] Further, the pulse width operator is composed of a time register 1 and a time register 2 connected in sequence; the input end of the pulse width operator includes state signals ST1 and ST2, comparison signals CKA1, CKA2, CKB1 and CKB2; and the output end includes comparison result outputs QA and QB.

[0018] Further, the working process is as follows:

[0019] The state controller detects the pulse on the frequency division clock signal and cyclically generates pulse signals STATE1 and STATE2 on the ST1 and ST2 output ports respectively;

[0020] The state controller cyclically performs operations in the following order:

[0021] 1) After the circuit is started, when the reference clock signal is at an invalid level and the state controller detects that the frequency division clock signal has an effective edge change, a single pulse signal STATE1 is generated on the ST1 port;

[0022] 2) When the reference clock signal and the PWC are at an invalid level and the frequency division clock signal has an effective edge change is detected, the STATE2 signal on the ST2 port is set to an effective level;

[0023] 3) When the state controller detects that the UP and DW signals are both at an effective level and the frequency division clock signal has an effective edge change, the STATE2 signal output by the ST2 port is inverted to an invalid level, a single pulse signal STATE1 is generated on the ST1 port, and the process jumps to 2);

[0024] When the STATE1 is at an effective level, the pulse width fraction regulator is reset; when the pulse width fraction regulator detects that the STATE1 is at an invalid level, a single pulse PWA and PWB are output on the SOA and SOB respectively according to the input frequency division values N1 and F; the phase difference between the effective edges of the two pulses is (N1-1+F / 2M ) x T, where M is a preset number of binary bits, T is a period of a divided clock signal, F has a value range of 0 to 2 M , N1 is a positive integer;

[0025] When STATE1 is a valid level, the integer frequency divider is reset; when the integer frequency divider detects that STATE1 is an invalid level, a single pulse signal PWC is output on a port CKO thereof according to an input value N2, a pulse width of the pulse signal PWC is N2 x T, where T is a clock period of a divided clock signal, and N2 is a natural number;

[0026] The pulse signals PWA, PWB and PWC and the reference clock signal are input to ports CKA1, CKB1, CKA2 and CKB2 of the pulse width operator respectively; the signals STATE1 and STATE2 are input to ports ST1 and ST2 of the pulse width operator respectively;

[0027] When STATE1 is a valid level, the pulse width operator is reset; let TA1, TA2, TB1 and TB2 be pulse widths of input signals of the ports CKA1, CKA2, CKB1 and CKB2 respectively; let TA = TA1 + TA2 be a parameter TA and TB = TB1 + TB2 be a parameter TB; when STATE2 is a valid level, the pulse width operator performs a pulse width operation and generates single pulse signals UP and DW on output ports QA and QB respectively and ensures a phase difference between UP and DW, that is, a time difference between valid edges of UP and DW is proportional to TA - TB.

[0028] Compared with the prior art, the pulse width fractional adjustment operator and the preferred scheme thereof can perform pulse width fractional adjustment on a clock signal and comparison, and compared with other fractional frequency dividers, the proposed circuit can help a phase-locked loop to realize fractional frequency division, theoretically without generating a fractional spur problem, and meanwhile, a loop bandwidth of the phase-locked loop can be close to or even exceed a resolution frequency of the phase-locked loop. The scheme can be widely used in applications related to pulse width fractional adjustment and comparison of a clock signal to reduce system noise and improve system response speed. BRIEF DESCRIPTION OF DRAWINGS

[0029] The application will be further described in detail below in combination with the drawings and specific embodiments:

[0030] Figure 1 FIG. 1 is a circuit structure schematic diagram of a pulse width fractional adjustment operator of an embodiment of the application;

[0031] Figure 2 FIG. 3 is a signal and principle schematic diagram related to the pulse width fractional adjustment operator of the embodiment of the application;

[0032] Figure 3 FIG. 4 is a circuit working principle schematic diagram of the pulse width fractional adjustment operator of the embodiment of the application.

[0033] Figure 4 The working principle diagram of the pulse width operator circuit of the embodiment of the present application is shown in the figure;

[0034] Figure 5 The circuit principle diagram of the preferred scheme of the pulse width decimal adjuster of the embodiment of the present application is shown in the figure;

[0035] Figure 6 The circuit principle diagram of the preferred scheme of the pulse width operator of the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0036] In order to make the features and advantages of the patent more obvious and easy to understand, the following specific examples are described in detail as follows:

[0037] It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the present application. Unless otherwise indicated, all technical and scientific terms used in the present description have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs.

[0038] It should be noted that the terms used herein are only for the purpose of describing specific embodiments, and are not intended to limit the exemplary embodiments according to the present application. As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise, and furthermore, it should be understood that when the terms "comprise" and / or "include" are used in the present description, they indicate the presence of a feature, step, operation, device, component and / or combination thereof.

[0039] The structure of the pulse width decimal adjustment operator circuit of the present application is shown in the figure, which comprises a pulse width decimal adjuster 1, a state controller 2, an integer frequency divider 3 and a pulse width operator 4 connected in series. Figure 1

[0040] The input end of the circuit of the present application comprises a frequency division clock signal, a reference clock signal, integer frequency division values N1, N2 and decimal frequency division value F, and the output end comprises comparison results UP, DW signals.

[0041] Among them, the frequency division clock signal is input to the CKIN port of the pulse width decimal adjuster, the CLK port of the state controller and the CKI port of the integer frequency divider respectively;

[0042] The reference clock signal is input to the IN1 port of the state controller and the CKB2 port of the pulse width operator respectively;

[0043] The integer frequency division value N1 is input to the N port of the pulse width decimal adjuster;

[0044] The integer frequency division value N2 is input to the N port of the integer frequency divider;

[0045] ​The decimal fraction value F is input to the F port of the pulse width decimal regulator;

[0046] The SOA and SOB ports of the pulse width decimal regulator are connected to the CKA1 and CKB1 ports of the pulse width operator respectively;

[0047] The ST1 port of the state controller is connected to the ST port of the pulse width decimal regulator, the ST1 port of the pulse width operator and the ST port of the integer divider respectively; the ST2 port is connected to the ST2 port of the pulse width operator;

[0048] The CKO port of the integer divider is connected to the IN2 port of the state controller and the CKA2 port of the pulse width operator respectively;

[0049] The QA and QB ports of the pulse width operator are used to output the comparison results UP and DW signals respectively, and are connected to the UP and DW ports of the state controller respectively.

[0050] In combination with Figure 1 and Figure 2 The working mechanism of the pulse width decimal regulation operator circuit provided by the embodiments of the present application is described as follows:

[0051] The state controller detects the pulse on the divided clock signal and cyclically generates the pulse signals STATE1 and STATE2 on the ST1 and ST2 output ports respectively;

[0052] The state controller cyclically performs operations in the following order:

[0053] 1) After the circuit is started, when the reference clock signal is invalid and the state controller detects that the divided clock signal has a valid edge change, a single pulse signal STATE1 is generated on the ST1 port;

[0054] 2) When the reference clock signal and the PWC are invalid and the divided clock signal has a valid edge change is detected, the STATE2 signal on the ST2 port is set to a valid level;

[0055] 3) When the state controller detects that the UP and DW signals are both valid and the divided clock signal has a valid edge change, the STATE2 signal output by the ST2 port is inverted to an invalid level, and a single pulse signal STATE1 is generated on the ST1 port, and the process jumps to 2).

[0056] When the STATE1 is valid, the pulse width decimal regulator is reset; when the pulse width decimal regulator detects that the STATE1 is invalid, a single pulse PWA and PWB are output on the SOA and SOB respectively according to the input divided values N1 and F; the phase difference between the valid edges of the two pulses is (N1-1+F / 2 M) x T, where M is a preset number of binary bits, T is a period of a divided clock signal, and F has a value ranging from 0 to 2 M , where N1 is a positive integer.

[0057] When STATE1 is a valid level, the integer frequency divider is reset; when the integer frequency divider detects that STATE1 is an invalid level, a single pulse signal PWC is output on a port CKO of the integer frequency divider according to an input value N2, and a pulse width of the pulse signal PWC is N2 x T, where T is a clock period of a divided clock signal, and N2 is a natural number.

[0058] The pulse signals PWA, PWB and PWC and the reference clock signal are input to ports CKA1, CKB1, CKA2 and CKB2 of the pulse width operator respectively; the signals STATE1 and STATE2 are input to ports ST1 and ST2 of the pulse width operator respectively.

[0059] When STATE1 is a valid level, the pulse width operator is reset; let TA1, TA2, TB1 and TB2 be pulse widths of the input signals of the ports CKA1, CKA2, CKB1 and CKB2 respectively; let TA=TA1+TA2 be a parameter TA, and let TB=TBl+TB2 be a parameter TB. When STATE2 is a valid level, the pulse width operator performs pulse width operation, and generates a single pulse signal UP and a single pulse signal DW on output ports QA and QB respectively, and ensures a phase difference between UP and DW, that is, a time difference between valid edges of UP and DW is proportional to (TA-TB).

[0060] For convenience of principle description, in the following embodiment, a high level of a digital signal is defined as a valid level, a low level is defined as an invalid level, and a rising edge is defined as a valid edge of the digital signal.

[0061] The working principle of the pulse width fraction regulator circuit is as follows: Figure 3 When a high level is input to the port ST, the pulse width fraction regulator is reset, and output signals of the ports SOA and SOB are reset to low levels; when a low level is input to the port ST, the pulse width fraction regulator normally works, and the output signals of the ports SOA and SOB are flipped to high levels at different times according to the input period of the signal CKIN and different values of N1 and F; when the input period of the signal CKIN is Ti, N1=ni, and F=fi, a phase difference between the output signals of the ports SOA and SOB is (ni-1+fi / 2 M ) x Ti, where ni≥1 and fi≥0.

[0062] The working principle of the pulse width operator circuit is as follows: Figure 4As shown, before each comparison, the ST1 pulse signal resets the pulse width operator, and the QA and QB port output signals are reset to low level; when ST2 is high, the pulse width operator outputs the QA and QB port output signals to high level at different times according to the different pulse widths of the input signals CKA1, CKA2, CKB1 and CKB2; when the first comparison is performed, the sum of the pulse widths of CKA1 and CKA2 (T1+T2) is less than the sum of the pulse widths of CKB1 and CKB2 (T3+T4), and the pulse phase of QA lags behind that of QB; when the second comparison is performed, the sum of the pulse widths of CKA1 and CKA2 (T5+T6) is equal to the sum of the pulse widths of CKB1 and CKB2 (T7+T8), and the pulse phases of QA and QB are the same; when the third comparison is performed, the sum of the pulse widths of CKA1 and CKA2 (T9+T10) is greater than the sum of the pulse widths of CKB1 and CKB2 (T11+T12), and the pulse phase of QA leads the pulse phase of QB.

[0063] As preferred, the present application provides an example of a pulse width fraction regulator circuit in a pulse width fraction regulator circuit, which structure is as shown in Figure 5 As shown, the pulse width fraction regulator is composed of a connected sequential clock generator, a time constant generating circuit, a time constant variable time register 1 and a time constant variable time register 2. The input end of the pulse width fraction regulator includes a clock signal CKIN, a state signal ST, a frequency division value N and F, and the output end thereof includes a pulse width regulation result SOA and SOB.

[0064] The working principle of the above-mentioned pulse width fraction regulator is as follows: when the ST_S port inputs a high level, the controller is reset, the RST_S port outputs a high level, and the RPC_S port outputs a low level; when the ST_S port inputs a low level, the controller outputs a low level at the RST_S port, outputs a high level at the CK_S port when the rising edge of the CKIN signal is detected for the first time, and outputs a low level at the CK_S port and a high level at the RPC_S port when the rising edge of the CKIN signal is detected for the second time.

[0065] The time constant generating circuit outputs time constants TO1, TO2 and TO3 at the T1, T2 and T3 ports respectively according to the input frequency division value N and F, wherein TO1=TO3=(N+F / 2 M )×TO2.

[0066] The time constant variable time register can store and read according to different time constants in the storage mode and the reading mode respectively according to the input time constants.

[0067] When the RST_PWA signal is high, the time constant variable time register 1 and the time constant variable time register 2 are reset.

[0068] When the PW signal is high, the time constant variable time register 1 stores the pulse width of the PW signal according to the time constant TOl, and the stored value is TPWxTOl, where TPW is the pulse width of the PW signal, and the time register 2 stores the pulse width of the PW signal according to the time constant TO2, and the stored value is TPWxTO2.

[0069] When the RPC_PWA signal is high, the time register 1 and the time register 2 read the stored value according to the time constant TO3, and output the SOA and SOB signals, respectively, and the phase difference between PRC_PWA and SOA is TPWxTOl / TO3, and the phase difference between PRC_PWA and SOB is TPWxTO2 / TO3.

[0070] As a preferred embodiment, the present application provides an example of a pulse width operator circuit in a pulse width fraction adjustment operator circuit, which is constructed by a time register 1 and a time register 2 connected in series, as shown in the figure. Figure 6 The input end of the pulse width operator circuit includes state signals ST1 and ST2, comparison signals CKA1, CKA2, CKB1 and CKB2, and the output end includes comparison result outputs QA and QB.

[0071] The working principle of the above-mentioned pulse width operator is as follows: when the input signal of the ST1 port is high, the time register 1 and the time register 2 are reset, and the output signals QA and QB of the time register 1 and the time register 2 are reset to low; when the input signals of the ST1 and ST2 ports are low, the time register 1 and the time register 2 enter the storage mode, the time register 1 stores the pulse width of CKA1 and CKA2, and the time register 2 stores the pulse width of CKB1 and CKB2; when the input signal of the ST1 port is low and the input signal of the ST2 port is high, the time register 1 and the time register 2 enter the reading mode, the output signals QA and QB of the time register 1 and the time register 2 are flipped to high, the phase difference between QA and ST2 is proportional to the pulse width of CKA1 and CKA2, and the phase difference between QB and ST2 is proportional to the pulse width of CKB1 and CKB2.

[0072] One or more examples described in the present application are suitable for implementation in a pulse width fraction adjustment operator, as it is considered that the example is particularly advantageous in this environment. However, it is also considered that the concept of the present application can be beneficially applied to other applications. Therefore, the above description is provided only by way of example, and is not intended to limit the true scope of the present application.

[0073] The above merely describes preferred embodiments of the present application, but is not intended to limit the present application to other forms. Any person skilled in the art can make changes or modifications to the above disclosed technical contents to obtain equivalent embodiments. However, any simple modification, equivalent change and modification made to the above embodiments without departing from the technical solution of the present application and according to the technical essence of the present application shall still fall within the protection scope of the present application.

[0074] The present application is not limited to the above preferred embodiments, and any person can derive other various forms of fractional pulse width adjustment operators under the inspiration of the present application. Any equivalent change and modification made within the scope of the present application shall fall within the scope of the present application.

Claims

1. A pulse width decimal adjustment arithmetic unit, characterized in that: include: The pulse width fractional regulator, state controller, integer frequency divider, and pulse width arithmetic unit are connected together; The input signals include a frequency divider clock signal, a reference clock signal, integer frequency divider values ​​N1 and N2, and a fractional frequency divider value F; the output signals include the comparison result UP and DW signals. Its working process is as follows: The state controller detects pulses on the frequency-divided clock signal and generates pulse signals STATE1 and STATE2 cyclically on the output ports of ST1 and ST2 respectively. The state controller performs operations sequentially and cyclically in the following order: 1) After the circuit starts, when the reference clock signal is invalid and the state controller detects a valid edge change in the frequency division clock signal, a single pulse signal STATE1 is generated on the ST1 port; 2) When the reference clock signal and PWC are invalid, and a valid edge change is detected in the frequency divider clock signal, the ST2 port sets the STATE2 signal to an active level; 3) When the state controller detects that both UP and DW signals are at valid levels and the frequency divider clock signal changes with a valid edge, the ST2 port output signal STATE2 toggles to an invalid level, and a single pulse signal STATE1 is generated on the ST1 port, jumping to step 2). When STATE1 is active, the pulse width fractional regulator resets; when the pulse width fractional regulator detects that STATE1 is inactive, it outputs single pulses PWA and PWB on SOA and SOB respectively, based on the input frequency division values ​​N1 and F; the phase difference between the active edges of the two pulses is (N1 - 1 + F / 2). M ) × T, where M is the preset number of binary bits, T is the period of the divided clock signal, and F ranges from 0 to 2. M The integer N1 is a positive integer; When STATE1 is active, the integer divider is reset; when the integer divider detects that STATE1 is inactive, it will output a single pulse signal PWC on its port CKO according to the input value N2, with a pulse width of N2×T, where T is the clock period of the divided clock signal and N2 is a natural number. The PWA, PWB, PWC pulse signals and the reference clock signal are input to the CKA1, CKB1, CKA2 and CKB2 ports of the pulse width amplifier, respectively; the STATE1 and STATE2 signals are input to the ST1 and ST2 ports of the pulse width amplifier, respectively. When STATE1 is active, the pulse width operator is reset. Let TA1, TA2, TB1, and TB2 be the pulse widths of the input signals at ports CKA1, CKA2, CKB1, and CKB2, respectively. Define parameters TA = TA1 + TA2 and TB = TB1 + TB2. When STATE2 is active, the pulse width operator performs pulse width calculation and generates single pulse signals UP and DW at the QA and QB output ports, respectively, ensuring the phase difference between UP and DW. That is, the time difference between the effective edges of UP and DW is proportional to TA - TB.

2. The pulse width decimal adjustment arithmetic unit according to claim 1, characterized in that: The frequency division clock signal is respectively input to the CKIN port of the pulse width fractional regulator, the CLK port of the state controller, and the CKI port of the integer frequency divider; The reference clock signal is input to the IN1 port of the state controller and the CKB2 port of the pulse width arithmetic unit, respectively. The integer frequency divider value N1 is input to the N port of the pulse width fractional regulator; The integer division value N2 is input to the N port of the integer frequency divider; The fractional frequency division value F is input to the F port of the fractional pulse width modulator; The SOA and SOB ports of the pulse width decimal regulator are respectively connected to the CKA1 and CKB1 ports of the pulse width arithmetic unit; The ST1 port of the state controller is connected to the ST port of the pulse width fractional regulator, the ST1 port of the pulse width arithmetic unit, and the ST port of the integer frequency divider, respectively; the ST2 port is connected to the ST2 port of the pulse width arithmetic unit. The CKO port of the integer frequency divider is connected to the IN2 port of the state controller and the CKA2 port of the pulse width arithmetic unit, respectively. The QA and QB ports of the pulse width amplifier are used to output the comparison result UP and DW signals, respectively, and are connected to the UP and DW ports of the state controller.

3. The pulse width decimal adjustment arithmetic unit according to claim 1, characterized in that: The pulse width fractional regulator consists of a sequential clock generator, a time constant generation circuit, a time constant variable time register 1, and a time constant variable time register 2 connected in series. The input terminals of the pulse width fractional regulator include a clock signal CKIN, a status signal ST, and frequency division values ​​N and F. The output terminals include pulse width adjustment results SOA and SOB.

4. The pulse width decimal adjustment arithmetic unit according to claim 1, characterized in that: The pulse width arithmetic unit consists of time register 1 and time register 2 connected together; the input terminals of the pulse width arithmetic unit include status signals ST1 and ST2, comparison signals CKA1, CKA2, CKB1, and CKB2; the output terminals include comparison result outputs QA and QB.

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