Design method of anti-interference filter for digital control circuit board under group pulse action

Abstract

The application discloses a kind of digital control circuit board anti-interference filter design methods under group pulse action, realize the accurate modeling of EFT noise to digital control circuit conduction interference coupling, and based on conduction interference coupling circuit model and failure threshold, the quantitative design of anti-interference filter is carried out.Compared with traditional method, the application provides a kind of method for establishing chip black box impedance model based on online test and vector matching method, solves the impedance model modeling problem of chip under no internal structure data, and establishes the conduction interference coupling model of digital control circuit under EFT noise, provides model basis for quantitative design;From the angle of quantitative design, the anti-interference filter design method of the application effectively improves the anti-interference level of digital control circuit.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of power electronics and electromagnetic compatibility, and particularly relates to a design method of an anti-interference filter for a digital control circuit board under the action of a group of pulses. BACKGROUND

[0002] With the rapid development of power station automation, substation automation and distribution automation, the application of power electronic control and protection devices is more and more widespread, and the requirement for their reliability is also higher and higher. In the power electronic control and protection devices, the digital control circuit board undertakes important functions such as data transmission and reception and information processing, and ensures the real-time supervision and equipment protection of the device. However, the control and protection device works in a complex electromagnetic environment and is often affected by various electromagnetic interferences. For example, the part of EFT (electrical fast transient) coupled to the digital control circuit board in a conductive manner will cause the power supply voltage for the chips such as DSP on the circuit board to fluctuate, and even cause the circuit function to fail, endanger the normal operation of the equipment, and affect the safety and stability of the entire system.

[0003] The existing research has proposed various test methods for the conducted or radiated immunity of equipment under electromagnetic pulse interference. The methods such as direct current injection and GTEM chamber are used to apply pulse interference to the equipment to evaluate its conducted or radiated immunity under electromagnetic pulse impact. However, there are few studies on the failure analysis and interference suppression of the equipment circuit under pulse interference, and there are still difficulties in the black-box impedance modeling of the internal structure of the chip on the circuit board under pulse interference.

[0004] The document [A. Dehbaoui, J. Dutertre, B. Robisson and A. Tria, "Electromagnetic Transient Faults Injection on a Hardware and a Software Implementations of AES," in Proc. Workshop on Fault Diagnosis Tolerance Cryptogr., Leuven, Belgium, Sep. 2012, pp. 7-15] analyzes the influencing factors of chip failure, injects electromagnetic pulse (EMP) on the surface of field programmable gate array (FPGA), analyzes the faults and interference coupling characteristics caused by the EMP, and proposes the local effect of the electromagnetic pulse and the important role of the time violation caused by the EMP in fault initiation. However, the research does not propose a method for evaluating the failure immunity of the overall circuit and a quantitative anti-interference design method.

[0005] The document [Z. Wang, C. Zhou, T. Liu, S. Zhao and Z. Liang, "Nonlinear Behavior Immunity Modeling of an LDO Voltage Regulator Under Conducted EMI," IEEE Trans. Electromagn.Compat., vol. 58, no. 4, pp. 1016-1024, Aug. 2016] obtains the Taylor series representing the input-output voltage relationship of the regulator chip by applying N different input amplitudes to the system and using the least square method; however, the research only obtains the mathematical expression of the input-output voltage relationship, and does not obtain the black-box impedance model of the chip.

[0006] In order to solve the circuit failure problem caused by EFT noise and realize a low-cost and effective solution, it is necessary to study the quantitative anti-interference design method of the digital control circuit. At the same time, in order to realize the quantitative design goal, it is very important to study the conduction coupling modeling method and interference suppression method of the digital control circuit board under EFT interference. SUMMARY

[0007] In view of the above, the present application provides a digital control circuit board anti-interference filter design method under group pulse action, which can improve the anti-interference performance of the digital control circuit.

[0008] A method for designing an anti-interference filter of a digital control circuit board under group pulse action, comprising the following steps:

[0009] (1) Perform EFT interference test on the power supply end of the power electronic control protection device to determine the coupling path of the conducted noise from the 5V power supply port to the 3.3V power supply port of the DSP chip on the digital control circuit board, which involves related elements including voltage regulation chip, DSP chip, circuit board loop trace, magnetic bead and Y capacitor;

[0010] (2) Establish a high-frequency impedance model of each element on the coupling path and determine the model parameters;

[0011] (3) According to the high-frequency impedance model of each element on the coupling path, establish a conducted interference coupling circuit model of the digital control circuit board under EFT conducted noise in the circuit simulation software, and then simulate the voltage signal of the DSP chip power supply port under EFT noise interference voltage based on the circuit model;

[0012] (4) Calculate the key characteristic quantity of the voltage signal of the DSP chip power supply port through EFT test, and then determine the failure threshold of the digital control circuit board according to the characteristic quantity;

[0013] (5) According to the conducted interference coupling circuit model, simulate the DSP chip power supply voltage under interference, and according to the simulation results and the failure threshold of the DSP chip power supply voltage interference signal, calculate the insertion loss required for filter design, and then design the filter according to the insertion loss.

[0014] Further, in step (2), for the voltage regulation chip, first obtain its input and output voltages using online test method, then obtain the transfer function of the input and output voltage relationship using system identification method, and then obtain the equivalent impedance function of the voltage regulation chip using load impedance, and finally establish the high-frequency impedance model of the voltage regulation chip using vector matching method and network synthesis theory.

[0015] Further, the high-frequency impedance model of the voltage regulation chip includes equivalent resistance R, equivalent inductance L, equivalent resistance R C1 ~ R C4 , equivalent capacitance C C1 ~ C C4 , equivalent resistance R L11 , R L12 , R L21 and R L22 , equivalent capacitance C L1 and C L2 , and equivalent inductance L L1 and L L2 , wherein one end of R is the 5V power supply input port, the other end of R is connected to one end of L, the other end of L is connected to R C1 ~ R C4 , equivalent capacitance C C1 ~ C C4 , equivalent resistance R L11 , R L12 , R L21 and R L22 , equivalent capacitance C L1 and C L2 , and equivalent inductance L L1 and L L2 , wherein one end of R is the 5V power supply input port, the other end of R is connected to one end of L, the other end of L is connected to RC1 one end of C C1 one end of R C1 the other end of C C1 the other end of R C2 one end of C C2 one end of R C2 the other end of C C2 the other end of R C3 one end of C C3 one end of R C3 the other end of C C3 the other end of R C4 one end of C C4 one end of R C4 the other end of C C4 the other end of L L1 one end of C L1 one end of R L21 one end of L L1 the other end of R L11 one end of C L11 the other end of R L1 the other end of R L21 one end of C L2 one end of R L2 one end of L L22 one end of R L2 the other end of L L12 one end of R L12 the other end of R L2 the other end of R L22 the other end of R

[0016] Further, in the step (2), the port impedance of the DSP chip is tested by using an impedance analyzer, a high-frequency impedance model is selected according to the impedance spectrum to represent the equivalent black-box impedance model, and the parameter values of each element in the model are obtained by using a Monte Carlo algorithm; the port impedance spectrum of the magnetic bead and the Y capacitor is also tested by using the impedance analyzer, a high-frequency impedance model is determined according to the topological structure, and the parameter values of each element in the model are obtained by using a Monte Carlo algorithm.

[0017] Further, the high-frequency impedance model of the DSP chip includes an equivalent resistance R DSP , an equivalent inductance L DSP , and an equivalent capacitance C DSP , one end of L DSP is connected to one end of C DSP and serves as a power port of the chip, and the other end of L DSP is connected to RDSP one end of R DSP the other end of C DSP the other end of R

[0018] Further, the high-frequency impedance model of the magnetic bead is formed by two identical circuit structures connected in parallel, and each circuit structure comprises an equivalent inductance L M , an equivalent capacitance C M , an equivalent resistance R M1 and an equivalent resistance R M2 , one end of L M is connected to one end of R M1 and one end of C M , and the other end of L M is connected to the other end of R M1 , the other end of C M and one end of R M2 , and the other end of R M2 is connected to the 5V power supply port of the voltage regulation chip through the loop trace of the circuit board; the high-frequency impedance model of the Y capacitor is formed by four identical RLC branches connected in parallel, and each RLC branch comprises an equivalent resistance R Y , an equivalent capacitance C Y and an equivalent inductance L Y , one end of C Y is connected to the noise source 2 through the loop trace of the circuit board, the other end of C Y is connected to one end of R Y , the other end of C Y is connected to one end of L Y , and the other end of L Y is connected to the ground E; the noise source 1 is a noise voltage source for measuring the noise voltage from the 5V power supply to the ground E in the EFT test, and the noise source 2 is a noise voltage source for measuring the noise voltage from the digital ground DGND to the ground E in the EFT test.

[0019] Further, the specific implementation of the step (4) is as follows: EFT tests are performed at different amplitudes and different frequencies, and the EFT level, the voltage signal of the DSP chip power port and the failure of the circuit board in each test are recorded, the law of the EFT interference characteristic quantity and the voltage signal waveform fluctuation and the circuit board failure is found, the Pearson correlation coefficient of each waveform characteristic quantity of the voltage signal and the circuit board failure is calculated according to the test data, and the maximum oscillation amplitude absolute value of the voltage of the DSP chip power port is determined as the key characteristic quantity with the most significant impact on failure; then, in the EFT test of different levels, when the circuit board does not fail, the maximum value of the maximum oscillation amplitude absolute value of the voltage of the DSP chip power port is taken as the failure threshold; when the amplitude of the voltage of the DSP chip power port does not exceed the threshold in the EFT test, the circuit board will not fail.

[0020] Further, the step (5) calculates the insertion loss IL required to be met by the designed filter by the following formula;

[0021] IL = 20lgU 3.3V - 20lgU threshold

[0022] Wherein: U 3.3V is the simulation result of the DSP chip power voltage under the interference, U threshold is the DSP chip power voltage under the interference signal of the failure threshold.

[0023] Further, the step (5) sets the source impedance and the load impedance as 50Ω when designing the filter, and designs the filter structure as a π-type filter and installs it at the DSP chip power port.

[0024] Compared with the prior art, the present application has the following beneficial technical effects:

[0025] 1. The present application establishes a black box model of the voltage regulating chip based on online testing and vector matching method, solves the impedance model modeling problem of the chip without internal structure data; on this basis, the present application obtains the impedance model of the DSP chip and other elements on the circuit board through online testing and algorithm fitting, establishes the EFT conducted interference coupling model of the digital control circuit board, and provides a model basis for quantitative design.

[0026] 2. The present application can quantitatively design the anti-interference filter by using the conducted interference coupling circuit model and the failure threshold of the digital control circuit under EFT noise, and can consider the EMI coupling in the product design stage, fully design, reduce the design and test time of the filter in the later stage, and reduce the development cost. DETAILED DESCRIPTION

[0027] Figure 1 It is the flowchart of the digital control circuit board anti-interference filter design method of the present application.

[0028] Figure 2 It is the EFT conducted interference coupling path diagram on the digital control circuit.

[0029] Figure 3 It is the conducted interference coupling model diagram of the digital control circuit under EFT noise.

[0030] Figure 4 It is the comparison diagram of the DSP chip power voltage result obtained by simulating the interference coupling model and the test result.

[0031] Figure 5 It is the calculation result diagram of the Pearson correlation coefficient of each waveform characteristic quantity and the circuit failure.

[0032] Figure 6 The schematic diagram of the DSP power voltage waveform measurement result corresponding to the failure threshold.

[0033] Figure 7 The schematic diagram of the spectrum comparison of the DSP chip power voltage simulation result under the 5kHz / +2.0kV level EFT interference, the DSP chip power voltage simulation result after adding the filter, and the DSP chip power voltage test result under the failure threshold.

[0034] Figure 8 The schematic diagram of the equivalent circuit of the digital control loop after inserting the filter.

[0035] Figure 9 The schematic diagram of the comparison of the DSP chip power voltage time domain waveform test result after inserting the filter and the DSP chip power voltage time domain waveform under the failure threshold. DETAILED DESCRIPTION

[0036] In order to describe the present application more specifically, the technical solutions of the present application are described in detail below in combination with the drawings and specific embodiments.

[0037] As shown in Figure 1 , the digital control circuit board anti-interference filter design method under the group pulse action of the present application specifically includes the following steps:

[0038] (1) According to the conducted noise flow on the digital control circuit board in the EFT interference test of the power supply end of the control protection device under the IEC 61000-4-4 standard, the electromagnetic noise coupling path from the circuit board 5V power supply port to the DSP chip 3.3V power supply port is determined; the coupling path includes a voltage regulation chip, a DSP chip, a PCB loop trace, and magnetic beads, capacitors and other elements, as shown in Figure 2 .

[0039] (2) The black box impedance model of the voltage regulation chip is established using online testing and vector matching method, and then the parameters of the high-frequency impedance model of the DSP chip and the magnetic beads and capacitors are extracted through impedance analyzer testing and Monte Carlo fitting algorithm, and the high-frequency impedance model parameters of the PCB loop trace are extracted using electromagnetic simulation method.

[0040] Since there is no internal structure data of the voltage regulation chip, in order to obtain the impedance model of the voltage regulation chip, it is regarded as a "black box" for research, and only the impedance frequency characteristics of its port are concerned. Under the EFT interference test condition, the waveforms of the input and output ports of the chip are measured. The waveforms of the input and output of the voltage regulation chip obtained by online testing are analyzed using the method of system identification, and the transfer function model H(s) representing the input and output relationship of the voltage regulation chip is obtained.

[0041] The online test is conducted under load, so the expression of the transfer function is calculated by taking into account the influence of the load impedance Z L , that is,

[0042]

[0043] The frequency characteristic curve of the load impedance Z L (s) is obtained by sweep frequency simulation in software, and its corresponding frequency domain expression is obtained by using an algorithm as follows:

[0044]

[0045] The impedance frequency domain expression Zs(s) of the voltage regulation chip can be calculated by substituting equation (2) into equation (1), and the partial fractions of Zs(s) and equation (3) are fitted using the vector matching method as follows:

[0046]

[0047] The equivalent circuit of the voltage regulation chip is obtained by using the circuit synthesis method according to the poles and residues of the obtained partial fractions and equation (3).

[0048] When establishing the equivalent impedance model of the DSP in the conducted interference frequency range, the impedance spectrum between the 3.3V power port and the digital ground DGND is tested, and the equivalent impedance of the DSP is represented by an inductance high-frequency model according to the tested impedance spectrum, and the parameters of each part are fitted using the Monte Carlo algorithm.

[0049] Sweep frequency simulation is performed using software to extract the parasitic parameters of the loop trace on the PCB board. In addition, the impedance spectrum of the Y capacitor and the magnetic bead is tested, and the impedance model parameters are also fitted using the Monte Carlo algorithm.

[0050] (3) The conducted interference coupling circuit model of the digital control circuit under EFT conducted noise is established in the circuit simulation software, and the voltage waveform signal of the DSP chip power port under EFT noise interference voltage is simulated based on the circuit model.

[0051] All the impedance models are integrated to obtain the overall model of the interference coupling path of the conducted noise from the 5V port of the digital control circuit board to the 3.3V power port of the DSP chip in the EFT test as shown in Figure 3 . The overall model is built in the circuit simulation software and the parameters are set, the voltage data of the 5V input end of the digital control circuit in the 1.5kV level EFT interference test is imported into the model for simulation, and the output waveform of the 3.3V end of the DSP chip obtained by simulation and the test waveform are as shown in Figure 4 . It can be seen that the simulation results are consistent with the test results.

[0052] (4) Perform EFT tests at different amplitudes and frequencies, and record the EFT level, DSP chip power port voltage waveform and circuit failure of each test; use the method of correlation analysis to analyze the EFT test results, find the key waveform characteristic quantity that causes the digital control circuit to fail; according to the key waveform characteristic quantity and the measurement results obtained by the test and analysis, the failure threshold of the digital control circuit is obtained.

[0053] According to the EFT interference test results at different amplitudes and frequencies, it is found that in the same voltage level interference test, the circuit fails when the pulse group frequency is reduced to a certain value; in the test with the same pulse group frequency, the circuit fails when the interference test voltage amplitude is increased to a certain value; in these test cases, when the pulse group frequency is reduced or the amplitude is increased, the absolute value of the maximum oscillation amplitude of the DSP chip power voltage increases.

[0054] In order to further clarify the influencing factors of failure, the influence degree of the waveform characteristic quantity of the single interference waveform of the power voltage of the DSP chip on the failure is analyzed. The method of correlation analysis is used in the present application, and the highest peak amplitude, the highest peak oscillation duration, the lowest valley amplitude, the lowest valley oscillation duration, the maximum oscillation amplitude absolute value, the maximum oscillation amplitude absolute value corresponding to the oscillation duration, the average value, the oscillation times, and the total oscillation duration of the single interference waveform of the power voltage are used as the waveform characteristic quantity. The Pearson correlation coefficient p Xi,Y , X i represents each waveform characteristic quantity, Y represents the circuit failure result, and when the coefficient absolute value is close to 1, it proves that there is a strong linear correlation between X i and Y.

[0055]

[0056] The calculation result is shown in Figure 5 The Pearson correlation coefficient between the maximum oscillation amplitude absolute value of the power voltage waveform and the digital control circuit failure is -0.587, which is the most significant characteristic quantity related to the circuit failure. The highest peak amplitude and the lowest valley amplitude also show a strong correlation with the circuit failure. The maximum oscillation amplitude absolute value is the absolute value of the larger value of the two, without considering the influence of polarity, and according to the calculation result, the correlation coefficient between the maximum oscillation amplitude absolute value and the circuit failure is obviously greater than the correlation coefficients between the two and the circuit failure, which proves that the maximum oscillation amplitude absolute value is the main reason for the failure of the digital control circuit. According to the above results, it is concluded that the relationship between the maximum oscillation amplitude absolute value and the circuit failure is: when the maximum oscillation amplitude absolute value of the chip power voltage increases and exceeds a certain threshold, the circuit fails.

[0057] According to the measurement and analysis results, the application adopts a maximum oscillation amplitude of a chip power voltage, referred to as MAPV, to predict a circuit state. The maximum value in the MAPV value is taken as a failure threshold when the circuit does not fail under different test conditions. According to the test results, the MAPV value of the chip under the IEC61000-4-4 standard EFT test at a +1.0kV voltage level and a pulse group frequency of 5kHz is 11V, as shown in Figure 6 . When the amplitude of the DSP chip power voltage is below 11V, the digital control circuit does not fail in the IEC61000-4-4 standard EFT interference test.

[0058] (5) The chip power voltage under the interference is simulated by using the interference coupling circuit model obtained above, the chip power voltage simulation result is subtracted from the frequency spectrum amplitude of the chip power voltage under the failure threshold, and an insertion loss required for designing a filter is obtained, and then the filter is quantitatively designed according to the insertion loss.

[0059] The control protection device used in the embodiment fails to pass the EFT test at 5kHz / +2.0kV, and therefore an anti-interference filter needs to be designed so that the device can withstand the interference at the level of 5kHz / +2.0kV in the IEC standard EFT test after the filter is installed. First, the voltage waveform data at the 5V port of the digital control circuit board under the EFT interference test at the level of 5kHz / +2.0kV is imported into the interference coupling model, and the voltage waveform data at the 3.3V power port of the DSP chip is obtained through simulation; then, the insertion loss required for designing the filter is obtained by subtracting the chip power voltage simulation result from the frequency spectrum amplitude of the chip power voltage under the failure threshold.

[0060]

[0061] wherein: U 3.3V_5kHz / 2kV represents the chip power voltage under the interference obtained through simulation, U threshold is the DSP chip power voltage interference signal under the failure threshold.

[0062] The filter placement position is located in front of the chip power port. In designing the filter, in order to ensure that the required loss value is reached and the designed filter is small enough to be installed on the circuit board and put into the case, according to Figure 7 , the designed filter needs to reach an insertion loss value of 45dB at a frequency of 18MHz. In designing the filter, it is assumed that the source impedance and the load impedance are 50Ω, and the selected filter structure is a π-type filter, as shown in Figure 8As shown, the final design of the filter element value is L = 1.5 μH, C = 2.286 nF. Finally, simulation and test verification, the chip power supply voltage spectrum under the failure threshold and the chip power supply voltage spectrum after adding the filter are simulated as shown in Figure 7 As shown, it can be seen that after adding the filter, the spectrum amplitude of the DSP chip power supply port voltage is reduced to below the spectrum amplitude of the voltage waveform under the failure threshold, and the designed filter meets the design index. The filter is assembled, installed on the digital control circuit board of the control protection device, and then the 5 kHz / +2.0 kV level EFT interference test is performed, at this time the device can successfully pass the interference test; Figure 9 For the DSP power supply voltage waveform in the interference test, it can be seen that after adding the filter, the power supply voltage amplitude under the 5 kHz / +2.0 kV level EFT interference test is below the failure threshold, which proves that when the DSP chip power supply voltage is below the failure threshold, the circuit will not fail, and at the same time verifies the quantitative design method of the filter of the present application.

[0063] The above description of the embodiments is for the purpose of facilitating the understanding and application of the present application by those skilled in the art. Those skilled in the art can obviously make various modifications to the above embodiments, and apply the general principles described herein to other embodiments without having to go through creative labor. Therefore, the present application is not limited to the above embodiments, and the improvements and modifications made by those skilled in the art to the present application according to the disclosure of the present application should be within the scope of protection of the present application.

Claims

1. A method for designing an anti-interference filter of a digital control circuit board under group pulse action, comprising the following steps: (1) performing an EFT interference test on a power supply end of a power electronic control protection device to determine a coupling path of conducted noise from a 5V power supply port to a 3.3V power supply port of a DSP chip on the digital control circuit board, the coupling path involving related elements including a voltage regulating chip, the DSP chip, a circuit board loop trace, a magnetic bead and a Y capacitor; (2) establishing a high-frequency impedance model of each element on the coupling path and determining model parameters, specifically: using an online test and a vector matching method to establish a black-box impedance model of the voltage regulating chip, and then extracting high-frequency impedance model parameters of the DSP chip, the magnetic bead and the Y capacitor through impedance analyzer testing and a Monte Carlo fitting algorithm, and extracting high-frequency impedance model parameters of the circuit board loop trace by using an electromagnetic simulation method; (3) establishing a conducted interference coupling circuit model of the digital control circuit board under EFT conducted noise in a circuit simulation software according to the high-frequency impedance model of each element on the coupling path, and then simulating a voltage signal of the power supply port of the DSP chip under an EFT noise interference voltage based on the circuit model; (4) calculating key characteristic quantities of the voltage signal of the power supply port of the DSP chip through the EFT test, and then determining a failure threshold of the digital control circuit board according to the characteristic quantities; (5) simulating a DSP chip power supply voltage under interference according to the conducted interference coupling circuit model, calculating an insertion loss required to be satisfied for filter design according to the simulation result and the DSP chip power supply voltage interference signal at the failure threshold, and then quantitatively designing a filter according to the insertion loss.

2. The method of designing a digital control circuit board anti-jamming filter according to claim 1, wherein: In the step (2), for the voltage regulating chip, first, an input and output voltage of the voltage regulating chip is obtained by using an online test method, then a transfer function of the input and output voltage relationship is obtained by using a system identification method, and then an equivalent impedance function of the voltage regulating chip is obtained by using a load impedance, and finally a high-frequency impedance model of the voltage regulating chip is established by using a vector matching method and network synthesis theory.

3. The method of designing a digital control circuit board anti-jamming filter according to claim 2, wherein: The high-frequency impedance model of the voltage regulation chip comprises equivalent resistance R, equivalent inductance L, equivalent resistance R C1 ~R C4 , equivalent capacitance C C1 ~C C4 , equivalent resistance R L11 , R L12 , R L21 and R L22 , equivalent capacitance C L1 and C L2 , and equivalent inductance L L1 and L L2 , wherein one end of R is a 5V power input port, the other end of R is connected with one end of L, the other end of L is connected with one end of R C1 and one end of C C1 , the other end of R C1 is connected with the other end of C C1 , one end of R C2 and one end of C C2 , the other end of R C2 is connected with the other end of C C2 , one end of R C3 and one end of C C3 , the other end of R C3 is connected with the other end of C C3 , one end of R C4 and one end of C C4 , the other end of R C4 is connected with the other end of C C4 , one end of L L1 , one end of C L1 and one end of R L21 , the other end of L L1 is connected with one end of R L11 , the other end of R L11 is connected with the other end of C L1 , the other end of R L21 , one end of L L2 , one end of C L2 and one end of R L22 , the other end of L L2 is connected with one end of R L12 , the other end of R L12 is connected with the other end of C L2 and the other end of R L22 , and serves as a 3.3V power output port to supply power to a DSP chip through a circuit board loop trace.

4. The method of designing a digital control circuit board anti-jamming filter according to claim 1, wherein: In the step (2), for the DSP chip, a port impedance of the DSP chip is tested by using an impedance analyzer, a high-frequency impedance model is selected according to an impedance spectrum to represent an equivalent black-box impedance model, and parameter values of each element in the model are obtained by using a Monte Carlo algorithm; for the magnetic bead and the Y capacitor, a port impedance spectrum is tested by using an impedance analyzer, a high-frequency impedance model is determined according to a topological structure, and parameter values of each element in the model are obtained by using a Monte Carlo algorithm.

5. The method of designing a digital control circuit board anti-jamming filter according to claim 4, wherein: The high-frequency impedance model of the DSP chip comprises an equivalent resistance R DSP , an equivalent inductance L DSP , and an equivalent capacitance C DSP , one end of L DSP is connected with one end of C DSP and serves as a power port of the chip, the other end of L DSP is connected with one end of R DSP , the other end of R DSP is connected with the other end of C DSP and is connected with a digital ground DGND.

6. The method of designing a digital control circuit board anti-jamming filter according to claim 4, wherein: The high-frequency impedance model of the magnetic beads is formed by two same circuit structures in parallel, the circuit structure includes equivalent inductance L M , equivalent capacitance C M , equivalent resistance R M1 and equivalent resistance R M2 , one end of L M is connected with one end of R M1 and one end of C M and is connected with noise source 1, the other end of L M is connected with the other end of R M1 , the other end of C M and one end of R M2 , the other end of R M2 is connected with the voltage regulating chip 5V power port through the circuit board loop trace; the high-frequency impedance model of the Y capacitor is formed by four same RLC branches in parallel, each RLC branch includes equivalent resistance R Y , equivalent capacitance C Y and equivalent inductance L Y , one end of C Y is connected with noise source 2 through the circuit board loop trace, the other end of C Y is connected with one end of R Y , the other end of C Y is connected with one end of L Y , the other end of L Y is connected with the ground E; the noise source 1 is the noise voltage source for measuring 5V power to the ground E in the EFT test, and the noise source 2 is the noise voltage source for measuring digital ground DGND to the ground E in the EFT test.

7. The method of designing a digital controlled circuit board anti-jamming filter of claim 1, wherein: The specific implementation of the step (4) is: performing EFT tests at different amplitudes and different frequencies, and recording the EFT level, the voltage signal of the power port of the DSP chip and the failure of the circuit board in each test; after discovering the EFT interference characteristic quantity and the law of the voltage signal waveform floating and the circuit board failure, calculating the Pearson correlation coefficient of each waveform characteristic quantity of the voltage signal and the circuit board failure according to the test data, and determining that the absolute value of the maximum oscillation amplitude of the voltage of the power port of the DSP chip is the key characteristic quantity with the most significant impact on the failure; then, in the EFT tests at different levels, when the circuit board does not fail, taking the maximum value of the absolute value of the maximum oscillation amplitude of the voltage of the power port of the DSP chip as the failure threshold; when the amplitude of the voltage of the power port of the DSP chip does not exceed the threshold in the EFT test, the circuit board will not fail.

8. The method of designing a digitally controlled circuit board anti-jam filter according to claim 1, wherein: In the step (5), the insertion loss IL required to be met by the designed filter is calculated by the following formula: IL = 20 lg U 3.3V - 20 lg U threshold Where: U 3.3V is the power supply voltage of the DSP chip under interference obtained by simulation threshold is the interference signal of the power supply voltage of the DSP chip under failure threshold.

9. The method of designing a digitally controlled circuit board anti-jam filter according to claim 1, wherein: In the step (5), when designing the filter, the source impedance and the load impedance are set to 50Ω, the filter structure is designed to be a π-type filter, and the filter is installed at the power port of the DSP chip.

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