Pulse generator, error checking and clearing circuit, and memory

Abstract

Embodiments of the present disclosure provide a pulse generator, an error checking and clearing circuit, and a memory. The pulse generator includes: a delay module configured to receive an ECS command signal, perform a delay process on the ECS command signal, and output a delayed command signal; wherein, the delay between the ECS command signal and the delayed command signal is a first preset value; a latching module configured to receive the ECS command signal and the delayed command signal, perform a latching process based on the ECS command signal and the delayed command signal, and output an ECS pulse signal; wherein, there are multiple values for the pulse width of the ECS command signal, and the pulse width of the ECS pulse signal is the first preset value. In this way, the pulse width of the ECS pulse signal is always the first preset value and is not affected by the pulse width of the ECS command signal, that is, the pulse generator can generate an ECS pulse signal with a stable pulse width, avoid errors in the ECS mode, and ultimately improve the performance of the memory.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor memories, and in particular, to a pulse generator, an error check and correction circuit, and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) has an Error Check and Scrub (ECS) mode. The ECS mode allows the internal reading and modification of detected error codewords in the DRAM while recording the error count. In the ECS mode, an ECS command signal can be generated by means of a multi-purpose command MPC, a self-refresh command Self_Refresh, or a refresh command Refresh, and then a stable ECS pulse signal is generated by using the ECS command signal to complete the internal activation, read / write, and precharge operation commands. Currently, in different working scenarios, the pulse width of the ECS command signal varies greatly, resulting in an unstable pulse width of the ECS pulse signal, and errors may occur in the ECS mode, affecting the performance of the memory. Summary of the Invention

[0003] The present disclosure provides a pulse generator, an error check and correction circuit, and a memory. The pulse generator can generate an ECS pulse signal with a stable pulse width, avoiding errors in the ECS mode.

[0004] The technical solution of the present disclosure is implemented as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a pulse generator, which includes:

[0006] A delay module configured to receive an ECS command signal, perform a delay process on the ECS command signal, and output a delayed command signal; wherein, the delay between the ECS command signal and the delayed command signal is a first preset value;

[0007] A latch module configured to receive the ECS command signal and the delayed command signal, perform a latch process based on the ECS command signal and the delayed command signal, and output an ECS pulse signal;

[0008] Wherein, the pulse width of the ECS command signal has multiple values, and the pulse width of the ECS pulse signal is the first preset value.

[0009] In some embodiments, the initial values of the ECS command signal and the ECS pulse signal are both the first level value; the latching module is specifically configured to control the ECS pulse signal to change from the first level value to the second level value when the ECS command signal changes from the first level value to the second level value; and to control the ECS pulse signal to change from the second level value to the first level value when the delay command signal changes from the first level value to the second level value..

[0010] In some embodiments, the latching module is further configured to receive a reset signal; and based on the reset signal, control the initial state of the ECS pulse signal to be the first level value.

[0011] In some embodiments, the latching module includes a first NOR gate and a second NOR gate; wherein, the first input terminal of the first NOR gate receives the ECS command signal, and the second input terminal of the first NOR gate is connected to the output terminal of the second NOR gate; the first input terminal of the second NOR gate is connected to the output terminal of the first NOR gate, the second input terminal of the second NOR gate receives the delay command signal, and the third input terminal of the second NOR gate receives the reset signal; correspondingly, the output terminal of the second NOR gate is used to output the ECS pulse signal.

[0012] In some embodiments, the latching module further includes a first inverter and a second inverter; wherein, the input terminal of the first inverter is connected to the output terminal of the second NOR gate, and the input terminal of the second inverter is connected to the output terminal of the first inverter; correspondingly, the output terminal of the second inverter is used to output the ECS pulse signal.

[0013] In some embodiments, the delay module includes a first delay unit and an adjustment unit; wherein, the first delay unit is configured to receive the ECS command signal and output an intermediate delay signal; wherein, the delay value between the ECS command signal and the intermediate delay signal is less than the first preset value; the adjustment unit is configured to receive an adjustment parameter and the intermediate delay signal, and perform a delay process on the intermediate delay signal based on the adjustment parameter to output the delay command signal.

[0014] In some embodiments, the delay module includes an adjustment unit; wherein, the adjustment unit is configured to receive an adjustment parameter and perform a delay process on the ECS command signal based on the adjustment parameter to output the delay command signal.

[0015] In some embodiments, the adjustment parameter includes an N-bit adjustment sub-signal, the adjustment unit includes N delay sub-modules arranged in series, the input end of the first delay sub-module forms the input end of the adjustment unit, the input end of the (i + 1)-th delay sub-module is connected to the output end of the i-th delay sub-module, and the output end of the N-th delay sub-module forms the output end of the adjustment unit; specifically, the adjustment unit is configured to, when the i-th adjustment sub-signal belongs to an upward adjustment parameter, if the i-th adjustment sub-signal is in the first state, control the i-th delay sub-module to perform a delay transmission process on the input signal; if the i-th adjustment sub-signal is in the second state, control the i-th delay sub-module to perform a direct transmission process on the input signal; or, when the i-th adjustment sub-signal belongs to a downward adjustment parameter, if the i-th adjustment sub-signal is in the first state, control the i-th delay sub-module to perform a direct transmission process on the input signal; if the i-th adjustment sub-signal is in the second state, control the i-th delay sub-module to perform a delay transmission process on the input signal; where both i and N are positive integers, and i is less than or equal to N.

[0016] In some embodiments, each of the delay sub-modules includes a first path and a second path, a second delay unit is provided on the first path, and the second delay unit is configured to cause the input signal to have a second preset value of delay; where the second preset value is less than the first preset value; the i-th delay sub-module is configured to receive an input signal, the i-th adjustment sub-signal, and an inverted signal of the i-th adjustment sub-signal; and based on the level state of the i-th adjustment sub-signal, perform a delay transmission process on the input signal through the first path, or perform a direct transmission process on the input signal through the second path.

[0017] In some embodiments, when the i-th adjustment sub-signal belongs to an upward adjustment parameter, the i-th delay sub-module further includes a first NAND gate, a second NAND gate, and a third NAND gate; where the first input end of the first NAND gate is connected to the inverted signal of the i-th adjustment sub-signal; the second input end of the first NAND gate receives the input signal of the i-th delay sub-module, the output end of the first NAND gate is connected to the first input end of the third NAND gate, and the output end of the third NAND gate outputs the output signal of the i-th delay sub-module to form the second path; the first input end of the second NAND gate is connected to the i-th adjustment sub-signal; the second input end of the second NAND gate receives the input signal of the i-th delay sub-module, the output end of the second NAND gate is connected to the input end of the second delay unit, the output end of the second delay unit is connected to the second input end of the third NAND gate, and the output end of the third NAND gate outputs the output signal of the i-th delay sub-module to form the first path.

[0018] In some embodiments, when the i-th adjustment sub-signal belongs to a down-regulation parameter, the i-th delay sub-module further includes a first NAND gate, a second NAND gate, and a third NAND gate; wherein, a first input terminal of the first NAND gate is connected to an inverted signal of the i-th adjustment sub-signal; a second input terminal of the first NAND gate receives an input signal of the i-th delay sub-module, an output terminal of the first NAND gate is connected to an input terminal of the second delay unit, an output terminal of the second delay unit is connected to a second input terminal of the third NAND gate, and an output terminal of the third NAND gate outputs an output signal of the i-th delay sub-module to form the first path; a first input terminal of the second NAND gate is connected to the i-th adjustment sub-signal, a second input terminal of the second NAND gate receives an input signal of the i-th delay sub-module, an output terminal of the second NAND gate is connected to a first input terminal of the third NAND gate, and an output terminal of the third NAND gate outputs an output signal of the i-th delay sub-module to form the second path.

[0019] In some embodiments, the pulse generator is applied to a memory; wherein, the N-bit adjustment sub-signal is set via an external command in a test mode of the memory; or, the N-bit adjustment sub-signal is determined based on temperature decoding of the memory; or, a part of the N-bit adjustment sub-signal is set via an external command in a test mode of the memory, and the remaining part of the N-bit adjustment sub-signal is determined based on temperature decoding of the memory.

[0020] In a second aspect, an embodiment of the present disclosure provides an error checking and correcting circuit, which includes a command generation module and the pulse generator as described in the first aspect; wherein,

[0021] The command generation module is configured to receive a multi-purpose instruction sent externally in a first operating mode, and output an ECS command signal based on the multi-purpose instruction; wherein, a pulse width of the ECS command signal is associated with a pulse width of the multi-purpose instruction, and there are multiple values for the pulse width of the multi-purpose instruction;

[0022] The pulse generator is configured to output an ECS pulse signal based on the ECS command signal, and a pulse width of the ECS pulse signal is a first preset value.

[0023] In some embodiments, the command generation module is configured to output the ECS command signal based on a refresh instruction or a self-refresh instruction in a second operating mode.

[0024] In a third aspect, an embodiment of the present disclosure provides a memory, which at least includes the error checking and correcting circuit as described in the second aspect.

[0025] Embodiments of the present disclosure provide a pulse generator, an error checking and clearing circuit, and a memory. The pulse generator includes: a delay module configured to receive an ECS command signal, perform a delay process on the ECS command signal, and output a delayed command signal; wherein, the delay between the ECS command signal and the delayed command signal is a first preset value; a latching module configured to receive the ECS command signal and the delayed command signal, perform a latching process based on the ECS command signal and the delayed command signal, and output an ECS pulse signal; wherein, there are multiple values for the pulse width of the ECS command signal, and the pulse width of the ECS pulse signal is the first preset value. In this way, the pulse width of the ECS pulse signal depends on the delay value between the ECS command signal and the delayed command signal, that is, the pulse width of the ECS pulse signal is only determined by the delay process of the delay module on the ECS command signal, and is not affected by the pulse width of the ECS command signal. Therefore, the pulse generator can generate an ECS pulse signal with a stable pulse width, avoid errors in the ECS mode, and ultimately improve the performance of the memory. Description of the Drawings

[0026] Figure 1 It is a schematic structural diagram of an ECS circuit;

[0027] Figure 2 It is a schematic structural diagram of a pulse generator;

[0028] Figure 3 It is a schematic signal timing diagram;

[0029] Figure 4 It is a schematic structural diagram of a pulse generator provided by an embodiment of the present disclosure;

[0030] Figure 5 It is a schematic signal timing diagram provided by an embodiment of the present disclosure;

[0031] Figure 6 It is a schematic structural diagram of a latching module provided by an embodiment of the present disclosure Figure 1 ;

[0032] Figure 7 It is a schematic structural diagram of a latching module provided by an embodiment of the present disclosure Figure 2 ;

[0033] Figure 8 It is a schematic structural diagram of another pulse generator provided by an embodiment of the present disclosure;

[0034] Figure 9 It is a schematic structural diagram of yet another pulse generator provided by an embodiment of the present disclosure;

[0035] Figure 10Structural schematic diagram of an adjustment unit provided by an embodiment of the present disclosure;

[0036] Figure 11 Structural schematic diagram of an error checking and clearing circuit provided by an embodiment of the present disclosure;

[0037] Figure 12 Structural schematic diagram of the composition of a memory provided by an embodiment of the present disclosure. Detailed implementation manners

[0038] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the related application, rather than limiting the application. Additionally, it should be noted that for the sake of description, only parts related to the related application are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict. It should be pointed out that the terms "first / second / third" related to the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0039] Dynamic Random Access Memory (DRAM)

[0040] Synchronous Dynamic Random Access Memory (SDRAM)

[0041] Double Data Rate SDRAM (DDR)

[0042] 5th generation DDR standard (DDR5 Specification, DDR5 SPEC)

[0043] Taking DDR5 DRAM as an example, the ECS mode can be divided into an automatic ECS operation mode and a manual ECS operation mode. In the manual ECS operation mode, an ECS command signal is generated by using a multi-purpose command MPC sent by a memory controller (Controller); in the automatic ECS operation mode, a refresh command or a self-refresh command is used to generate the ECS command signal. After the ECS command signal, activation, read / write, and precharge operations need to be performed. Refer to Figure 1 which shows a schematic structural diagram of an ECS circuit. As Figure 1 shown, the ECS circuit at least includes a command generation module and a pulse generator. As Figure 1 shown, in the manual ECS operation mode, the command generation module receives the multi-purpose command MPC from the memory controller (Controller), and a specific multi-purpose command MPC can generate an ECS command signal ECS_CMD; however, in the automatic ECS operation mode, there is no multi-purpose command MPC at this time, so the command generation module steals a refresh command Refresh or a self-refresh command Self_Refresh to generate the ECS command signal ECS_CMD. Then, the pulse generator generates a stable ECS pulse signal ECS_Pulse by using the ECS command signal ECS_CMD, and the ECS pulse signal ECS_Pulse is used for internal activation, read / write, and precharge operations.

[0044] For a memory, the pulse width of the required ECS pulse signal ECS_Pulse is approximately 2 ns. Refer to Figure 2 which shows a schematic structural diagram of a pulse generator. As Figure 2 shown, the pulse generator includes two inverters, a NAND gate, and a delay unit, and the delay unit fixedly generates a delay of 2 nanoseconds (ns). That is to say, the inverted signal of the delay command signal ECS_Delay generates a delayed command signal ECS_Delay after a delay of 2 ns, and the delayed command signal ECS_Delay and the delayed command signal ECS_Delay are AND-operated to generate the ECS pulse signal ECS_Pulse. In the automatic ECS operation mode, the pulse width of the stolen self-refresh command Self_Refresh is approximately 2.5 ns, and the pulse width of the ECS command signal ECS_CMD generated by this pulse meets the requirements. In the manual ECS operation mode, when the ECS command signal ECS_CMD is generated by the multi-purpose command MPC, the pulse width of the multi-purpose command MPC sent by the external Controller can be 1 clock cycle (tCK) or multiple tCKs. That is to say, for Figure 2For the pulse generator shown, in the manual ECS operation mode, if the external operating frequency is high and the multi-purpose command MPC only includes 1 tCK, the pulse width of the generated ECS command signal ECS_CMD is small, and at this time, the required ECS pulse signal ECS_Pulse cannot be generated.

[0045] Taking the operating frequency of 3200 million bits per second (Mbps) and the pulse widths of the multi-purpose command MPC being 1 tCK and 5 tCK as examples, the variation of the ECS pulse signal ECS_Pulse will be described. Refer to Figure 3 , which shows a signal timing schematic diagram. As Figure 3 shown in (a) of, when the pulse width of the multi-purpose command MPC is 5 tCK, the pulse width of the ECS command signal ECS_CMD is approximately 3.125 ns, the delay between the delay command signal ECS_Delay and the ECS command signal ECS_CMD is 2 ns, and the falling edge of the ECS pulse signal ECS_Pulse is generated by the falling edge of the delay command signal ECS_Delay. Therefore, the pulse width of the ECS pulse signal ECS_Pulse is also 2 ns; as Figure 3 shown in (b) of, when the pulse width of the multi-purpose command MPC is 1 tCK, the pulse width of the ECS command signal ECS_CMD is approximately 0.625 ns, the delay between the delay command signal ECS_Delay and the ECS command signal ECS_CMD is 2 ns, and the falling edge of the ECS pulse signal ECS_Pulse is generated by the falling edge of the ECS command signal ECS_CMD. Therefore, the pulse width of the ECS pulse signal ECS_Pulse is 0.625 ns, which cannot meet the requirements.

[0046] In short, in the manual ECS operation mode, the ECS command needs to be generated through the multi-purpose command MPC, and then the ECS pulse signal ECS_Pulse is generated. Since the pulse width of the multi-purpose command MPC can be 1 tCK or multiple tCKs, when using Figure 2 the shown pulse generator to generate the ECS pulse signal ECS_Pulse, if the external operating frequency changes, the pulse width of the corresponding ECS command signal will also change. If the external operating frequency is high, the required ECS pulse signal ECS_Pulse cannot be generated. Therefore, a stable automatic pulse generator is needed to generate an ECS pulse signal ECS_Pulse with a pulse width of approximately 2 ns to solve the problems encountered in the ECS mode.

[0047] Based on this, embodiments of the present disclosure provide a pulse generator, which includes: a delay module configured to receive an ECS command signal, perform delay processing on the ECS command signal, and output a delayed command signal; wherein, the delay between the ECS command signal and the delayed command signal is a first preset value; a latching module configured to receive the ECS command signal and the delayed command signal, perform latching processing based on the ECS command signal and the delayed command signal, and output an ECS pulse signal; wherein, the pulse width of the ECS command signal has multiple values, and the pulse width of the ECS pulse signal is the first preset value. In this way, the pulse width of the ECS pulse signal depends on the delay value between the ECS command signal and the delayed command signal, that is, the pulse width of the ECS pulse signal is only determined by the delay processing of the ECS command signal by the delay module, and is not affected by the pulse width of the ECS command signal. Therefore, the pulse generator can generate an ECS pulse signal with a stable pulse width, avoid errors in the ECS mode, and ultimately improve the performance of the memory.

[0048] The following will describe each embodiment of the present disclosure in detail with reference to the accompanying drawings.

[0049] In an embodiment of the present disclosure, refer to Figure 4 , which shows a schematic structural diagram of a pulse generator 10 provided by an embodiment of the present disclosure. As Figure 4 shown, the pulse generator 10 includes:

[0050] A delay module 11 configured to receive an ECS command signal, perform delay processing on the ECS command signal, and output a delayed command signal; wherein, the delay between the ECS command signal and the delayed command signal is a first preset value;

[0051] A latching module 12 configured to receive the ECS command signal and the delayed command signal, perform latching processing based on the ECS command signal and the delayed command signal, and output an ECS pulse signal.

[0052] Here, the pulse width of the ECS command signal has multiple values, and the pulse width of the ECS pulse signal is the first preset value.

[0053] It should be noted that the pulse generator 10 in the embodiments of the present disclosure can be applied but not limited to memories, such as DRAM, SDRAM, DDR, etc. In addition, in other analog circuits / digital circuits, a signal with a stable pulse width can be generated by the pulse generator 10 provided by the embodiments of the present disclosure.

[0054] It should be noted that in the pulse generator 10, the delay processing performed by the delay module 11 on the ECS command signal is preset. Therefore, the delay value between the ECS command signal and the delay command signal is stably the first preset value. Further, since the pulse width of the ECS pulse signal depends only on the delay value between the ECS command signal and the delay command signal and is not affected by the pulse width of the ECS command signal, the pulse width of the ECS pulse signal is also stably the first preset value. In this way, the pulse generator 10 can generate an ECS pulse signal with a stable pulse width, which is not affected by the external operating frequency, ensuring that the waveform of the ECS pulse signal always meets the requirements, thereby ensuring the smooth execution of subsequent operations such as activation, reading, writing, and precharging, and avoiding errors in the ECS mode.

[0055] It should be understood that the present disclosure embodiments allow a certain error for the relevant numerical limitations such as the delay value and the pulse width. That is to say, the delay between the ECS command signal and the delay command signal is the first preset value within the allowable error range.

[0056] In some embodiments, the initial values of both the ECS command signal and the ECS pulse signal are the first level value. The latching module 11 is specifically configured to control the ECS pulse signal to change from the first level value to the second level value when the ECS command signal changes from the first level value to the second level value, and to control the ECS pulse signal to change from the second level value to the first level value when the delay command signal changes from the first level value to the second level value.

[0057] It should be noted that the first level value and the second level value are different, and their specific values can be determined according to the actual application scenario. Exemplarily, the first level value is represented as 0 and the second level value is represented as 1. At this time, the rising edge of the ECS pulse signal is generated by the rising edge of the ECS command signal, and the falling edge of the ECS pulse signal is generated by the rising edge of the ECS command signal. Therefore, the "pulse width of the ECS pulse signal" is the same as the "delay between the ECS command signal and the delay command signal", both of which are the first preset value.

[0058] As described above, since the ECS command signal is generated according to a multi-purpose instruction, a refresh instruction, or a self-refresh instruction, and there are multiple possibilities for the pulse width of the multi-purpose instruction, there are multiple values for the pulse width of the ECS command signal. However, due to the structure of the pulse generator 10, the pulse width of the ECS pulse signal is always fixed at the first preset value.

[0059] Specifically, in the manual ECS operation mode, the pulse width of the ECS command signal depends on the pulse width of the multi-purpose command MPC; in the automatic ECS operation mode, the pulse width of the ECS command signal depends on the pulse width of the refresh command Refresh or the self-refresh command Self_Refresh. For the manual ECS operation mode, the multi-purpose command MPC is sent by the memory controller, and its pulse width can have multiple possible values such as 1tCK or 5tCK, and the size of tCK depends on the external operating frequency.

[0060] Taking the external operating frequency of 3200 Mbps as an example, at this time 1tCK = 0.625 ns, 5tCK = 3.125 ns, and at the same time assume that the delay module 11 can fixedly generate a delay of 2 ns (i.e., the first preset value = 2 ns), see Figure 5 , which shows a signal timing schematic diagram provided by an embodiment of the present disclosure. As Figure 5 shown in (a) of, when the pulse width of the multi-purpose command MPC is 5tCK, the pulse width of the ECS command signal ECS_CMD is 3.125 ns. Since the delay between the ECS command signal ECS_CMD and the command delay signal ECS_Delay is 2 ns, the pulse width of the ECS pulse signal ECS_Pulse is 2 ns. As Figure 5 shown in (b) of, when the pulse width of the multi-purpose command MPC is 1tCK, the pulse width of the ECS command signal ECS_CMD is 0.625 ns. Since the delay between the ECS command signal ECS_CMD and the command delay signal ECS_Delay is 2 ns, the pulse width of the ECS pulse signal ECS_Pulse is also 2 ns.

[0061] In this way, in the manual ECS operation, no matter how many tCKs the pulse width of the multi-purpose command MPC is, and no matter what range the external operating frequency is in, an ECS pulse signal with a stable pulse width can be generated to facilitate the normal progress of subsequent operations.

[0062] In some embodiments, the latch module 12 is further configured to receive a reset signal; based on the reset signal, control the initial state of the ECS pulse signal to be a first level value. In this way, through the reset signal, the initial state of the ECS pulse signal can be maintained as the first level value to implement the foregoing control logic.

[0063] The following provides a specific composition of the latch module 12.

[0064] In some embodiments, as Figure 6As shown in the figure, the latch module 12 includes a first NOR gate 201 and a second NOR gate 202; among them, the first input terminal of the first NOR gate 201 receives the ECS command signal ECS_CMD, and the second input terminal of the first NOR gate 201 is connected to the output terminal of the second NOR gate 202; the first input terminal of the second NOR gate 202 is connected to the output terminal of the first NOR gate 201, the second input terminal of the second NOR gate 202 receives the delay command signal ECS_Delay, and the third input terminal of the second NOR gate 202 receives the reset signal Reset; correspondingly, the output terminal of the second NOR gate 202 is used to output the ECS pulse signal ECS_Pulse.

[0065] It should be noted that the first NOR gate 201 and the second NOR gate 202 together constitute an SR latch (Set-Reset Latch). The ECS command signal ECS_CMD is connected to the SET terminal of the SR latch, and then the delay command signal ECS_Delay (equivalent to the ECS command signal delayed by 2 ns) is connected to the RESET terminal of the SR latch. In addition, the external reset signal Reset will be used as an initial value, that is, when there is no ECS command signal ECS_CMD, it controls the ECS pulse signal ECS_Pulse to be always 0.

[0066] Combined Figure 5 with Figure 6 it can be known that for the SET terminal of the SR latch, when the ECS command signal ECS_CMD changes from 0 to 1 (rising edge), the ECS pulse signal ECS_Pulse changes from 0 to 1 (rising edge); then for the RESET terminal of the SR latch, when the delay command signal ECS_Delay changes from 0 to 1 (rising edge), the ECS pulse signal ECS_Pulse changes from 1 to 0 (falling edge), ensuring that the pulse width of the ECS pulse signal ECS_Pulse is about 2 ns.

[0067] It should be noted that the ECS pulse signal ECS_Pulse, as the output of the second NOR gate 202, must be connected to the input terminal of the first NOR gate 201, so that the delay command signal ECS_Delay and the reset signal Reset have higher priorities in the SR latch. In this way, when the pulse width of the ECS command signal ECS_CMD is greater than 2 ns, both the ECS command signal ECS_CMD and the delay command signal ECS_Delay are 1, but the delay command signal ECS_Delay can still reset the ECS pulse signal ECS_Pulse, thus ensuring that the pulse width of the ECS pulse signal ECS_Pulse is the first preset value.

[0068] On Figure 6 this Figure 7As shown, in some other embodiments, the latching module 12 further includes a first inverter 203 and a second inverter 204; wherein, the input end of the first inverter 203 is connected to the output end of the second NOR gate 202, and the input end of the second inverter 204 is connected to the output end of the first inverter 203; correspondingly, the output end of the second inverter 204 is used to output the ECS pulse signal.

[0069] It should be noted that the ECS pulse signal can be delay-matched and drive-enhanced via two inverters, so that the ECS pulse signal is more stable and meets the timing requirements.

[0070] In this way, compared with the pulse generator in Figure 2 , the pulse generator 10 in Figure 7 can ensure that the pulse width of the ECS pulse signal is 2 ns in both the automatic ECS operation mode or the manual ECS operation mode, so that the ECS pulse signal is not affected by the external frequency in the manual ECS operation mode. Regardless of how many tCKs the pulse period of the multi-purpose instruction MPC is, an ECS pulse signal with a stable pulse width can be generated.

[0071] In addition, the embodiments of the present disclosure also improve the delay module so that the delay of the delay module 11 is stably the first preset value in different scenarios, and the delay of the delay module 11 is adjustable (that is, the size of the first preset value can be adjusted).

[0072] In a feasible embodiment, as shown in (a) of Figure 8 , the delay module 11 includes a first delay unit 111 and an adjustment unit 112; wherein,

[0073] The first delay unit 111 is configured to receive the ECS command signal and output an intermediate delay signal; wherein, the delay value between the ECS command signal and the intermediate delay signal is less than the first preset value;

[0074] The adjustment unit 112 is configured to receive an adjustment parameter and perform delay processing on the intermediate delay signal based on the adjustment parameter to output a delay command signal.

[0075] It should be understood that the first delay unit 111 and the adjustment unit 112 are connected in series, and their front and rear positions can be exchanged. In this way, the first delay unit 111 can perform a fixed delay on the ECS command signal, and the adjustment unit 112 can adjust the ECS command signal to different degrees according to the adjustment parameter, so as to ensure that the delay between the ECS command signal and the delay command signal is the first preset value.

[0076] Exemplarily, assume that the first preset value is 2 ns. The first delay unit 111 can cause a 1.8 ns delay of the intermediate delay signal relative to the ECS command signal under standard environmental parameters. At the same time, the adjustment unit 112 can cause a 0.2 ns delay of the delay command signal relative to the intermediate delay signal when the initial value of the adjustment parameter is adjusted, so as to jointly achieve a 2 ns delay between the ECS command signal and the delay command signal.

[0077] In one case, due to the change of the working environment parameters, the delay value of the first delay unit 111 shifts so that the intermediate delay signal has a 1.7 ns delay relative to the ECS command signal. Then, by adjusting the value of the adjustment parameter, the delay command signal has a 0.3 ns delay relative to the intermediate delay signal, so that the delay between the ECS command signal and the delay command signal is still 2 ns. The delay offset caused by other factors can be understood correspondingly.

[0078] In another case, if it is desired to adjust the first preset value from 2 ns to 2.5 ns, then by adjusting the value of the adjustment parameter, the delay command signal has a 0.7 ns delay relative to the intermediate delay signal, so that the delay between the ECS command signal and the delay command signal is adjusted to 2.5 ns.

[0079] In this way, the function of the delay module 11 provided by the embodiments of the present disclosure is richer and more stable, and the performance of the pulse generator 10 is also improved.

[0080] In another feasible embodiment, as shown in Figure 8 (b), the delay module 11 includes an adjustment unit 112; wherein, the adjustment unit 112 is configured to receive an adjustment parameter and perform delay processing on the ECS command signal based on the adjustment parameter, and output a delay command signal.

[0081] That is to say, the delay module 11 is composed of adjustable units, and there is no unit for fixed delay. In this way, the adjustment range of the first preset value is more flexible, but the control logic becomes correspondingly more, and it can be applied to scenarios with specific requirements.

[0082] The adjustment principle of the adjustment unit 112 will be specifically described below. In particular, the following descriptions can be applied to the circuit structure shown in Figure 8 (a), or applied to the circuit structure shown in Figure 8 (b).

[0083] In some embodiments, as shown in Figure 9As shown in (a) or (b) therein, the pulse generator 10 is applied to the memory, and the adjustment parameter includes an N-bit adjustment sub-signal, where N is a positive integer; among them, the N-bit adjustment sub-signal is set via an external command in the test mode of the memory and can be referred to as the test mode code TS_Code; or, the N-bit adjustment sub-signal is determined based on the temperature decoding of the memory and can be referred to as the temperature control adjustment code TM_Code; or, a part of the N-bit adjustment sub-signal is set via an external command in the test mode of the memory, and the remaining part of the N-bit adjustment sub-signal is determined based on the temperature decoding of the memory, that is, the N-bit adjustment sub-signal is jointly composed of the test mode code TS_Code and the temperature control adjustment code TM_Code.

[0084] In this way, when the memory is in the test mode, the user can send a setting command to set the specific value of the test mode code TM_Code to change the delay generated by the adjustment unit 112, compensate for the process deviation in the manufacturing process of the delay module 11 or the deviation caused by other factors (or modify the size of the first preset value). And / or, during the operation of the memory, the temperature control adjustment code TS_Code is obtained based on the operating temperature decoding to change the delay generated by the adjustment unit 112, that is, the memory can automatically adjust the delay value generated by the delay module 11 according to the temperature situation, so as to compensate for the delay deviation of the delay module 11 caused by the change of the operating temperature (or the size of the first preset value can also be modified by modifying the decoding rule). In this way, the delay value of the delay module 11 is always the first preset value and remains stable, so that the pulse width of the ECS pulse signal meets the requirements and ensures the normal execution of subsequent operations.

[0085] In some embodiments, refer to Figure 10 , which is a schematic structural diagram of an adjustment unit 112 provided by an embodiment of the present disclosure. As Figure 10 shown, the adjustment unit 112 includes N delay sub-modules arranged in series (shown by taking N = 4 as an example in Figure 10 ), and the input end of the first delay sub-module is the input end of the adjustment unit 112, the input end of the (i + 1)-th delay sub-module is connected to the output end of the i-th delay sub-module, and the output end of the N-th delay sub-module forms the output end of the adjustment unit 112.

[0086] It should be noted that among the N-bit adjustment sub-signals for adjusting parameters, each adjustment sub-signal belongs to an upward adjustment parameter (such as TM_UP0, TS_CD1) or a downward adjustment parameter (such as TM_DN0, TS_CD0). Correspondingly, the adjustment unit 112 is specifically configured to, when the i-th adjustment sub-signal belongs to an upward adjustment parameter, if the i-th adjustment sub-signal is in the first state, control the i-th delay sub-module to perform a delay transmission process on the input signal; if the i-th adjustment sub-signal is in the second state, control the i-th delay sub-module to perform a direct transmission process on the input signal; or, when the i-th adjustment sub-signal belongs to a downward adjustment parameter, if the i-th adjustment sub-signal is in the first state, control the i-th delay sub-module to perform a direct transmission process on the input signal; if the i-th adjustment sub-signal is in the second state, control the i-th delay sub-module to perform a delay transmission process on the input signal. Wherein, i is a positive integer and i is less than or equal to N

[0087] Here, the first state and the second state are different, and the specific values can be set according to the actual application scenario. For example, the first state can be represented as 1 and the second state can be represented as 0.

[0088] It should be understood that in Figure 10 the adjustment unit 112 includes 4 delay sub-modules, the adjustment parameters include 4-bit adjustment sub-signals of TM_UP0, TS_CD1, TM_DN0, and TS_CD0, and TS_CD1 and TS_CD0 belong to the test mode code, TM_UP0 and TM_DN0 belong to the temperature control adjustment code. At the same time, TM_UP0 and TS_CD1 belong to the upward adjustment parameters, and TM_DN0 and TS_CD0 belong to the downward adjustment parameters. In the actual application process, the specific quantities of the delay sub-module, the adjustment sub-signal of the adjustment parameter, the upward adjustment parameter, the downward adjustment parameter, etc. can all be determined according to requirements. The embodiments of the present disclosure only use Figure 10 as an example for subsequent description, but Figure 10 do not constitute any limitation on the quantity.

[0089] In this way, for the adjustment unit 112, by setting the specific values of the upward adjustment parameter and the downward adjustment parameter, the working state of the delay sub-module can be changed, thereby changing the delay generated by the adjustment unit 112.

[0090] In some embodiments, each delay sub-module includes a first path and a second path, and a second delay unit is provided on the first path (such as Figure 10among 34-1, 34-2, 34-3, 34-4), and the second delay unit is used to introduce a delay of a second preset value to the input signal (such as 0.1 ns, 0.05 ns); wherein, the second preset value is less than the first preset value. Correspondingly, the i-th delay sub-module is configured to receive an input signal, the i-th adjustment sub-signal, and the inverted signal of the i-th adjustment sub-signal; and based on the level state of the i-th adjustment sub-signal, perform a delayed transmission process on the input signal through a first path, or perform a direct transmission process on the input signal through a second path.

[0091] It should be understood that since the second delay unit is provided on the first path, compared with the second path, an additional delay of the second preset value is generated during signal transmission on the first path. Therefore, the signal transmission via the first path is referred to as a delayed transmission process, and the signal transmission via the second path is referred to as a direct transmission process.

[0092] Here, each second delay unit is used to generate a delay of the second preset value, and the delays generated by different second delay units can be the same or different. For example, all the second delay units generate a delay of 0.1 ns, or all the second delay units generate a delay of 0.05 ns, or some second delay units generate a delay of 0.1 ns and some second delay units generate a delay of 0.05 ns. In the following embodiments of the present disclosure, it is taken as an example that all the second delay units generate a delay of 0.1 ns, but this does not constitute a relevant limitation.

[0093] It should also be noted that when the adjustment sub-signal belongs to an up-regulation parameter (such as Figure 10 TM_UP0 / TS_CD1 in), if the adjustment sub-signal is in a first state, then the corresponding delay sub-module performs a delayed transmission process on the input signal through the first path; if the adjustment sub-signal is in a second state, then the corresponding delay sub-module performs a direct transmission process on the input signal through the second path. On the contrary, when the adjustment sub-signal belongs to a down-regulation parameter (such as Figure 10 TM_DN0 / TS_CD0 in), if the adjustment sub-signal is in a first state, then the corresponding delay sub-module performs a direct transmission process on the input signal through the second path; if the adjustment sub-signal is in a second state, then the corresponding delay sub-module performs a delayed transmission process on the input signal through the first path.

[0094] In a specific embodiment, when the i-th adjustment sub-signal belongs to an up-regulation parameter (specifically referring to Figure 10 the 1st and 3rd delay sub-modules from the left in), the i-th delay sub-module further includes a first NAND gate (such as Figure 10 31-2, 31-4 in), a second NAND gate (such as Figure 10in 32-2, 32-4) and the third NAND gate (e.g., Figure 10 in 33-2, 33-4). Among them, the first input terminal of the first NAND gate is connected to the inverted signal of the i-th regulator signal; the second input terminal of the first NAND gate receives the input signal of the i-th delay sub-module, the output terminal of the first NAND gate is connected to the first input terminal of the third NAND gate, and the output terminal of the third NAND gate outputs the output signal of the i-th delay sub-module to form the second path; the first input terminal of the second NAND gate is connected to the i-th regulator signal; the second input terminal of the second NAND gate receives the input signal of the i-th delay sub-module, the output terminal of the second NAND gate is connected to the input terminal of the second delay unit (e.g., Figure 10 in 34-2, 34-4), the output terminal of the second delay unit is connected to the second input terminal of the third NAND gate, and the output terminal of the third NAND gate outputs the output signal of the i-th delay sub-module to form the first path.

[0095] Similarly, when the i-th regulator signal belongs to the down-regulation parameter (specifically refer to Figure 10 the first and the third delay sub-modules from the left in), the i-th delay sub-module further includes a first NAND gate (e.g., Figure 10 in 31-1, 31-3), a second NAND gate (e.g., Figure 10 in 32-1, 32-3) and a third NAND gate (e.g., Figure 10 in 33-1, 33-3). Among them, the second input terminal of the first NAND gate receives the input signal of the i-th delay sub-module, the output terminal of the first NAND gate is connected to the input terminal of the second delay unit (e.g., Figure 10 in 34-1, 34-3), the output terminal of the second delay unit is connected to the second input terminal of the third NAND gate, and the output terminal of the third NAND gate outputs the output signal of the i-th delay sub-module to form the first path;

[0096] the first input terminal of the second NAND gate is connected to the i-th regulator signal, the second input terminal of the second NAND gate receives the input signal of the i-th delay sub-module, the output terminal of the second NAND gate is connected to the first input terminal of the third NAND gate, and the output terminal of the third NAND gate outputs the output signal of the i-th delay sub-module to form the second path.

[0097] In addition, as Figure 10 shown, the adjustment unit 112 further includes N third inverters ( Figure 11Taking N = 4 as an example for output), the receiving end of the i-th third inverter receives the i-th bit adjustment sub-signal (TM_DN0, TM_UP0, TS_CD0 or TS_CD1), and the output end of the i-th third inverter outputs the inverted signal of the i-th bit adjustment sub-signal (TM_DNB0, TM_UPB0, TS_CDB0 or TS_CDB1).

[0098] As in the aforementioned example scenario, the initial values of TM_DN0, TM_UP0, TS_CD0 or TS_CD1 can all be set to 0. At this time, the adjustment unit 112 generates a total delay of 0.2 ns. In this way, by setting TS_CD0 to 1 in the test mode, the delay value of the adjustment unit 112 can be reduced by 0.1 ns, or by setting TS_CD1 to 1, the delay value of the adjustment unit 112 can be increased by 0.1 ns. In addition, for the memory, the delay value of the delay module 11 is associated with the operating temperature. Therefore, by decoding the temperature signal measured by the temperature sensor and performing corresponding logical processing, the delay can be increased or decreased for compensation; specifically, by decoding the temperature sensor to set TM_DN0 to 1, the delay value of the delay module 11 can be reduced by 0.1 ns; or by setting TM_UP1 to 1, the delay value of the delay module 11 can be increased by 0.1 ns. As can be seen from the above, the operating parameters of the delay module 11 in the pulse generator 10 (the operating parameters refer to that there are multiple delay sub-modules in the adjustment module 112 to delay the input signal for transmission processing) can be adjusted, which can not only compensate for the delay value changes caused by various factors, but also adjust the size of the first preset value to further ensure the pulse width stability of the ECS pulse signal.

[0099] In summary, in the automatic ECS operation mode, it is necessary to steal a refresh instruction or a self-refresh instruction to generate an ECS command signal; in the manual ECS operation mode, it is necessary to generate an ECS command signal through a multi-purpose command MPC. Since the ECS command signal indicates error checking and clearing of the memory, subsequent operations such as activation, reading / writing, and precharging need to be performed. Therefore, after the ECS command signal is generated, the pulse needs to be made stable. In particular, the pulse width of the ECS command signal generated by the multi-purpose command MPC may be 1 tCK or multiple tCKs. An embodiment of the present disclosure provides a pulse generator 10. On the one hand, for ECS command signals with different pulse widths, it can generate ECS pulse signals with a stable pulse width, which is not affected by the external operating frequency, ensuring that the waveform of the ECS pulse signal always meets the requirements, and thus ensuring the smooth execution of subsequent operations such as activation, reading / writing, and precharging. On the other hand, the operating parameters of the delay module in the pulse generator 10 can be adjusted, which can not only compensate for the change in the delay value caused by various factors, but also adjust the size of the first preset value, further ensuring the stability of the pulse width of the ECS pulse signal.

[0100] In another embodiment of the present disclosure, refer to Figure 11 , which shows a schematic structural diagram of an error checking and clearing circuit 40 provided by an embodiment of the present disclosure. As Figure 11 shown, the error checking and clearing circuit 40 includes a command generation module 401 and the aforementioned pulse generator 10; wherein,

[0101] The command generation module is configured to receive a multi-purpose command sent externally in the first operating mode, and output an ECS command signal based on the multi-purpose command MPC; wherein, the pulse width of the ECS command signal is associated with the pulse width of the multi-purpose command MPC, and there are multiple values for the pulse width of the multi-purpose command MPC;

[0102] The pulse generator is configured to output an ECS pulse signal based on the ECS command signal, and the pulse width of the ECS pulse signal is a first preset value.

[0103] It should be noted that for the structure of the pulse generator 10, please refer to the foregoing description. Here, since there are multiple values for the pulse width of the multi-purpose instruction, and the pulse width of the multi-purpose instruction determines the pulse width of the ECS command signal (specifically refer to the foregoing description), there are multiple values for the pulse width of the ECS command signal. For the pulse generator 10, the ECS command signal is delayed to generate a delayed command signal, and the delay between the ECS command signal and the delayed command signal is a first preset value. Subsequently, the ECS pulse signal is jointly generated by using the ECS command signal and the delayed command signal; further, since the pulse width of the ECS pulse signal depends on the delay between the ECS command signal and the delayed command signal, the pulse width of the ECS pulse signal is also the first preset value. In this way, the pulse generator 10 can generate an ECS pulse signal with a stable pulse width, which is not affected by the external operating frequency, ensuring that the waveform of the ECS pulse signal always meets the requirements, and thus ensuring the smooth execution of subsequent operations such as activation, reading, writing, and precharging.

[0104] In some embodiments, the command generation module is configured to output an ECS command signal based on a refresh instruction Refresh or a self-refresh instruction Self_Refresh in a second operating mode. Here, the first operating mode is a manual ECS operation mode, and the second operating mode is an automatic ECS operation mode.

[0105] The embodiment of the present disclosure provides an error checking and clearing circuit 40, which includes a pulse generator 10 as shown in Figure 4 , Figures 6 - 10 On the one hand, for ECS command signals with different pulse widths, the pulse generator 10 can generate ECS pulse signals with a stable pulse width, which is not affected by the external operating frequency, ensuring that the waveform of the ECS pulse signal always meets the requirements, and thus ensuring the smooth execution of subsequent operations such as activation, reading, writing, and precharging; on the other hand, the operating parameters of the delay module in the pulse generator 10 can be adjusted, which can not only compensate for the change of the delay value caused by various factors, but also adjust the size of the first preset value, further ensuring the stability of the pulse width of the ECS pulse signal.

[0106] In another embodiment of the present disclosure, refer to Figure 12 , which shows a schematic diagram of the composition structure of a memory 50 provided by the embodiment of the present disclosure. As shown in Figure 12 , the memory 50 at least includes the foregoing error checking and clearing circuit 40.

[0107] In some embodiments, the memory complies with the DDR5 specification.

[0108] In this way, the memory of the embodiment of the present disclosure passes through such as Figure 4 ,Figures 6 - 10 The pulse generator 10 shown generates an ECS pulse signal. On the one hand, for ECS command signals with different pulse widths, the pulse generator 10 can generate ECS pulse signals with stable pulse widths, without being affected by the external operating frequency, ensuring that the waveform of the ECS pulse signal always meets the requirements, and thus ensuring the smooth execution of subsequent operations such as activation, reading / writing, and precharging. On the other hand, the operating parameters of the delay module in the pulse generator 10 can be adjusted, which can not only compensate for the change in the delay value caused by various factors, but also adjust the magnitude of the first preset value, further ensuring the stability of the pulse width of the ECS pulse signal.

[0109] The above are only the preferred embodiments of the present disclosure and are not used to limit the protection scope of the present disclosure. It should be noted that in the present disclosure, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including the element. The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the superiority or inferiority of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments. The above are only the specific implementation manners of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A pulse generator, characterized in that, the pulse generator comprises: a delay module configured to receive an ECS command signal, perform delay processing on the ECS command signal, and output a delayed command signal; wherein, the delay between the ECS command signal and the delayed command signal is a first preset value; a latch module configured to receive the ECS command signal and the delayed command signal, perform latch processing based on the ECS command signal and the delayed command signal, and output an ECS pulse signal; wherein, the pulse width of the ECS command signal has multiple values, and the pulse width of the ECS pulse signal is the first preset value; the latch module includes a first NOR gate and a second NOR gate; wherein, a first input terminal of the first NOR gate receives the ECS command signal, and a second input terminal of the first NOR gate is connected to an output terminal of the second NOR gate; a first input terminal of the second NOR gate is connected to an output terminal of the first NOR gate, a second input terminal of the second NOR gate receives the delayed command signal, and a third input terminal of the second NOR gate receives a reset signal; correspondingly, the output terminal of the second NOR gate is used to output the ECS pulse signal.

2. The pulse generator according to claim 1, characterized in that, the initial values of the ECS command signal and the ECS pulse signal are both a first level value; the latch module is specifically configured to control the ECS pulse signal to change from the first level value to the second level value when the ECS command signal changes from the first level value to the second level value; and control the ECS pulse signal to change from the second level value to the first level value when the delayed command signal changes from the first level value to the second level value.

3. The pulse generator according to claim 2, characterized in that, the latch module is further configured to receive the reset signal, and based on the reset signal, control the initial state of the ECS pulse signal to be the first level value.

4. The pulse generator according to claim 1, characterized in that, the latch module further includes a first inverter and a second inverter; wherein, an input terminal of the first inverter is connected to an output terminal of the second NOR gate, and an input terminal of the second inverter is connected to an output terminal of the first inverter; correspondingly, the output terminal of the second inverter is used to output the ECS pulse signal.

5. The pulse generator according to claim 2, characterized in that, the delay module includes a first delay unit and an adjustment unit; wherein, the first delay unit is configured to receive the ECS command signal and output an intermediate delay signal; wherein, the delay value between the ECS command signal and the intermediate delay signal is less than the first preset value; the adjustment unit is configured to receive an adjustment parameter and the intermediate delay signal, perform delay processing on the intermediate delay signal based on the adjustment parameter, and output the delayed command signal.

6. The pulse generator according to claim 2, characterized in that, The delay module includes an adjustment unit; wherein, The adjustment unit is configured to receive an adjustment parameter, delay the ECS command signal based on the adjustment parameter, and output the delayed command signal.

7. The pulse generator according to any one of claims 5 or 6, characterized in that, The adjustment parameter includes an N-bit adjustment sub-signal, and the adjustment unit includes N delay sub-modules arranged in series. The input end of the first delay sub-module forms the input end of the adjustment unit. The input end of the (i + 1)-th delay sub-module is connected to the output end of the i-th delay sub-module, and the output end of the N-th delay sub-module forms the output end of the adjustment unit; The adjustment unit is specifically configured to, when the i-th bit adjustment sub-signal belongs to an up-regulation parameter, if the i-th bit adjustment sub-signal is in the first state, control the i-th delay sub-module to perform a delay transmission process on the input signal; if the i-th bit adjustment sub-signal is in the second state, control the i-th delay sub-module to perform a direct transmission process on the input signal; or, When the i-th bit adjustment sub-signal belongs to a down-regulation parameter, if the i-th bit adjustment sub-signal is in the first state, control the i-th delay sub-module to perform a direct transmission process on the input signal; if the i-th bit adjustment sub-signal is in the second state, control the i-th delay sub-module to perform a delay transmission process on the input signal; wherein both i and N are positive integers, and i is less than or equal to N.

8. The pulse generator according to claim 7, characterized in that, Each of the delay sub-modules includes a first path and a second path. A second delay unit is provided on the first path, and the second delay unit is used to cause a delay of a second preset value to the input signal; wherein, the second preset value is less than the first preset value; wherein, The i-th delay sub-module is configured to receive an input signal, the i-th bit adjustment sub-signal, and the inverted signal of the i-th bit adjustment sub-signal; and based on the level state of the i-th adjustment sub-signal, perform a delay transmission process on the input signal through the first path, or perform a direct transmission process on the input signal through the second path.

9. The pulse generator according to claim 8, characterized in that, When the i-th bit adjustment sub-signal belongs to an up-regulation parameter, the i-th delay sub-module further includes a first NAND gate, a second NAND gate, and a third NAND gate; wherein, The first input end of the first NAND gate is connected to the inverted signal of the i-th bit adjustment sub-signal; the second input end of the first NAND gate receives the input signal of the i-th delay sub-module, the output end of the first NAND gate is connected to the first input end of the third NAND gate, and the output end of the third NAND gate outputs the output signal of the i-th delay sub-module to form the second path; The first input terminal of the second NAND gate is connected to the i-th regulator signal; the second input terminal of the second NAND gate receives the input signal of the i-th delay sub-module, the output terminal of the second NAND gate is connected to the input terminal of the second delay unit, the output terminal of the second delay unit is connected to the second input terminal of the third NAND gate, and the output terminal of the third NAND gate outputs the output signal of the i-th delay sub-module to form the first path.

10. The pulse generator according to claim 8, wherein When the i-th regulator signal belongs to a down-regulated parameter, the i-th delay sub-module further includes a first NAND gate, a second NAND gate, and a third NAND gate; wherein The first input terminal of the first NAND gate is connected to the inverted signal of the i-th regulator signal; the second input terminal of the first NAND gate receives the input signal of the i-th delay sub-module, the output terminal of the first NAND gate is connected to the input terminal of the second delay unit, the output terminal of the second delay unit is connected to the second input terminal of the third NAND gate, and the output terminal of the third NAND gate outputs the output signal of the i-th delay sub-module to form the first path; The first input terminal of the second NAND gate is connected to the i-th regulator signal; the second input terminal of the second NAND gate receives the input signal of the i-th delay sub-module, the output terminal of the second NAND gate is connected to the first input terminal of the third NAND gate, and the output terminal of the third NAND gate outputs the output signal of the i-th delay sub-module to form the second path.

11. The pulse generator according to claim 7, wherein The pulse generator is applied to a memory; wherein The N-bit regulator signal is set via an external command in the test mode of the memory; or, the N-bit regulator signal is determined based on the temperature decoding of the memory; or, a part of the N-bit regulator signal is set via an external command in the test mode of the memory, and the remaining part of the N-bit regulator signal is determined based on the temperature decoding of the memory.

12. An error checking and correcting circuit, characterized in that The error checking and correcting circuit includes a command generation module and the pulse generator according to any one of claims 1-11; wherein The command generation module is configured to receive a multi-purpose instruction sent externally in a first operating mode, and output an ECS command signal based on the multi-purpose instruction; wherein, the pulse width of the ECS command signal is associated with the pulse width of the multi-purpose instruction, and there are multiple values for the pulse width of the multi-purpose instruction; The pulse generator is configured to output an ECS pulse signal based on the ECS command signal, and the pulse width of the ECS pulse signal is a first preset value.

13. The error checking and correcting circuit according to claim 12, wherein The command generation module is configured to output the ECS command signal based on a refresh instruction or a self-refresh instruction in a second operating mode.

14. A memory, characterized in that, the memory includes an error checking and correcting circuit as described in claim 12 or 13.

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