Bevel 6° goi substrate, short-wave infrared focal plane pixel and preparation method thereof

Abstract

The application relates to a 6-degree bevel GOI substrate, a short-wave infrared focal plane pixel and a preparation method thereof. A bevel GOI substrate comprises a silicon substrate, a medium stack layer and a 6-degree bevel germanium layer from bottom to top. A 6-degree bevel silicon substrate is provided; a low-temperature germanium layer and a high-temperature germanium layer are sequentially formed on the 6-degree bevel silicon substrate; a first medium layer is formed on the high-temperature germanium layer to obtain a sacrifice substrate; a second medium layer is formed on the silicon substrate to obtain a support substrate; the sacrifice substrate and the support substrate are bonded with the first medium layer and the second medium layer as bonding surfaces; and then the bevel silicon substrate and the low-temperature germanium layer are sequentially removed. The application solves the problems of reverse domains, large lattice mismatch and high thermal mismatch existing in III-V material epitaxial growth, improves the responsivity of III-V material epitaxial material and short-wave infrared focal plane pixels and other devices based on the III-V material epitaxial material, and reduces the dark current of the devices.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to a bevel 6° GOI substrate, a short-wave infrared focal plane pixel and a preparation method thereof. BACKGROUND

[0002] The short-wave infrared focal plane based on III-V short-wave infrared material system has the characteristics of high sensitivity, high uniformity and high stability, and its response band can cover the range of 0.9-3.0 μm. However, the commercialized III-V short-wave infrared focal plane has the disadvantages of small wafer size, high manufacturing cost and small array size, and it is an inevitable trend to replace the high-cost small-size substrate with a low-cost large-size substrate. The Si substrate not only has the characteristics of large size and mature manufacturing process, but also has the advantage of low cost, so it is one of the important technical approaches to support the development of low-cost short-wave infrared imaging technology to realize high-performance III-V short-wave infrared focal plane on the Si substrate. The technical difficulty lies in the difference in crystal structure between Si and III-V short-wave infrared material system, and problems such as reverse domain, large lattice mismatch and thermal mismatch are also faced in epitaxial growth.

[0003] Therefore, the present application is proposed. SUMMARY

[0004] The main purpose of the present application is to provide a bevel 6° GOI substrate, a short-wave infrared focal plane pixel and a preparation method thereof, which solves the problems of reverse domain, large lattice mismatch and thermal mismatch in the epitaxial growth of III-V materials, improves the quality of III-V epitaxial materials and the responsivity of short-wave infrared focal plane pixels and other devices based thereon, and reduces the dark current of the device.

[0005] In order to achieve the above purpose, the present application provides the following technical solutions.

[0006] The first aspect of the present application provides a bevel 6° GOI substrate, which comprises a silicon substrate, a dielectric stack layer and a bevel 6° germanium layer from bottom to top.

[0007] Compared with ordinary GOI substrates or III-V-OI substrates, the bevel 6° GOI substrate provided by the present application can improve the quality of III-V materials epitaxially grown thereon due to the 6° bevel angle and high crystal quality, reduce the defect density, and avoid problems such as reverse domain, large lattice mismatch and thermal mismatch.

[0008] In addition, the dielectric stack layer in the bevel GOI substrate provided by the present application has a resonant cavity effect, which can significantly improve the responsivity when used in a short-wave infrared focal plane pixel.

[0009] The medium stack layer in the present application can be a stack of multiple medium materials or a stack of multiple layers of the same medium material.

[0010] For example, in some embodiments, the medium stack layer is a stack of multiple layers of silicon oxide, or a cross stack of silicon oxide and aluminum oxide, or a stack of multiple layers of aluminum oxide.

[0011] In some embodiments, the thickness of the 6°-bevelled germanium layer is 100-500 nm.

[0012] Unless otherwise specified, the silicon substrate in the present application refers to a substrate without bevel.

[0013] The second aspect of the present application provides a method for preparing a 6°-bevelled GOI substrate, comprising:

[0014] providing a 6°-bevelled silicon substrate;

[0015] forming a low-temperature germanium layer and a high-temperature germanium layer on the 6°-bevelled silicon substrate in sequence;

[0016] forming a first medium layer on the high-temperature germanium layer to obtain a sacrificial substrate;

[0017] providing a silicon substrate;

[0018] forming a second medium layer on the silicon substrate to obtain a support substrate;

[0019] bonding the sacrificial substrate and the support substrate with the first medium layer and the second medium layer as the bonding surface;

[0020] then removing the 6°-bevelled silicon substrate and the low-temperature germanium layer in sequence;

[0021] optionally performing a planarization treatment on the surface of the high-temperature germanium layer.

[0022] The above method uses a 6°-bevelled silicon substrate with the same bevel angle as a template or guide substrate to grow a high-quality 6°-bevelled high-temperature germanium layer thereon, and then transfers the 6°-bevelled high-temperature germanium layer to a silicon substrate without bevel, which greatly improves the quality of the 6°-bevelled high-temperature germanium layer and greatly reduces the defect density.

[0023] In some embodiments, the first medium layer and the second medium layer each independently uses at least one of silicon oxide, aluminum oxide or TEOS.

[0024] In some embodiments, the second medium layer is a stack of multiple layers of material.

[0025] The medium stack layer in the above various forms has good resonant cavity effect.

[0026] The second medium layer also adopts a form of a stack of multiple layers of materials, which can further reduce the adverse effect of the bonding on the bevelled high-temperature germanium layer and improve the resonance cavity effect.

[0027] In some embodiments, the first medium layer is formed by using an ALD method; for example, an ALD method is used to form an aluminum oxide as the first medium layer.

[0028] In addition, the second medium layer is formed by using at least one of a thermal oxidation method and a CVD method. When the second medium layer is a stack of multiple layers of materials, a silicon oxide layer can be formed on the silicon substrate by using a thermal oxidation method, and then a silicon oxide or other material layer is formed by using a CVD method.

[0029] In some embodiments, the bevelled silicon substrate is removed by using grinding or dry etching.

[0030] In addition, the low-temperature germanium layer is removed by using a TMAH etching method.

[0031] The above embodiments use appropriate methods to remove different materials, which can reduce the adverse effect on the substrate and improve the process efficiency.

[0032] In some embodiments, a compositionally graded germanium-silicon buffer layer is formed on the bevelled 6° silicon substrate before the low-temperature germanium layer is formed.

[0033] The compositionally graded germanium-silicon buffer layer can further improve the crystal quality of the bevelled germanium layer.

[0034] In some embodiments, high-temperature annealing or cyclic annealing treatment is performed when the high-temperature germanium layer is formed, the high-temperature annealing has a temperature of 820°C, an annealing time of 10 min, and an annealing atmosphere of H2. This scheme can also further improve the crystal quality of the bevelled germanium layer.

[0035] In some embodiments, the growth temperature of the high-temperature germanium layer is 550-750°C, and the growth temperature of the low-temperature germanium layer is 350-450°C.

[0036] A third aspect of the present application provides a short-wave infrared focal plane pixel, comprising:

[0037] The bevelled 6° GOI substrate described above;

[0038] A GaAs buffer layer located above the substrate;

[0039] A PIN stack structure located above the GaAs buffer layer, and the PIN stack structure adopts III-V group materials, and the PIN stack structure mainly comprises: + -InGaAs / I-InGaAs / P +-InGaAs, N + -InP / I-InGaAs / P + -InP, P + -GaAsSb / I-InGaAs / N + -InP, N + -GaAs / I-AlGaAs / InGaAs multi-quantum well / P + -GaAs, N + -GaAs / I-AlGaAs / InGaAs multi-quantum dot / P + -GaAs, etc.

[0040] and N-type contact structure and P-type contact structure respectively achieving ohmic contact with N layer and P layer in the PIN stack structure.

[0041] The short-wave infrared focal plane pixel is taken the bevel 6° GOI substrate as the substrate, so the III-V PIN stack structure grown thereon has high quality, and has no problems such as reverse domain, large lattice mismatch, high thermal mismatch, etc., and the responsivity is improved and the dark current is reduced. Meanwhile, GaAs is taken as the buffer layer in the scheme, and the crystal quality is further improved.

[0042] In some embodiments, the PIN stack structure is a vertical stack structure.

[0043] Of course, the PIN structure of the present application is not limited to the vertical stack structure.

[0044] In addition, the order of the PIN vertical stack structure can be P-I-N from bottom to top, or N-I-P.

[0045] The fourth aspect of the present application provides a preparation method of the short-wave infrared focal plane pixel, comprising:

[0046] The bevel 6° GOI substrate is prepared by using the preparation method of the bevel 6° GOI substrate described above;

[0047] A GaAs buffer layer is formed on the bevel 6° GOI substrate;

[0048] A PIN stack structure is formed on the GaAs buffer layer;

[0049] The N-type contact structure and the P-type contact structure are formed respectively.

[0050] In some embodiments, the GaAs buffer layer is formed by using a low-temperature-moderate-temperature-high-temperature three-step method, and the ranges of the low temperature, the moderate temperature and the high temperature are 390-410℃, 580-610℃ and 660-680℃ respectively, and the ranges of the low temperature, the moderate temperature and the high temperature are preferably 400℃, 600℃ and 670℃ respectively.

[0051] In some embodiments, after forming the N-type contact structure and the P-type contact structure, further comprising: forming a two-dimensional crystal. The two-dimensional crystal can improve responsivity.

[0052] In some embodiments, before forming the N-type contact structure and the P-type contact structure, further comprising: patterning the PIN stack structure to form a mesa; the mesa exposes layers of the PIN stack structure close to the GaAs buffer layer. The device of this structure has a simpler patterning process, without the need for etching contact holes and other structures prone to defects.

[0053] In summary, compared with the prior art, the present application achieves the following technical effects: on the one hand, a high-quality bevel 6° GOI substrate is obtained; on the other hand, a high-quality epitaxial III-V short-wave infrared focal plane pixel is obtained based on the substrate, with higher responsivity and smaller dark current; on the other hand, all process flows can be compatible with existing semiconductor processes, with the advantages of low cost, etc. BRIEF DESCRIPTION OF DRAWINGS

[0054] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are merely illustrative and are not considered to be limiting on the present application.

[0055] Figures 1-8 Structure schematic diagram obtained by each step of the preparation method of the bevel 6° GOI substrate provided by the present application;

[0056] Figures 9-13 Structure schematic diagram obtained by each step of the preparation method of the short-wave infrared focal plane pixel provided by the present application. DETAILED DESCRIPTION

[0057] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description is merely exemplary and is not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0058] In the drawings, various structure schematic diagrams according to embodiments of the present disclosure are shown. These diagrams are not drawn to scale, in which certain details are exaggerated for clarity and others are omitted. The shapes and relative sizes of the various regions, layers, and elements illustrated in the drawings are exemplary only and can vary depending on the manufacturing process and / or technology used to form the structures. The skilled person can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0059] In the context of the present disclosure, when one layer / element is referred to as being located "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intervening layer / element therebetween. In addition, if one layer / element is located "on" another layer / element in one orientation, the layer / element can be located "under" the other layer / element when the orientation is reversed.

[0060] As described in the background, the III-V short-wave infrared focal plane pixels are limited by the substrate crystal quality and cannot avoid the problems of reverse domain, large lattice mismatch, and thermal mismatch, resulting in poor key indicators such as device responsivity and dark current.

[0061] To this end, the present application provides a 6°-bevel GOI substrate and a preparation method thereof, and a short-wave infrared focal plane pixel based on the substrate and a preparation method thereof.

[0062] The structure of the 6°-bevel GOI substrate provided by the present application is key to the "bevel angle" and the crystal quality of the germanium layer, and the structure includes a silicon substrate, a dielectric stack layer, and a 6°-bevel germanium layer from bottom to top.

[0063] In order to obtain the above high-quality 6°-bevel GOI substrate, the preparation process provided by the present application mainly includes four key stages of making a sacrificial substrate, making a support substrate, bonding, and removing excess layers, which are as follows.

[0064] I. Making a sacrificial substrate

[0065] First, a 6°-bevel silicon substrate is provided; the bevel angle of the substrate should be the same as the bevel angle of the required bevel germanium layer.

[0066] Then, a low-temperature germanium layer and a high-temperature germanium layer are formed in sequence on the 6°-bevel silicon substrate. In this step, the growth temperature of the low-temperature germanium layer and the high-temperature germanium layer can be in the range of 350-450℃ and 550-750℃, respectively. Meanwhile, if high-temperature annealing or cyclic annealing is increased, the crystal quality can be further improved. Of course, the annealing can be performed after the formation of the subsequent first dielectric layer. The annealing temperature is preferably controlled at 820℃, the annealing time is 10 min, and the annealing atmosphere is H2.

[0067] In addition, a compositionally graded germanium-silicon buffer layer can be added before the formation of the germanium layer. The use of a compositionally graded germanium-silicon buffer layer can further improve the crystal quality of the bevel germanium layer.

[0068] Next, a first dielectric layer is formed on the high-temperature germanium layer to obtain a sacrificial substrate. The first dielectric layer can be an aluminum oxide layer, a silicon oxide layer, a silicon oxynitride layer, or a stack of these layers. When selecting the material, on the one hand, the resonant cavity effect should be considered, and on the other hand, the difficulty and stability of bonding the support substrate can also be considered. Therefore, the present application preferably uses aluminum oxide.

[0069] II. Fabricating to support substrate

[0070] First, a silicon substrate is provided. The substrate is a non-bevelled substrate.

[0071] Then a second dielectric layer is formed on the silicon substrate to obtain a support substrate.

[0072] In the above fabrication of the sacrificial substrate and the support substrate, the forming means of each dielectric layer includes but is not limited to CVD, ALD, PCVD, PECVD, thermal oxidation method, etc.

[0073] III. Bonding

[0074] The sacrificial substrate and the support substrate are bonded with the first dielectric layer and the second dielectric layer as the bonding surface. The bonding is usually performed by fusion bonding.

[0075] IV. Removing excess layers

[0076] The bevelled 6° silicon substrate and the low-temperature germanium layer are removed in sequence. The removal means includes but is not limited to CMP, dry etching, wet etching, etc. or a combination of multiple means. It is preferred that different means are used for different materials, for example, the bevelled silicon substrate is removed by grinding or dry etching, and the low-temperature germanium layer is removed by TMAH etching method.

[0077] Then the surface of the high-temperature germanium layer is optionally subjected to a planarization treatment to reduce the roughness, which is usually performed by CMP.

[0078] When the above-obtained bevelled 6° GOI substrate is used to fabricate a short-wave infrared focal plane pixel, the subsequent process further includes the following main steps:

[0079] First, a GaAs buffer layer is formed on the bevelled 6° GOI substrate. The GaAs buffer layer is preferably formed by a low-temperature-moderate-temperature-high-temperature three-step method, and the low-temperature, moderate-temperature and high-temperature ranges are 390-410℃, 580-610℃ and 660-680℃, respectively, and the low-temperature, moderate-temperature and high-temperature ranges are preferably 400℃, 600℃ and 670℃, respectively.

[0080] Then, a PIN stack structure is formed on the GaAs buffer layer. The stack structure can be a horizontal or vertical stack, and the order of the P-type layer and the N-type layer is arbitrary. Meanwhile, the PIN stack structure of the present application adopts III-V group materials.

[0081] Then, the N-type contact structure and the P-type contact structure are formed, respectively. The contact structure, i.e. ohmic contact, can adopt mesa or contact hole, etc., and mesa is preferred.

[0082] Finally, a two-dimensional crystal is optionally formed.

[0083] Based on the core of the above-mentioned scheme, the present application further provides the following preferred embodiments.

[0084] Example 1: Fabricating a 6°-bevel GOI substrate

[0085] Fabricating a sacrificial substrate stage:

[0086] Step S1: Forming a 6°-bevel low-temperature germanium buffer layer 2 on the 6°-bevel silicon substrate 1 as shown in Fig. 1(a), and then forming a 6°-bevel high-temperature germanium buffer layer 3 as shown in Fig. 1(b). Figure 1 Figure 2 The growth temperature of the low-temperature and high-temperature is 350-450℃ and 550-750℃ respectively.

[0087] Step S2: Forming an aluminum oxide layer 4 on the 6°-bevel high-temperature germanium buffer layer 3 by ALD method, to obtain a sacrificial substrate as shown in Fig. 1(c). Figure 3

[0088] Fabricating a support substrate stage:

[0089] Step S3: Forming a silicon oxide layer 6 on another ordinary silicon substrate 5 by thermal oxidation method as shown in Fig. 2(a). Figure 4

[0090] Step S4: Forming a TEOS layer 7 on the silicon oxide layer 6 by TEOS method, to obtain a support substrate as shown in Fig. 2(b). Figure 5

[0091] Bonding and removing extra layers:

[0092] Step S5: Fusing bonding the sacrificial substrate and the support substrate with the aluminum oxide layer 4 and the TEOS layer 7 as the bonding surface as shown in Fig. 3(a). Figure 6

[0093] Step S6: Then removing the 6°-bevel silicon substrate 1 by grinding or dry etching as shown in Fig. 3(b). Figure 7

[0094] Step S7: Removing the 6°-bevel low-temperature germanium buffer layer 2 by TMAH etching method as shown in Fig. 4(a). Figure 8

[0095] Step S8: CMP processing the surface of the 6°-bevel high-temperature germanium buffer layer 3 until the thickness reaches 100-500nm, and the defect density can be as low as 10 7 cm -2 order of magnitude.

[0096] Example 2: Fabricating a short-wave infrared focal plane pixel

[0097] Firstly, forming a GaAs buffer layer 8 on the 6°-bevel GOI substrate obtained in Example 1 as shown in Fig. 5(a).​​​​​​​Figure 9 The forming method is a three-step method of low temperature (400℃) - medium temperature (600℃) - high temperature (670℃).

[0098] The second step is to form a PIN stack structure on the GaAs buffer layer 8: from bottom to top, the P-type III-V material layer 9, the III-V short-wave infrared absorption layer 10, and the N-type III-V material layer 11, as shown in FIG. 2. Figure 10

[0099] The third step is to perform a patterning process on the PIN stack structure, to form a structure as shown in FIG. 3. Figure 11

[0100] The fourth step is to perform a surface passivation process on the formed PIN stack structure, and the passivation layer is 12, as shown in FIG. 4. Figure 12

[0101] The fifth step is to form the N-type contact structure and the P-type contact structure respectively: etching a contact hole in the passivation layer, so as to deposit metals 13 and 14 at the exposed parts of the P-type III-V material layer 9 and the N-type III-V material layer 11, as shown in FIG. 5. Figure 13

[0102] The sixth step is to form a two-dimensional crystal, which is not shown in the figure, and is appropriately adjusted according to actual needs.

[0103] The above describes the embodiments of the present disclosure. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.​​​​

Claims

1. A short-wave infrared focal plane pixel, comprising: The application relates to a 6-degree bevel GOI substrate, which comprises a silicon substrate, a dielectric stack layer and a 6-degree bevel germanium layer from bottom to top. A GaAs buffer layer is arranged on the 6-degree bevel GOI substrate; the GaAs buffer layer is formed by a low-temperature-middle-temperature-high-temperature three-step method, and the low-temperature, the middle-temperature and the high-temperature are respectively in the ranges of 390-410 DEG C, 580-610 DEG C and 660-680 DEG C. N-type contact structure and P-type contact structure are respectively formed on the N layer and the P layer of the PIN stack structure to realize ohmic contact. a PIN stack structure on the GaAs buffer layer and employing III-V materials, the PIN stack structure being: N + - InGaAs / I-InGaAs / P + - InGaAs, N + - InP / I-InGaAs / P + - InP, P + - GaAsSb / I-InGaAs / N + - InP, N + - GaAs / I-AlGaAs / InGaAs multiple quantum well / P + - GaAs, N + - GaAs / I-AlGaAs / InGaAs multiple quantum dot / P + - GaAs; The PIN stack structure is a vertical stack structure.

2. The SWIR focal plane pixel of claim 1, wherein, The dielectric stack layer is a stack of multiple layers of silicon oxide, or a cross stack of silicon oxide and aluminum oxide, or a stack of multiple layers of aluminum oxide.

3. The short-wave infrared focal plane pixel of any of claims 1-2, wherein, The thickness of the 6-degree bevel germanium layer is 100-500 nm. The application further relates to a preparation method of the 6-degree bevel GOI substrate. A 6-degree bevel silicon substrate is provided, and a low-temperature germanium layer and a high-temperature germanium layer are sequentially formed on the 6-degree bevel silicon substrate.

4. A method of fabricating a short-wave infrared focal plane pixel, comprising: A first dielectric layer is formed on the high-temperature germanium layer to obtain a sacrifice substrate. A silicon substrate is provided. A second dielectric layer is formed on the silicon substrate to obtain a support substrate. The sacrifice substrate and the support substrate are bonded with the first dielectric layer and the second dielectric layer as the bonding surfaces. Then, the 6-degree bevel silicon substrate and the low-temperature germanium layer are removed in sequence. The surface of the high-temperature germanium layer is subjected to a planarization treatment. A GaAs buffer layer is formed on the 6-degree bevel GOI substrate; the GaAs buffer layer is formed by a low-temperature-middle-temperature-high-temperature three-step method, and the low-temperature, the middle-temperature and the high-temperature are respectively in the ranges of 390-410 DEG C, 580-610 DEG C and 660-680 DEG C. N-type contact structure and P-type contact structure are respectively formed on the N layer and the P layer of the PIN stack structure to realize ohmic contact. The low-temperature, the middle-temperature and the high-temperature are respectively 400 DEG C, 600 DEG C and 670 DEG C. forming a PIN stack on the GaAs buffer layer; the PIN stack is of III-V materials, the PIN stack is: N + - InGaAs / I - InGaAs / P + - InGaAs, N + - InP / I - InGaAs / P + - InP, P + - GaAsSb / I - InGaAs / N + - InP, N + - GaAs / I - AlGaAs / InGaAs multiple quantum well / P + - GaAs, N + - GaAs / I - AlGaAs / InGaAs multiple quantum dot / P + - GaAs ; After the N-type contact structure and the P-type contact structure are formed, a two-dimensional crystal is formed.

5. The preparation method according to claim 4, characterized in that, Before the N-type contact structure and the P-type contact structure are formed, the PIN stack structure is subjected to a patterning treatment to form a mesa; the mesa exposes the layers of the PIN stack structure close to the GaAs buffer layer.

6. The production method according to any one of claims 4 to 5, characterized by, The first dielectric layer and the second dielectric layer are independently formed by using at least one of silicon oxide, aluminum oxide or TEOS.

7. The production method according to any one of claims 4 to 5, characterized by, The second dielectric layer is a stack of multiple layers of materials.

8. The method of any one of claims 4-5, wherein, The first dielectric layer is formed by using an ALD method. The second dielectric layer is formed by using at least one of a thermal oxidation method and a CVD method.

9. The method of any one of claims 4-5, wherein, The 6-degree bevel silicon substrate is removed by using grinding and polishing or dry etching. The low-temperature germanium layer is removed by using a TMAH etching method.

10. The method of any one of claims 4-5, wherein, Before the low-temperature germanium layer is formed, a composition-gradually-changing germanium-silicon buffer layer is formed on the 6-degree bevel silicon substrate. When the high-temperature germanium layer is formed, high-temperature annealing or cyclic annealing treatment is performed; the high-temperature annealing is performed at a temperature of 820 DEG C for 10 min in an H2 atmosphere.

11. The method of any one of claims 4-5, wherein, The growth temperature of the high-temperature germanium layer is 550-750 DEG C, and the growth temperature of the low-temperature germanium layer is 350-450 DEG C.

12. The method of any one of claims 4-5, wherein, ​ 13. The method of any one of claims 4-5, wherein, ​

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