Wafer preparation method for increasing wafer strength

Abstract

An embodiment of the present invention provides a wafer preparation method for increasing wafer strength, comprising: performing ion beam implantation on the back side of the wafer after wafer grinding; performing high-temperature annealing on the back side of the wafer after ion beam implantation; preparing a plurality of raised metal blocks on the front side of the wafer, with the multiple metal blocks evenly spaced at predetermined lateral and longitudinal intervals; cutting the wafer; and cleaning the cut wafer. This technical solution effectively improves wafer strength by introducing an ion beam implantation process and a high-temperature annealing process, and providing a polyimide layer on the wafer metal layer, making the wafer less susceptible to cracking during subsequent wafer thinning processes.

Description

Technical Field

[0001] The present invention relates to the technical field of wafer manufacturing, and in particular to a wafer preparation method for increasing wafer strength. Background Art

[0002] In integrated circuit manufacturing, in order to reduce device thermal resistance, improve working heat dissipation and cooling capacity, and facilitate packaging, after the integrated circuit is manufactured on the front side of the silicon wafer, the back side needs to be thinned. However, wafer grinding will deteriorate the surface integrity. At this time, chemical mechanical methods are needed to polish the wafer to make one side as smooth as a mirror. Due to the characteristics of the wafer itself and the requirements of production costs, the grinding force cannot be too small, otherwise the grinding time will be too long. The grinding force cannot be too large either, because the wafer is a very thin glass product. Excessive grinding force can easily cause wafer breakage. Therefore, Taiko (Tai KO) and other grinding (thinning) processes are currently commonly used. After using this type of thinning process, a smooth transition edge will be formed on one side of the wafer, and the wafer will be thinner in the center and thicker at the gently sloping edge.

[0003] In the process of implementing the present invention, the inventors discovered that the prior art has at least the following problems:

[0004] During wafer preparation after thinning, when the wafer needs to be placed with the smooth transition side facing downward, the center of the wafer will be suspended. Since the wafer thickness has been reduced to a very thin layer, the wafer strength is low, which greatly increases the probability of wafer cracking at the suspended part. Therefore, how to improve the strength of the wafer to prevent wafer cracking during the wafer preparation process after thinning is a problem that needs to be solved. Summary of the Invention

[0005] An embodiment of the present invention provides a wafer preparation method for increasing wafer strength, so as to solve the problem in the prior art that wafers that have undergone a thinning process are prone to cracking during subsequent preparation processes.

[0006] To achieve the above-mentioned purpose, a wafer preparation method for increasing wafer strength includes: after completing wafer grinding, performing ion beam implantation on the wafer from the back side of the wafer, the back side of the wafer refers to the unground surface on the wafer; performing high-temperature annealing on the wafer after completing the ion beam implantation; preparing a plurality of raised metal blocks on the front side of the wafer, the plurality of metal blocks are evenly distributed at preset lateral intervals and preset longitudinal intervals, the front side of the wafer refers to the ground surface on the wafer; cutting the wafer; and cleaning the wafer after cutting.

[0007] Furthermore, after the high-temperature annealing is performed on the wafer after the ion beam implantation, the method further includes: preparing a wafer metal layer on the back side of the wafer.

[0008] Furthermore, after preparing the wafer metal layer on the back side of the wafer, the method further includes: preparing a first polyimide layer on the wafer metal layer.

[0009] Furthermore, before cutting the wafer, it also includes: reserving a circular top space with a preset radius on the top surface of each metal block; preparing a second polyimide layer for each metal block, and making the second polyimide layer cover the side surfaces of the metal block and the top surface outside the circular top space; and preparing a rare metal layer in each circular top space.

[0010] Furthermore, the ion beam implantation on the wafer specifically includes: selecting boron ions and phosphorus ions as implantation ions; and performing ion beam implantation after controlling the temperature of the ions at 600° C. to 700° C.

[0011] Furthermore, the temperature range of the high temperature annealing is 300° C. to 700° C.; and the time range of the high temperature annealing is 0.5 h to 3 h.

[0012] Furthermore, the thickness of the first polyimide layer is in the range of 5 to 10 μm.

[0013] Furthermore, any one of the following materials is selected when preparing the rare metal layer: nickel-silver alloy Ni / Au, or palladium-silver alloy Pd / Au, or p-type aluminum gallium nitride p-AlGaN.

[0014] Furthermore, the cutting of the wafer includes: selecting a transverse cutting position between any two adjacent rows of the metal blocks; selecting a longitudinal cutting position between any two adjacent columns of the metal blocks; and cutting the wafer, the wafer metal layer and the first polyimide layer in sequence along the transverse cutting position and the longitudinal cutting position.

[0015] Furthermore, the cleaning of the wafer after cutting includes: removing the metal layer of the wafer; and removing the first polyimide layer.

[0016] The above technical solution has the following beneficial effects:

[0017] This technical solution adds a high-temperature annealing process to the wafer preparation process to reduce hardness, improve machinability, reduce residual stress, and minimize deformation and cracking tendencies. At the same time, an ion beam implantation process is introduced to complement the high-temperature annealing process to eliminate the adverse effects of high-temperature annealing, effectively improving the problem of wafer cracking. Furthermore, this technical solution adds a polyimide layer to the wafer metal layer to effectively eliminate the thermal stress generated by the wafer metal layer after high-temperature annealing, thereby indirectly improving the wafer strength and making the wafer less susceptible to cracking during the subsequent thinning process. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 This is a flow chart of a wafer preparation method for increasing wafer strength according to an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of the first preparation process in a specific embodiment of the present invention:

[0021] Figure 3 This is a schematic diagram of the second preparation process in a specific embodiment of the present invention:

[0022] Figure 4 This is a schematic diagram of the third preparation process in a specific embodiment of the present invention:

[0023] Figure 5 This is a schematic diagram of the fourth preparation process in a specific embodiment of the present invention:

[0024] Figure 6 This is a schematic diagram of the fifth preparation process in a specific embodiment of the present invention:

[0025] Figure 7 This is a schematic diagram of the sixth preparation process in a specific embodiment of the present invention:

[0026] Figure 8 This is a schematic diagram of the seventh preparation process in a specific embodiment of the present invention:

[0027] Figure 9 This is a schematic diagram of the eighth preparation process in a specific embodiment of the present invention:

[0028] Figure 10 This is a schematic diagram of the ninth preparation process in a specific embodiment of the present invention:

[0029] Figure 11 This is a schematic diagram of the 10th preparation process in a specific embodiment of the present invention:

[0030] Figure 12 This is a schematic diagram of the 11th preparation process in a specific embodiment of the present invention:

[0031] Figure 13 This is a schematic diagram of the 12th preparation process in a specific embodiment of the present invention:

[0032] Figure 14This is a schematic diagram of the 13th preparation process in a specific embodiment of the present invention:

[0033] Reference numerals: 1. wafer; 2. first carrier; 3. second carrier; 4. first cutting frame; 5. second cutting frame; 11. wafer metal layer; 12. first polyimide layer; 13. metal block; 14. first polyimide layer; 15. rare metal layer. DETAILED DESCRIPTION

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0035] like Figure 1 As shown, the present invention provides a wafer preparation method for increasing wafer strength, comprising:

[0036] S101, after wafer grinding is completed, performing ion beam implantation on the wafer from the back side of the wafer, where the back side of the wafer refers to the unground surface of the wafer;

[0037] S102, performing high temperature annealing on the wafer after the ion beam implantation;

[0038] S103, preparing a plurality of square raised metal blocks on the front side of the wafer, wherein the plurality of metal blocks are evenly distributed at preset horizontal intervals and preset vertical intervals, wherein the front side of the wafer refers to the ground surface of the wafer;

[0039] S104, cutting the wafer;

[0040] S105: Clean the cut wafers.

[0041] As mentioned above, in the wafer preparation process of the prior art, the wafer has the problems of low strength, high hardness, high brittleness and easy cracking. In order to solve this problem, in this application, a high-temperature annealing process is added in addition to the conventional preparation process. High-temperature annealing can refine the grains, adjust the structure, and eliminate tissue defects, thereby reducing hardness and improving machinability. At the same time, it can also reduce residual stress, stabilize the size, reduce deformation and crack tendency, and thus solve the aforementioned problems. However, it has been confirmed by actual measurements that it is difficult to achieve better technical effects by simply adding a high-temperature annealing process. In this application, an ion beam implantation process is also introduced before high-temperature annealing, which can effectively improve the effect of the subsequent high-temperature annealing process. Since too high a temperature will cause defects to the wafer, in this application, the temperature required for ion beam implantation is relatively low. More importantly, the ion beam implantation process is controllable and therefore easy to implement.

[0042] Furthermore, after step S102, the method further includes:

[0043] S1021. Prepare a wafer metal layer on the back side of the wafer.

[0044] Typically, due to the needs of certain processes, a wafer metal layer needs to be prepared on the back of the wafer to facilitate the implementation of certain processes. After the wafer preparation is completed, the wafer metal layer needs to be removed. There are many types of wafer metal layers, and the types and contents of metals contained in different wafer metal layers are also different. They generally contain copper, tin, nickel, zinc, aluminum, chromium, lead, mercury, silver, and gold, and exist in various forms of elements and compounds; there are also different types in physical form, including alloys, platings, and so on.

[0045] Furthermore, after step S1021, the method further includes:

[0046] S1022. Prepare a first polyimide layer on the wafer metal layer.

[0047] After annealing is completed, the wafer metal layer is prepared. The metal will expand due to heat, and then generate thermal stress after cooling. Thermal stress will cause the wafer to crack in the subsequent steps. Therefore, in this application, a first polyimide layer is prepared on the wafer metal layer. This polyimide layer can promptly eliminate the thermal stress in the wafer metal layer. After the thermal stress is reduced, the wafer is less likely to crack, which is equivalent to indirectly improving the strength of the wafer.

[0048] Furthermore, before step S104, the method further includes:

[0049] S1031. Reserve a circular top space with a preset radius on the top surface of each metal block;

[0050] S1032, preparing a second polyimide layer for each metal block, and making the second polyimide layer cover the side surfaces of the metal block and the top surface portion other than the circular top space;

[0051] S1033. Prepare a rare metal layer in each circular top space.

[0052] In order to further protect the wafer, the present application also provides a second polyimide layer on the front side of the wafer. This layer of material can act as a mask layer. It is not easy to corrode itself and can protect the parts of the wafer that do not need to be etched in subsequent work, preventing the parts that do not need to be etched from being etched, thereby also improving the strength of the wafer to a certain extent. In order to facilitate the non-polarized electroplating of the rare metal layer, when preparing the second polyimide layer, the top of the metal block cannot be sealed, but a circular top space with a preset radius must be left on the top surface of each metal block. At the same time, the second polyimide layer covering the outside of each two adjacent metal blocks does not contact each other. In the horizontal and vertical directions, the second polyimide layer has a hollow area, which corresponds to the cutting position during the subsequent wafer cutting.

[0053] Furthermore, the step S101 specifically includes:

[0054] S1011, selecting boron ions and phosphorus ions as implanted ions;

[0055] S1012, controlling the temperature of the ions at 600°C to 700°C for ion beam implantation.

[0056] Furthermore, the temperature range of the high temperature annealing is 300° C. to 700° C.; and the time range of the high temperature annealing is 0.5 h to 3 h.

[0057] Furthermore, the thickness of the first polyimide layer is in the range of 5 to 10 μm.

[0058] It has been confirmed by actual measurements that when the temperature of the ions, the process parameters of the high-temperature annealing and the thickness of the first polyimide layer are controlled within the above ranges, better implementation effects can be achieved.

[0059] Furthermore, the material of the rare metal layer is any one of the following materials:

[0060] Nickel silver alloy Ni / Au, or palladium silver alloy Pd / Au, or p-type aluminum gallium nitride p-AlGaN.

[0061] Nickel-silver alloy and palladium-silver alloy are rare metal layer materials commonly used in the prior art, while p-type aluminum gallium nitride is a new type of rare metal layer material used in this application.

[0062] Furthermore, the step S104 includes:

[0063] S1041. Select a transverse cutting position between any two adjacent rows of metal blocks;

[0064] S1042. Selecting a longitudinal cutting position between any two adjacent rows of metal blocks;

[0065] S1043 , cutting the wafer, the wafer metal layer, and the first polyimide layer in sequence along the transverse cutting position and the longitudinal cutting position.

[0066] The cutting position is the hollow area reserved between two adjacent metal blocks when the second polyimide layer is laid.

[0067] Furthermore, the step S105 includes:

[0068] S1051, removing the metal layer of the wafer;

[0069] S1052, removing the first polyimide layer.

[0070] Since the wafer metal layer is only used as an auxiliary facility for certain specific processes (which are not directly related to the technical problems to be solved in this application and will not be described in detail in this application), it can be removed after all wafer preparation work is completed; correspondingly, the purpose of the first polyimide layer is to eliminate the thermal stress generated in the wafer metal layer during high and low temperature changes. After the wafer preparation is completed, it no longer plays a role and needs to be removed.

[0071] The wafer preparation method of the present invention is described below using a specific example of preparing a MOS transistor wafer. The preparation process of this example is as follows:

[0072] Step 1: Figure 2 As shown, a smooth transition wafer 1 that has undergone a thinning process is placed in a groove of a carrier (i.e., the first carrier 2), with the back side of the wafer 1 (i.e., the unground surface) facing upward, and the back side of the wafer 1 is sequentially subjected to ion beam implantation and high-temperature annealing processes.

[0073] In this step, the implanted ions include B (boron) ions and P (phosphorus) ions, and the preset temperature range for activating the ions is 600-700° C. The temperature cannot be too high, otherwise it may affect the subsequent annealing process.

[0074] When the wafer 1 is annealed, the annealing temperature is 300 to 700 degrees, and the annealing time is 0.5 to 3 hours. After annealing at 450°C, the single crystal silicon will introduce multiple acceptor energy levels in the band gap. After annealing at above 650°C, the quadrivacancy defects in the single crystal silicon disappear quickly, and the conductivity type begins to recover. Through preheating treatment, the formation of thermal donors in the irradiated single crystal silicon can be slowed down or suppressed.

[0075] Step 2: Figure 2 As shown, after the high temperature annealing process is completed, a metal layer (wafer metal layer 11 ) is prepared on the back side of the wafer 1 .

[0076] Step 3: Figure 3As shown, Polyimide 1 (i.e., first polyimide layer 12) is formed on the back side of wafer 1, completely covering the wafer metal layer 11. The thickness of first polyimide layer 12 is controlled to be between 5μm and 10μm, ensuring a certain flatness on the back side of wafer 1. First polyimide layer 12 effectively protects wafer 1, improving its mechanical properties, preventing chemical corrosion, and effectively increasing its moisture resistance. This layer also provides a buffering function, effectively reducing cracking of wafer 1 caused by thermal stress generated during annealing of the wafer metal layer 11, thereby minimizing damage to wafer 1 during subsequent processing, packaging, and post-processing.

[0077] Step 4: Figure 4 As shown, the first carrier 2 is flipped over and the wafer (1) is transferred to another carrier (ie, the second carrier 3) so that the front side of the wafer 1 faces upward.

[0078] Step 5: Figure 5 As shown, metal blocks 13 are generated on the front side of the wafer 1. In this step, the metal blocks 13 are evenly distributed on the front side of the wafer 1. The metal blocks 13 may be Al Pads, and the preparation process may be photolithography, electrochemical deposition and growth.

[0079] Step 6: Figure 6 As shown, Polyimide 2 (i.e., a second polyimide layer 14) is formed on the front surface of wafer 1. The second polyimide layer 14 covers the sides of each metal block 13 and the periphery of the top of the metal block 13, leaving only a circular top space with a preset radius in the center of the top. The second polyimide layer 14 covering the exteriors of each two adjacent metal blocks 13 does not contact each other, but instead leaves hollow areas in both the horizontal and vertical directions. These hollow areas correspond to the cutting positions during subsequent wafer dicing. To ensure good coverage of wafer 1, the laying range of the second polyimide layer 14 can be appropriately enlarged so that it completely covers wafer 1 while also extending outside of wafer 1.

[0080] Step 7: Figure 7 As shown, the rare metal layer 15 is prepared in the circular top space on the top of the metal block 13, and materials such as Ni / Au, Pd / Au, and p-AlGaN can be used for electroless plating.

[0081] Step 8: Figure 8 As shown, the wafer 1 is cut by using a laser cutting process, and the wafer 1 is first cut through the hollowed-out area on the surface of the second polyimide layer 14 corresponding to the cutting line position.

[0082] Step 9: Figure 9As shown, the laser cutting process is used to sequentially cut the wafer metal layer 11 and the first polyimide layer 12 on the back of the wafer 1. In this application, by utilizing the selection ratio of the first polyimide layer and the wafer, the wafer 1 can be directly cut while still having the first polyimide layer.

[0083] Step 10: Figure 10 As shown, the cut wafer 1 is turned over so that its front side is attached to a Cutting frame (ie, the first cutting frame 4).

[0084] Step 11: Figure 11 As shown, the second carrier 3 on the back side of the wafer 1 is removed, the redundant portion cut off around the wafer 1 is removed, and the second polyimide layer 14 originally covering the outer side around the front side of the wafer 1 and now cut off is removed.

[0085] Step 12: Figure 12 、 Figure 13 As shown, the first polyimide layer 12 and the wafer metal layer 11 on the back side of the wafer 1 are removed in sequence, and then the back side of the wafer 1 is attached to another Cutting frame (ie, the second Cutting frame 5).

[0086] Step 13: Figure 14 As shown, the first cutting frame 4 is removed to complete the wafer preparation.

[0087] It should be understood that the specific order or hierarchy of steps in the disclosed processes is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged without departing from the scope of the present disclosure. The accompanying method claims present elements of the various steps in an exemplary order and are not intended to be limited to the specific order or hierarchy described.

[0088] In the foregoing detailed description, various features are grouped together in a single embodiment to simplify the disclosure. This method of disclosure should not be interpreted as reflecting an intention that embodiments of the claimed subject matter require more features than are expressly recited in each claim. On the contrary, as reflected in the appended claims, the invention comprises less than all the features of any individual disclosed embodiment. The appended claims are hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate preferred embodiment of the invention.

[0089] The above description of the disclosed embodiments is intended to enable any person skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is not limited to the embodiments presented herein but is intended to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0090] The foregoing description includes examples of one or more embodiments. Of course, it is not possible to describe all possible combinations of components or methods for the purposes of describing the above embodiments, but one of ordinary skill in the art will recognize that the various embodiments may be further combined and arranged. Therefore, the embodiments described herein are intended to encompass all such changes, modifications and variations that fall within the scope of the appended claims. Furthermore, to the extent the term "comprising" is used in the specification or claims, the term is intended to be encompassed in a manner similar to the term "including," as explained in terms of "including," used as a transitional word in the claims. Furthermore, any use of the term "or" in the specification of the claims is intended to mean a "non-exclusive or."

[0091] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A wafer preparation method for increasing wafer strength, characterized in that: include: After the wafer is ground, ion beam implantation is performed on the wafer from the back side of the wafer, where the back side of the wafer refers to the unground surface of the wafer; performing high temperature annealing on the wafer after the ion beam implantation; Preparing a plurality of raised metal blocks on the front side of a wafer, and distributing the plurality of metal blocks evenly at predetermined lateral and longitudinal intervals, wherein the front side of the wafer refers to the ground surface of the wafer; cutting the wafer; Cleaning the wafer after cutting; The ion beam implantation on the wafer specifically includes: Boron ions and phosphorus ions are selected as implanted ions; Controlling the temperature of the implanted ions to be between 600° C. and 700° C. for ion beam implantation; The temperature range of the high temperature annealing is 300° C. to 700° C.; the time range of the high temperature annealing is 0.5 h to 3 h; After the wafer having undergone ion beam implantation is subjected to high temperature annealing, the method further comprises: preparing a wafer metal layer on the back side of the wafer; preparing a first polyimide layer on the wafer metal layer; The thickness of the first polyimide layer is in the range of 5 to 10 μm.

2. The wafer preparation method according to claim 1, wherein: Before cutting the wafer, the method further includes: A circular top space with a preset radius is reserved on the top surface of each metal block; preparing a second polyimide layer for each of the metal blocks, and making the second polyimide layer cover the side surfaces of the metal block and the portion of the top surface of the metal block except the circular top space; A rare metal layer is prepared in each of the circular top spaces.

3. The wafer preparation method according to claim 1, wherein: The step of cutting the wafer comprises: Selecting a transverse cutting position between any two adjacent rows of the metal blocks; Selecting a longitudinal cutting position between any two adjacent rows of metal blocks; The wafer, the wafer metal layer and the first polyimide layer are sequentially cut along the transverse cutting position and the longitudinal cutting position.

4. The wafer preparation method according to claim 1, wherein: The step of cleaning the cut wafers comprises: removing the wafer metal layer; The first polyimide layer is removed.

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