Semiconductor structure and method of manufacturing the same
By forming an arc-shaped sidewall on the opening sidewall and removing the second material layer using wet etching, the problem of material residue inside the opening is solved, and the performance and reliability of the device are improved.
Patent Information
- Application Number
- CN202210797573.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-07-08
- Publication Date
- 2025-11-25
- Estimated Expiration
- 2042-07-08
AI Technical Summary
After depositing the material to be etched on the surface of a structure with a height difference, such as an opening, it is difficult to completely remove the material to be etched inside the opening, resulting in material residue and affecting device performance.
An exposed arc-shaped sidewall is formed on the sidewall of the opening, and a second material layer inside the opening is covered by the gently sloping sidewall. The second material layer is removed by wet etching to avoid leaving residue at the bottom of the opening.
Effective removal of the second material layer inside the opening ensures device performance and improves device reliability.
Smart Images
Figure CN115206791B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a preparation method thereof. BACKGROUND
[0002] For the structure with height difference, such as opening, after the deposition of the material to be etched on the surface of the obtained structure, it is difficult to completely remove the material to be etched in the opening when etching to remove the material to be etched in the opening, and the material to be etched is easily left at the bottom of the opening, thereby affecting the performance of the device. SUMMARY
[0003] Based on the problem in the prior art that after the deposition of the material to be etched in the structure with height difference such as opening, the material to be etched is easily left at the bottom of the opening when etching to remove the material to be etched in the opening, thereby affecting the performance of the device, it is necessary to provide a semiconductor structure and a preparation method thereof for solving the above-mentioned problems in the prior art.
[0004] The first aspect of the present application provides a preparation method of a semiconductor structure, comprising:
[0005] providing a substrate, an upper surface of the substrate is formed with a first material layer, the first material layer has an opening therein, and the opening exposes the upper surface of the substrate;
[0006] forming a side wall on the opposite sidewall surface of the opening, and the exposed surface of the side wall is an arc surface;
[0007] forming a second material layer, the second material layer at least covers the upper surface of the first material layer and fills the opening;
[0008] removing the second material layer on the upper surface of the first material layer and in the opening.
[0009] In the above preparation method of the semiconductor structure, the side wall with the arc-shaped exposed surface is first formed on the sidewall of the opening, the slope of the side wall is relatively gentle, when the second material layer is formed in the opening, the slope of the second material layer on the side wall is also relatively gentle, and when etching to remove the second material layer in the opening, the second material layer in the opening is easily completely removed, thereby avoiding the residue of the second material layer at the bottom of the opening, and further ensuring the performance of the device and improving the reliability of the device.
[0010] In one of the embodiments, the substrate comprises a temperature sensor region and a die region adjacent to the temperature sensor region, and the first material layer is located on the upper surface of the temperature sensor region.
[0011] In one of the embodiments, the first material layer comprises an intrinsic polysilicon layer.
[0012] In one embodiment, the sidewall opposite to the opening forms a side wall, and a surface of the side wall exposed is an arc surface, comprising:
[0013] forming a first hard mask layer, the first hard mask layer covering an upper surface of the first material layer and filling the opening;
[0014] forming a second hard mask layer on a surface of the first hard mask layer;
[0015] etching the second hard mask layer and the first hard mask layer to form the side wall.
[0016] In one embodiment, the forming of the first hard mask layer covering the upper surface of the first material layer and filling the opening comprises:
[0017] forming a first hard mask material layer, the first hard mask material layer covering the upper surface of the first material layer and filling the opening;
[0018] performing thinning treatment on the first hard mask material layer to obtain the first hard mask layer.
[0019] In one embodiment, the etching of the second hard mask layer and the first hard mask layer to form the side wall comprises:
[0020] etching the first hard mask layer and the second hard mask layer to form a deep groove, the deep groove being located in the opening;
[0021] adopting a wet etching process to remove the second hard mask layer, the first hard mask layer on the upper surface of the first material layer and part of the first hard mask layer in the opening, and the first hard mask layer in the opening remaining as the side wall.
[0022] In one embodiment, the first hard mask layer and the second hard mask layer are both TEOS layers.
[0023] The second aspect of the present application further provides a semiconductor structure, comprising:
[0024] a substrate;
[0025] a first material layer located on an upper surface of the substrate, the first material layer having an opening therein, the opening exposing the upper surface of the substrate;
[0026] a side wall located on a surface of a side wall opposite to the opening, a surface of the side wall exposed being an arc surface.
[0027] In the semiconductor structure, the side wall of the opening is arc-shaped, the slope of the side wall is gentle, and the slope of the second material layer on the side wall is also gentle when the second material layer is formed in the opening. When the second material layer in the opening is removed by etching, the second material layer in the opening can be completely removed, thereby avoiding the residual of the second material layer at the bottom of the opening, and ensuring the performance of the device and improving the reliability of the device.
[0028] In one of the embodiments, the substrate includes a temperature sensor region and a die region adjacent to the temperature sensor region, and the first material layer is located on an upper surface of the temperature sensor region.
[0029] In one of the embodiments, the substrate includes a silicon substrate, the first material layer includes an intrinsic polysilicon layer, and the side wall includes a TEOS side wall. BRIEF DESCRIPTION OF DRAWINGS
[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings of other embodiments can be obtained by those skilled in the art without creative labor.
[0031] Figure 1 The flow chart of the preparation method of the semiconductor structure provided in an embodiment of the present application.
[0032] Figure 2 The cross-sectional structure schematic diagram of the structure obtained in step S10 of the preparation method of the semiconductor structure provided in an embodiment of the present application.
[0033] Figure 3 The flow chart of step S20 of the preparation method of the semiconductor structure provided in an embodiment of the present application.
[0034] Figures 4 to 7 The cross-sectional structure schematic diagram of the structure obtained in step S20 of the preparation method of the semiconductor structure provided in an embodiment of the present application.
[0035] Figure 8 The cross-sectional structure schematic diagram of the structure obtained in step S30 of the preparation method of the semiconductor structure provided in an embodiment of the present application.
[0036] Figure 9 The cross-sectional structure schematic diagram of the structure obtained in step S40 of the preparation method of the semiconductor structure provided in an embodiment of the present application; and Figure 9 It is also the cross-sectional structure schematic diagram of the semiconductor structure obtained in another embodiment of the present application.
[0037] Explanation of reference numerals in the attached figures: 10, substrate; 101, sensor region; 102, die region; 11, first material layer; 111, opening; 12, first hard mask material layer; 121, first hard mask layer; 13, second hard mask layer; 14, sidewall; 15, second material layer. Detailed Implementation
[0038] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0040] It is understood that the terms "first," "second," "third," "fourth," etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first control device may be referred to as a second control device, and similarly, a second control device may be referred to as a first control device. Both the first control device and the second control device are control devices, but they are not the same control device.
[0041] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.
[0042] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.
[0043] For structures with height difference, such as openings, etc., after the deposition of the material to be etched on the surface of the resulting structure, it is difficult to completely remove the material to be etched in the opening when etching to remove the material to be etched in the opening, and it is easy to have material to be etched remaining at the bottom of the opening, thereby affecting the performance of the device.
[0044] An improvement is to form a mask layer on the surface of the resulting structure after forming the opening, and after etching the mask layer, a side wall with a relatively steep exposed surface can be formed on the sidewall of the opening; after subsequent etching process, the side wall morphology will be more concave; after depositing a layer of polysilicon material to be etched in the opening, there will still be material to be etched remaining at the bottom of the opening after etching, thereby affecting the performance of the device.
[0045] Please refer to Figure 1 , the present application provides a preparation method of a semiconductor structure, comprising:
[0046] S10: providing a substrate, an upper surface of the substrate is formed with a first material layer, the first material layer has an opening therein, the opening exposes the upper surface of the substrate;
[0047] S20: forming a side wall on the opposite sidewall surface of the opening, the exposed surface of the side wall is an arc surface;
[0048] S30: forming a second material layer, the second material layer covers at least the upper surface of the first material layer and fills the opening;
[0049] S40: removing the second material layer on the upper surface of the first material layer and in the opening.
[0050] In the above preparation method of the semiconductor structure, by first forming a side wall with an arc-shaped exposed surface on the sidewall of the opening, the slope of the side wall is relatively gentle, when forming a second material layer in the opening, the slope of the second material layer on the side wall is also relatively gentle, and when etching to remove the second material layer in the opening, it is easy to completely remove the second material layer in the opening, thereby avoiding the residual of the second material layer at the bottom of the opening, and further ensuring the performance of the device and improving the reliability of the device.
[0051] In step S10, please refer to Figure 1 and Figure 2 , a substrate 10 is provided, an upper surface of the substrate 10 is formed with a first material layer 11, the first material layer 11 has an opening 111 therein, the opening 111 exposes the upper surface of the substrate 10.
[0052] Specifically, the substrate 10 can include but is not limited to a silicon substrate. In other examples, the substrate 10 can also be a sapphire substrate, a gallium nitride substrate, or a silicon carbide substrate, etc.
[0053] In one example, as Figure 2As shown, the substrate 10 can include a temperature sensor region 101 and a die region 102 adjacent to the temperature sensor region 101, and the first material layer 11 is located on the upper surface of the temperature sensor region 101.
[0054] Specifically, the temperature sensor region 101 can be a temperature sensor region of an on-vehicle IGBT (Insulated Gate Bipolar Transistor).
[0055] It should be noted that in other examples, the substrate 10 can also not be divided into regions, but only include one region; can also include a device region and an edge region, etc.; which is not limited here, and can be set and selected according to actual needs.
[0056] In one example, the thickness of the first material layer 11 can be set according to actual needs; specifically, the thickness of the first material layer 11 can be 5000 angstroms to 7000 angstroms, for example, the thickness of the first material layer 11 can be 5000 angstroms, 5500 angstroms, 6000 angstroms, 6500 angstroms or 7000 angstroms, etc.; in this embodiment, the thickness of the first material layer 11 can be 6000 angstroms.
[0057] In one example, the first material layer 11 includes but is not limited to an intrinsic polysilicon layer. Of course, in other examples, the first material layer 11 can also be a dielectric layer, etc.
[0058] In one example, the specific shape and size of the opening 111 can be set according to actual needs, which is not limited here.
[0059] In step S20, please refer to Figure 1 S20 step and Figures 3 to 7 , a side wall 14 is formed on the side wall surface opposite to the opening 111, and the exposed surface of the side wall 14 is an arc surface.
[0060] In one example, in step S20, the side wall 14 is formed on the side wall opposite to the opening 111, and the exposed surface of the side wall 14 is an arc surface, which can include:
[0061] S201: forming a first hard mask layer 121, the first hard mask layer 121 covers the upper surface of the first material layer 11 and fills the opening 111, as shown in Figure 4 and Figure 5 ;
[0062] S202: forming a second hard mask layer 13 on the surface of the first hard mask layer 121, as shown in Figure 6 ;
[0063] S203: etching the second hard mask layer 13 and the first hard mask layer 121 to form a side wall 14, as shown inFigure 7 As shown.
[0064] In one example, in step S201, the first hard mask layer 121 is formed, the first hard mask layer 121 covers the upper surface of the first material layer 11 and fills the opening 111, which can include:
[0065] S2011: forming a first hard mask material layer 12, the first hard mask material layer 12 covers the upper surface of the first material layer 11 and fills the opening 111, as shown in Figure 4 ;
[0066] S2012: thinning the first hard mask material layer 12 to obtain the first hard mask layer 121.
[0067] Specifically, in step S201, the first hard mask material layer 12 can be formed by physical vapor deposition process or chemical vapor deposition process, but not limited to, the thickness of the first hard mask material layer 12 can be set according to actual needs; specifically, the thickness of the first hard mask material layer 12 can be 8000 angstroms to 10000 angstroms, for example, the thickness of the first hard mask material layer 12 can be 8000 angstroms, 8500 angstroms, 9000 angstroms, 9500 angstroms or 10000 angstroms; in this embodiment, the thickness of the first hard mask material layer 12 can be 9000 angstroms.
[0068] In one example, the first hard mask material layer 12 can include but not limited to TEOS (tetraethyl orthosilicate) layer, and can also be a silicon oxide layer formed based on TEOS.
[0069] In one example, in step S2012, the first hard mask material layer 12 can be thinned by chemical mechanical polishing process, but not limited to, the thickness of the first hard mask layer 121 obtained after thinning can be set according to actual needs; specifically, the thickness of the first hard mask layer 121 can be 2000 angstroms to 4000 angstroms, for example, the thickness of the first hard mask layer 121 can be 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms or 4000 angstroms; specifically, in this embodiment, the thickness of the first hard mask layer 121 can be 3000 angstroms.
[0070] In one example, the thickness of the second hard mask layer 13 formed in step S202 can be set according to actual needs, specifically, the thickness of the second hard mask layer 13 can be 2000 angstroms to 4000 angstroms, specifically, the thickness of the second hard mask layer 13 can be 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms or 4000 angstroms, etc.
[0071] In one example, the second hard mask layer 13 can include but is not limited to a TEOS (tetraethyl orthosilicate) layer, and can also be a silicon oxide layer formed based on TEOS.
[0072] In one example, in step S203, the second hard mask layer 13 and the first hard mask layer 121 are etched to form the side wall 14, including:
[0073] S2031: a dry etching process is used to etch the first hard mask layer 121 and the second hard mask layer 13 to form a deep trench (not shown), which is located in the opening 111;
[0074] S2032: a wet etching process is used to remove the second hard mask layer 13, the first hard mask layer 121 on the upper surface of the first material layer 11, and part of the first hard mask layer 121 in the opening 111, and the first hard mask layer 121 remaining in the opening 111 is the side wall 14.
[0075] In this embodiment, the first hard mask material layer 12 is first formed, and then the first hard mask material layer 12 is thinned to obtain the first hard mask layer 121 with a relatively thin thickness, and then the second hard mask layer 13 is formed; by first etching the first hard mask layer 12 and the second mask layer 13 to form a deep trench, and then using a wet etching process to remove the second hard mask layer 13, the first hard mask layer 121 on the upper surface of the first material layer 11, and part of the first hard mask layer 121 in the opening 111, the surface of the side wall of the side wall 14 exposed is an arc surface with a relatively gentle slope, which can easily completely remove the second material layer formed in the subsequent opening 111, thereby avoiding the residue of the second material layer at the bottom of the opening 111, and further ensuring the performance of the device and improving the reliability of the device.
[0076] In one example, the first hard mask layer 121 can be a TEOS layer, and the second hard mask layer 13 can be a TEOS layer. Of course, in other examples, the first hard mask layer 121 can also be a silicon oxide layer formed based on TEOS, and the second hard mask layer 13 can also be a silicon oxide layer formed based on TEOS.
[0077] As an example, the side wall 14 can include but is not limited to a TEOS side wall, and can also be a silicon oxide side wall formed based on TEOS.
[0078] In step S30, please refer to Figure 1 S30 step and Figure 8 , the second material layer 15 is formed, which at least covers the upper surface of the first material layer 11 and fills the opening 111.
[0079] Specifically, the second material layer 15 can be formed by, but is not limited to, a physical vapor deposition process or a chemical vapor deposition process. The second material layer 15 can include, but is not limited to, a polysilicon layer. The second material layer 15 can be, but is not limited to, a doped polysilicon layer or an intrinsic polysilicon layer.
[0080] Specifically, the thickness of the second material layer 15 can be set according to actual needs. Specifically, the thickness of the second material layer 15 can be 7000 angstroms to 9000 angstroms, for example, the thickness of the second material layer 15 can be 7000 angstroms, 7500 angstroms, 8000 angstroms, 8500 angstroms or 9000 angstroms, and the like. In this embodiment, the thickness of the second material layer 15 can be 8000 angstroms.
[0081] It should be noted that when the substrate 10 also has other regions, the second material layer 15 covers the other regions in addition to the temperature sensor region 101. Figure 8 For example, the substrate in the temperature sensor region 101 and the die region 102, the second material layer 15 of this step can also cover the die region 102.
[0082] In step S40, please refer to Figure 1 and S40 in Figure 9 , the second material layer 15 located on the upper surface of the first material layer 11 and in the opening 111 is removed.
[0083] Specifically, the second material layer 15 located on the upper surface of the first material layer 11 and in the opening 111 can be removed by an etching process, but is not limited to this.
[0084] It should be noted that in step S30, the second material layer 15 can also cover the surface of the die region 102. The second material layer 15 can be used to form a device structure in the die region 102. For example, when the second material layer 15 is a polysilicon layer, the second material layer 15 is used to form a gate in the die region 102. At this time, in step S40, the second material layer 15 located on the upper surface of the first material layer 11 and in the opening 111 is removed, and part of the second material layer 15 located on the upper surface of the die region 102 is also removed, so as to form a gate and other device structures in the die region 102. Specifically, a patterned photoresist layer can be formed on the upper surface of the second material layer 15 first, and the patterned photoresist layer defines the shape and position of the gate and other device structures to be formed. Then, the second material layer 15 is etched based on the patterned photoresist layer, and the remaining second material layer 15 is the gate and other device structures.
[0085] Please continue to refer to Figures 1 to 8 and Figure 9The application further provides a semiconductor structure, comprising: a substrate 10; a first material layer 11 located on the upper surface of the substrate 10, the first material layer 11 having an opening 111 exposing the upper surface of the substrate 10; and a side wall 14 located on the opposite sidewall surfaces of the opening 10, the surface exposed by the side wall 14 being an arc surface.
[0086] In the semiconductor structure, the sidewall of the opening 111 forms the side wall 14 with the exposed arc surface, and the side wall 14 has a gentle slope. When the second material layer is formed in the opening 111, the second material layer has a gentle slope on the side wall 14. When the second material layer in the opening 111 is removed by etching, the second material layer in the opening 111 can be completely removed, thereby avoiding the residue of the second material layer at the bottom of the opening 111, ensuring the performance of the device and improving the reliability of the device.
[0087] Specifically, the substrate 10 can include but is not limited to a silicon substrate. In other examples, the substrate 10 can also be a sapphire substrate, a gallium nitride substrate, a silicon carbide substrate, etc.
[0088] In one example, as shown in FIG. 1, the substrate 10 can include a temperature sensor region 101 and a die region 102 adjacent to the temperature sensor region 101, and the first material layer 11 is located on the upper surface of the temperature sensor region 101. Figure 2
[0089] Specifically, the temperature sensor region 101 can be a vehicle-mounted IGBT (Insulated Gate Bipolar Transistor) temperature sensor region.
[0090] It should be noted that in other examples, the substrate 10 can also not be divided into regions, but only include one region; can also include a device region and an edge region, etc.; which is not limited here, and can be set and selected according to actual needs.
[0091] In one example, the thickness of the first material layer 11 can be set according to actual needs; specifically, the thickness of the first material layer 11 can be 5000 angstroms to 7000 angstroms, for example, the thickness of the first material layer 11 can be 5000 angstroms, 5500 angstroms, 6000 angstroms, 6500 angstroms or 7000 angstroms, etc.; in this embodiment, the thickness of the first material layer 11 can be 6000 angstroms.
[0092] In one example, the first material layer 11 includes but is not limited to an intrinsic polysilicon layer. Of course, in other examples, the first material layer 11 can also be a dielectric layer, etc.
[0093] In one example, the specific shape and size of the opening 111 can be set according to actual needs, which is not limited here.
[0094] As an example, the side wall 14 can include, but is not limited to, a TEOS side wall, and can also be a silicon oxide side wall formed based on TEOS.
[0095] In the description of the present specification, the description referring to the terms "one embodiment", "some embodiments", "other embodiments", and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily mean the same embodiment or example.
[0096] The technical features of the above-described embodiments can be combined arbitrarily, and in order to make the description simple, all possible combinations of the technical features in the above-described embodiments are not described, but as long as the combinations of the technical features do not contradict, they should be considered as the scope of the present specification.
[0097] The above-described embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.
Claims
1. A method of fabricating a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate, an upper surface of the substrate being formed with a first material layer, the first material layer having an opening therein, the opening exposing the upper surface of the substrate; forming a first hard mask material layer, the first hard mask material layer covering the upper surface of the first material layer and filling the opening; performing thinning treatment on the first hard mask material layer to obtain a first hard mask layer, the first hard mask layer covering the upper surface of the first material layer and filling the opening; forming a second hard mask layer on the surface of the first hard mask layer; etching the second hard mask layer and the first hard mask layer to form a side wall on the opposite sidewall surface of the opening, the exposed surface of the side wall being an arc surface; forming a second material layer, the second material layer covering at least the upper surface of the first material layer and filling the opening; removing the second material layer on the upper surface of the first material layer and in the opening.
2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The substrate comprises a temperature sensor region and a die region adjacent to the temperature sensor region, and the first material layer is located on the upper surface of the temperature sensor region.
3. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The first material layer comprises an intrinsic polysilicon layer.
4. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The etching of the second hard mask layer and the first hard mask layer to form the side wall comprises: etching the first hard mask layer and the second hard mask layer to form a deep trench in the opening; using a wet etching process to remove the second hard mask layer, the first hard mask layer on the upper surface of the first material layer, and part of the first hard mask layer in the opening, and the first hard mask layer remaining in the opening is the side wall.
5. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The first hard mask layer and the second hard mask layer are both TEOS layers.
6. A semiconductor structure, characterized by The semiconductor structure prepared by the method for preparing a semiconductor structure according to any one of claims 1-5 comprises: a substrate; a first material layer on the upper surface of the substrate, the first material layer having an opening therein, the opening exposing the upper surface of the substrate; a side wall on the opposite sidewall surface of the opening, the exposed surface of the side wall being an arc surface.
7. The semiconductor structure of claim 6, wherein, The substrate comprises a temperature sensor region and a die region adjacent to the temperature sensor region, and the first material layer is located on the upper surface of the temperature sensor region.
8. The semiconductor structure of claim 6, wherein, The substrate comprises a silicon substrate; the first material layer comprises an intrinsic polysilicon layer; and the side wall comprises a TEOS side wall.
Citation Information
Patent Citations
Manufacturing method of semiconductor device
CN104916591A
Epitaxial source or drain structures for advanced integrated circuit structure fabrication
CN113410233A