Method for manufacturing high voltage device

Abstract

The present invention provides a method for manufacturing a high-voltage device. Isolation trenches are formed in a substrate, with the region between adjacent isolation trenches serving as a high-voltage region. A first dielectric layer is filled in the isolation trenches, and a hard mask layer having an opening is formed on the substrate surface. The opening exposes at least the high-voltage region and a portion of the first dielectric layer adjacent to the high-voltage region. A first etching process is performed to etch the first dielectric layer and substrate within the opening, thereby forming a sharp corner in the portion of the substrate adjacent to the first dielectric layer within the opening. A second etching process is performed to further etch the first dielectric layer within the opening, exposing the surface of the sharp corner adjacent to the first dielectric layer. A portion of the thickness of the substrate, including the sharp corner, is oxidized to form a sacrificial layer, which is then removed. The present invention exposes the surface of the sharp corner by performing the second etching process, allowing the sharp corner to be completely oxidized to form a sacrificial layer, which is then removed. This improves the roundness of the substrate top corner in the high-voltage region and improves the performance of the high-voltage device.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a method for manufacturing a high-voltage device. Background Art

[0002] High-voltage integrated circuits are widely used in fields such as flat-panel displays, communications circuits, and automotive circuits. Typically, a low-voltage logic circuit generates control signals to control the high-voltage circuit. The output of the low-voltage logic circuit is then boosted to a high-voltage level by a high-voltage driver circuit containing high-voltage components. Existing high-voltage integrated circuits integrate both high-voltage (HV) and low-voltage (LV) components. High-voltage components require a thick gate oxide process to achieve gate-source withstand voltage, while LV components can utilize a thin gate oxide process.

[0003] In the fabrication process of 28nm high voltage devices, see Figure 1 When the substrate 100 in the high voltage region is etched back (recess), the portion of the substrate 100 close to the isolation trench 101 is difficult to be etched due to the blocking of the first dielectric layer 110, thereby forming a sharp corner A. Figure 2 In the subsequent process flow, the sharp corner A cannot be fully oxidized, resulting in the substrate 100 having a poor corner rounding problem, thereby adversely affecting the performance of the high-voltage device, such as the breakdown voltage (BV), hot carrier injection (HCI) and reliability (RE).

[0004] In view of this, a method is needed to reduce or eliminate the sharp corners or protrusions at the top corners of the substrate in the high voltage region, improve the roundness of the top corners of the substrate in the high voltage region, and thus improve the performance of the high voltage device. Summary of the Invention

[0005] The object of the present invention is to provide a method for manufacturing a high-voltage device, which reduces or eliminates the sharp corners at the top corners of the substrate in the high-voltage region and improves the roundness of the top corners of the substrate in the high-voltage region.

[0006] In order to achieve the above object, the present invention provides a method for manufacturing a high-voltage device, comprising:

[0007] Providing a substrate, wherein isolation trenches are formed in the substrate, the region between adjacent isolation trenches being a high-voltage region, the isolation trenches being filled with a first dielectric layer, and a hard mask layer having an opening formed on a surface of the substrate, wherein the opening exposes at least the high-voltage region and a portion of the surface of the first dielectric layer adjacent to the high-voltage region;

[0008] performing a first etching process to etch the first dielectric layer and the substrate exposed by the opening, so that a portion of the substrate in the opening close to the first dielectric layer forms a sharp corner;

[0009] performing a second etching process to continue etching the first dielectric layer exposed by the opening, so that a surface of the sharp corner close to the first dielectric layer is exposed;

[0010] Oxidizing a portion of the thickness of the substrate within the opening to form a sacrificial layer, wherein the portion of the substrate forming the sacrificial layer includes at least the sharp corner; and

[0011] The sacrificial layer is removed.

[0012] Optionally, the first etching process is a dry etching process.

[0013] Optionally, after performing the first etching process, a surface of the first dielectric layer in the opening is higher than a surface of the substrate in the opening.

[0014] Optionally, the second etching process is a wet etching process.

[0015] Optionally, the sacrificial layer is formed by an in-situ water vapor generation process or a thermal oxidation growth process.

[0016] Optionally, the sacrificial layer is removed by a wet etching process.

[0017] Optionally, the thickness of the sacrificial layer is in the range of

[0018] Optionally, after removing the sacrificial layer, the method further includes:

[0019] A second dielectric layer is formed on the surface of the substrate within the opening, and the second dielectric layer fills the opening.

[0020] Optionally, the second dielectric layer is formed by an in-situ water vapor generation process or a thermal oxidation growth process.

[0021] Optionally, both the first dielectric layer and the second dielectric layer include silicon oxide layers.

[0022] In summary, the present invention provides a method for manufacturing a high-voltage device, comprising: forming isolation trenches within a substrate; defining a high-voltage region between adjacent isolation trenches; and filling the isolation trenches with a first dielectric layer. A hard mask layer having an opening is formed on the surface of the substrate, wherein the opening exposes at least the high-voltage region and a portion of the first dielectric layer adjacent to the high-voltage region. A first etching process is performed to etch the first dielectric layer and substrate within the opening, thereby forming a sharp corner in the portion of the substrate adjacent to the first dielectric layer within the opening. A second etching process is performed to further etch the first dielectric layer within the opening, thereby exposing the surface of the sharp corner adjacent to the first dielectric layer. A portion of the substrate within the opening, including at least the thickness of the sharp corner, is oxidized to form a sacrificial layer, which is then removed. The present invention exposes the surface of the sharp corner by performing the second etching process, allowing the sharp corner to be completely oxidized to form a sacrificial layer, which is then removed. This reduces or eliminates the sharp corner, improves the roundness of the substrate top corner in the high-voltage region, and thereby improves the performance of the high-voltage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 and Figure 2 TEM images of high-voltage regions corresponding to different steps in a method for manufacturing a high-voltage device;

[0024] Figures 3 to 6 It is a schematic structural diagram corresponding to each step in a method for manufacturing a semiconductor device;

[0025] Figure 7 is a flow chart of a method for manufacturing a high-voltage device according to an embodiment of the present invention;

[0026] Figures 8 to 17 Schematic diagram of the structures corresponding to the steps in the method for manufacturing a high-voltage device according to an embodiment of the present invention;

[0027] The accompanying drawings are numerals as follows:

[0028] 100 - substrate; 101 - isolation trench; 110 - first dielectric layer;

[0029] 200 - substrate; 201 - isolation trench; 210 - first dielectric layer; 220 - hard mask layer; 221 - opening; 230 - photoresist layer; 240 - second dielectric layer;

[0030] 300 - substrate; 301 - isolation trench; 310 - first dielectric layer; 320 - hard mask layer; 321 - opening; 330 - photoresist layer; 340 - sacrificial layer; 350 - second dielectric layer;

[0031] X-high voltage area; A-pointed corner; B-substrate top angle; C-trench top angle. DETAILED DESCRIPTION

[0032] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0033] Figures 3 to 6 It is a schematic structural diagram corresponding to each step in the existing semiconductor device manufacturing method.

[0034] First, see Figure 3 An active area (AA) is formed in a substrate 200. A plurality of shallow trench isolation (STI) trenches 201 are formed in the active area. The region between two adjacent isolation trenches 201 is a high-voltage region X. The isolation trenches 201 are filled with a first dielectric layer 210. A hard mask layer 220 and a patterned photoresist layer 230 are sequentially formed on the surface of the substrate 200. Optionally, the substrate 200 is a silicon substrate, the first dielectric layer 210 is a silicon oxide layer, and the hard mask layer 220 is a silicon nitride layer.

[0035] Next, see Figure 3 and Figure 4 The hard mask layer 220 is etched using the patterned photoresist layer 230 as a mask to form an opening 221 in the hard mask layer 220. The opening 221 exposes at least the high-voltage region X and a portion of the surface of the first dielectric layer 210 near the high-voltage region X. Subsequently, the patterned photoresist layer 230 is removed. Optionally, a dry etching process is used to etch the hard mask layer 220, and a wet cleaning process is used to remove the patterned photoresist layer 230.

[0036] Then, see Figure 5 , using the hard mask layer 220 as a mask, the first dielectric layer 210 and the substrate 200 exposed by the opening 221 are etched. Optionally, a dry etching process is used to etch the first dielectric layer 210 and the substrate 200. It should be noted that since the first dielectric layer 210 and the substrate 200 are made of different materials, their etching rates in the same etching process are also different. The etching rate of the first dielectric layer 210 is lower than that of the substrate 200. Therefore, after the etching is completed, the surface of the first dielectric layer 210 in the opening 221 is higher than the surface of the substrate 200 in the opening 221.

[0037] At the same time, due to process limitations, the angle of the trench top angle (STI Trench Angle) C of the isolation trench 201 is less than 90°, that is, the sidewall of the isolation trench 201 is not completely vertical. Therefore, during the simultaneous etching of the first dielectric layer 210 and the substrate 220, the portion of the first dielectric layer 210 in the isolation trench 201 near the high-voltage region X will cover the portion of the substrate 200 near the isolation trench 201 in the high-voltage region X, making the portion of the substrate 200 near the first dielectric layer 210 unable to be etched or having a slow etching rate, thereby causing a sharp corner A to appear in the portion of the substrate 200 near the first dielectric layer 210. Optionally, the height of the sharp corner A is

[0038] Next, see Figure 6 A second dielectric layer 240 is formed on the surface of the substrate 200 within the opening 221, and the surface of the second dielectric layer 240 is flush with the surface of the substrate 200 outside the opening 240. Optionally, the second dielectric layer 240 can be formed by chemical vapor deposition, or by thermal oxidation growth to oxidize a portion of the thickness of the substrate 200 within the opening 221 to form the second dielectric layer 240. The second dielectric layer 240 is a silicon oxide layer.

[0039] It should be noted that when a thermal oxidation growth process is used to oxidize part of the substrate 200 in the opening 221 into the second dielectric layer 240, since the side of the sharp corner A close to the isolation trench 201 is covered by the first dielectric layer 210, the side of the sharp corner A close to the isolation trench 201 cannot come into contact with the reaction gas (for example, oxygen). Therefore, the sharp corner A cannot be completely oxidized, resulting in a poor degree of smoothness of the top corner B of the substrate in the subsequently formed semiconductor device.

[0040] Exemplarily, when the semiconductor device is a high-voltage device, Figure 5 The TEM electron microscope image corresponding to the semiconductor structure shown is Figure 1 similar, Figure 6 The TEM electron microscope image corresponding to the semiconductor structure shown is Figure 2 Similar. Combined Figure 1 and Figure 5 、 Figure 2 and Figure 6 It can be seen that in the process of forming a semiconductor device using the manufacturing method of the semiconductor device, the sharp corner A generated at the top corner of the substrate in the high-voltage area X can only be partially oxidized in the subsequent manufacturing process, resulting in the final top corner B of the substrate being less smooth, and having an adverse effect on the performance of the high-voltage device (such as breakdown voltage BV, hot carrier injection effect HCI, reliability RE, etc.).

[0041] To address the above-mentioned issues, an embodiment of the present invention provides a method for manufacturing a high-voltage device, wherein the surface of the sharp corner is exposed by further etching the first dielectric layer within the opening so that the sharp corner is completely oxidized into a sacrificial layer and removed, thereby reducing or eliminating the sharp corner, improving the roundness of the top corner of the substrate in the high-voltage region, and thereby improving the performance of the high-voltage device.

[0042] Figure 7 Flowchart of the method for manufacturing the high voltage device according to this embodiment. Figure 7 The manufacturing method of the high-voltage device in this embodiment includes:

[0043] Step S01: providing a substrate, wherein isolation trenches are formed in the substrate, wherein an area between adjacent isolation trenches is a high-voltage area, wherein the isolation trenches are filled with a first dielectric layer, and a hard mask layer having an opening is formed on the substrate, wherein the opening exposes at least the high-voltage area and a portion of the surface of the first dielectric layer adjacent to the high-voltage area;

[0044] Step S02: performing a first etching process to etch the first dielectric layer and the substrate exposed by the opening, so that a portion of the substrate in the opening close to the first dielectric layer forms a sharp corner;

[0045] Step S03: performing a second etching process to continue etching the first dielectric layer exposed by the opening, so that the surface of the sharp corner close to the first dielectric layer is exposed;

[0046] Step S04: oxidizing a portion of the thickness of the substrate within the opening to form a sacrificial layer, wherein the portion of the substrate forming the sacrificial layer includes at least the sharp corner; and

[0047] Step S05: removing the sacrificial layer.

[0048] Figures 8 to 17 The schematic diagram of the structure corresponding to each step in the manufacturing method of the high voltage device of this embodiment is shown below. Figures 8 to 17 The manufacturing method of the high-voltage device of this embodiment is described in detail.

[0049] First, see Figures 8 to 10 , perform step S01, provide a substrate 300, wherein isolation trenches 301 are formed in the substrate 300, and the area between adjacent isolation trenches 301 is a high-voltage area X, and the isolation trenches 301 are filled with a first dielectric layer 310, and a hard mask layer 320 having an opening 321 is formed on the substrate 300, wherein the opening 321 exposes at least the high-voltage area X and a portion of the surface of the first dielectric layer 310 near the high-voltage area X.

[0050] Specifically, the process of forming the opening 321 is as follows.

[0051] First, see Figure 8 A mask layer (not shown in the figure; the mask layer may be a patterned photoresist layer) is formed on the surface of the substrate 300. Using the mask layer as a mask, the substrate 300 is etched to form the isolation trenches 301. The mask layer is then removed. At this point, the region between adjacent isolation trenches 301 serves as the high-voltage region X. Subsequently, a first dielectric layer 310 is deposited in the isolation trenches 301, extending to cover the surface of the substrate 300 on both sides of the isolation trenches 301. A planarization process is performed on the first dielectric layer 310 to remove the first dielectric layer 310 from the surface of the substrate 300 and make the surface of the first dielectric layer 310 flush with the surface of the substrate 300.

[0052] Next, see Figure 9 The hard mask layer 320 is deposited on the surface of the substrate 300 and the first dielectric layer 310, and the photoresist layer 330 is deposited on the surface of the hard mask layer 320. The photoresist layer 330 is subjected to photolithography and etching processes to form a patterned photoresist layer 330. Figure 10 The hard mask layer 320 is etched using the patterned photoresist layer 330 as a mask to form an opening 321 on the hard mask layer 320, wherein the opening 321 exposes at least the high-voltage region X and a portion of the surface of the first dielectric layer 310 close to the high-voltage region X, and the patterned photoresist layer 330 is removed.

[0053] In this embodiment, a chemical vapor deposition process is used to form the first dielectric layer 310, a chemical mechanical polishing process is used to planarize the first dielectric layer 310, a dry etching process is used to etch the hard mask layer 320, and a wet cleaning process is used to remove the mask layer and the patterned photoresist layer 330. In other embodiments of the present invention, other process flows and process methods can be used to form the opening 321, and the present invention is not limited to this.

[0054] In this embodiment, before forming the mask layer on the surface of the substrate 300, the process further includes: performing an ion implantation process to form an active area (not shown in the figure) in the substrate 300, and the trench 301 formed subsequently is located in the active area. Figure 8 The substrate 300 shown is only a portion of the substrate of the high voltage device, and Figure 8 The substrate 300 shown in the figure forms the active area during the ion implantation process. For the sake of simplicity, the subsequent process steps and the process steps related to the substrate 300 in the corresponding drawings can be understood as process steps related to the active area.

[0055] In this embodiment, the substrate 300 is a silicon substrate, the first dielectric layer 310 is a silicon oxide layer, and the hard mask layer 320 is a silicon nitride layer. In other embodiments of the present invention, the materials of the first dielectric layer 310 and the hard mask layer 320 can be adjusted according to actual needs, and the present invention does not impose any restrictions on this.

[0056] Next, see Figure 11 , execute step S02, perform a first etching process to etch the first dielectric layer 310 and the substrate 300 exposed by the opening 321, so that the portion of the substrate 300 in the opening 321 close to the first dielectric layer 310 forms a sharp corner A. In this embodiment, a dry etching process is used to etch the first dielectric layer 310 and the substrate 300 exposed by the opening 321. Since the first dielectric layer 310 and the substrate 300 are made of different materials, their etching rates in the same etching process are also different. The etching rate of the first dielectric layer 310 is lower than the etching rate of the substrate 300. Therefore, after the first etching process is completed, the surface of the first dielectric layer 310 in the opening 321 is higher than the surface of the substrate 300 in the opening 310. Optionally, the height difference between the surface of the first dielectric layer 310 in the opening 321 and the surface of the substrate 300 in the opening 310 is

[0057] It should be noted that, due to process limitations, the angle of the trench top angle (STI TrenchAngle) C of the isolation trench 301 is less than 90°, that is, the sidewall of the isolation trench 301 is not completely vertical. Therefore, during the execution of the first etching process and the simultaneous etching of the first dielectric layer 310 and the substrate 320, the portion of the first dielectric layer 310 in the isolation trench 301 near the high-voltage region X will cover the portion of the substrate 300 near the isolation trench 301 in the high-voltage region X, making the portion of the substrate 300 near the first dielectric layer 310 unable to be etched or the etching rate is slow, thereby causing the sharp corner A to appear in the portion of the substrate 300 near the first dielectric layer 310. Exemplarily, the height of the sharp corner A is Width is

[0058] Then, see Figure 12, step S03 is executed to perform a second etching process to continue etching the first dielectric layer 310 exposed by the opening 321, so that the surface of the sharp corner A close to the first dielectric layer 321 is exposed. In this embodiment, a wet etching process is used to continue etching the first dielectric layer 310 exposed by the opening 321, and the etchant used in the wet etching process is dilute hydrofluoric acid (DHF). Optionally, in the second etching process, the thickness of the first dielectric layer 321 etched is

[0059] Next, see Figure 13 , execute step S04, oxidize the partial thickness of the substrate 300 within the opening 321 to form a sacrificial layer 340, and the portion of the substrate 300 forming the sacrificial layer 340 includes at least the sharp corner A. In this embodiment, the sacrificial layer 340 is formed by an in-situ water vapor generation process, and the material of the sacrificial layer 340 is silicon oxide. In other embodiments of the present invention, the sacrificial layer 340 can be formed by oxidizing a portion of the substrate 300 by a thermal oxidation growth process or other processes, and the present invention is not limited thereto. Optionally, the thickness range of the sacrificial layer 340 is

[0060] It should be noted that, because the surface of the sharp corner A near the isolation trench 301 is exposed, when the sharp corner A is small (for example, when the height and width of the sharp corner A are both smaller than the thickness range of the sacrificial layer 340), the sharp corner A can be completely oxidized during the in-situ water vapor generation process to form the sacrificial layer 340. However, when the sharp corner A is large (for example, when the height or width of the sharp corner A is greater than the thickness range of the sacrificial layer 340), only the surface of the sharp corner A will be oxidized to form the sacrificial layer 340.

[0061] Then, see Figure 14 and Figure 15 ( Figure 15 for Figure 17 ), execute step S05 to remove the sacrificial layer 340. In this embodiment, a wet etching process is adopted to remove the sacrificial layer 340, and the etchant of the wet etching process is dilute hydrofluoric acid (DHF). It should be noted that when the sharp angle A in step S04 is small and the sacrificial layer 340 is completely oxidized, removing the sacrificial layer 340 can completely eliminate the sharp angle A; and when the sharp angle A in step S04 is large, resulting in a limited thickness of the sacrificial layer 340 formed by oxidation, removing the sacrificial layer 340 can only reduce the height and width of the sharp angle A, but cannot completely eliminate the sharp angle A.

[0062] In combination with step S02, it can be seen that in this embodiment, the height and width of the sharp corner A are significantly greater than the thickness of the sacrificial layer 340 formed in step S04. Therefore, removing the sacrificial layer 340 can only reduce the height and width of the sharp corner A. For example, the height of the sharp corner A is Width is

[0063] In addition, see Figure 16 and Figure 17 ( Figure 17 for Figure 16 (TEM electron microscope image corresponding to a portion of the structure of the high-voltage device shown in FIG. 3 ) After removing the sacrificial layer 340, the method for manufacturing the high-voltage device further includes: forming a second dielectric layer 350 on the surface of the substrate 300 within the opening 321, with the surface of the second dielectric layer 350 being flush with the surface of the substrate 300 outside the opening 321. In this embodiment, the second dielectric layer 350 is formed using an in-situ water vapor generation process. The second dielectric layer 350 is a silicon oxide layer. In other embodiments of the present invention, the second dielectric layer 350 can be formed by oxidizing a portion of the substrate 300 within the opening 321 using a thermal oxidation growth process or other processes, which is not limited by the present invention.

[0064] It should be noted that, since silicon increases in volume during oxidation to form silicon dioxide, the volume of the second dielectric layer 350 formed by oxidation is larger than the volume of the oxidized portion of the substrate 300 within the opening 321. Based on this, the morphology of the second dielectric layer 350 can be controlled by controlling the process parameters of the in-situ water vapor generation process, so that the surface of the second dielectric layer 350 is flush with the surface of the substrate 300 outside the opening 321, so that subsequent processes can proceed normally. Figure 14 and Figure 16 It can be seen that in the process of forming the second dielectric layer 350 using the in-situ water vapor generation process, the sharp corner A remaining in step S05 will be oxidized again to form the second dielectric layer 350, thereby further improving the smoothness of the substrate top corner B in the subsequently formed high-voltage device, thereby improving the performance of the high-voltage device.

[0065] Combine Figure 5 and Figure 6 It can be seen that during the preparation process of the existing semiconductor device, the surface of the sharp corner A close to the first dielectric layer 210 is covered by the first dielectric layer 210, so that the sharp corner A cannot be completely oxidized, resulting in a poor degree of roundness of the top corner B of the substrate in the final semiconductor device, thereby affecting the performance of the semiconductor device. Figure 15 and Figure 17It can be seen that the method for manufacturing a high-voltage device described in this embodiment further etches the first dielectric layer 310 to expose the surface of the sharp corner A on the side close to the first dielectric layer 310, allowing the sharp corner to be completely oxidized, thereby achieving a smoother substrate top corner B in the final high-voltage device, thereby improving the performance of the high-voltage device. It should be noted that the method for manufacturing a high-voltage device is used to manufacture a 28nm high-voltage device. In other embodiments of the present invention, the method for manufacturing a high-voltage device can be used to manufacture high-voltage devices below 60nm, such as 40nm high-voltage devices and 55nm high-voltage devices. The method for manufacturing a high-voltage device can also be used to prepare other semiconductor devices with the same or similar structures, and the present invention is not limited to this.

[0066] In summary, the present invention provides a method for manufacturing a high-voltage device, comprising: forming isolation trenches within a substrate; defining a high-voltage region between adjacent isolation trenches; and filling the isolation trenches with a first dielectric layer. A hard mask layer having an opening is formed on the surface of the substrate, wherein the opening exposes at least the high-voltage region and a portion of the first dielectric layer adjacent to the high-voltage region. A first etching process is performed to etch the first dielectric layer and substrate within the opening, thereby forming a sharp corner in the portion of the substrate adjacent to the first dielectric layer within the opening. A second etching process is performed to further etch the first dielectric layer within the opening, thereby exposing the surface of the sharp corner adjacent to the first dielectric layer. The substrate within the opening, including at least a portion of the thickness of the sharp corner, is oxidized to form a sacrificial layer, which is then removed. The present invention exposes the surface of the sharp corner by performing the second etching process, allowing the sharp corner to be completely oxidized to form a sacrificial layer, which is then removed. This reduces or eliminates the sharp corner, improves the roundness of the substrate top corner in the high-voltage region, and thereby improves the performance of the high-voltage device.

[0067] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A method for manufacturing a high voltage device, characterized in that: include: A substrate is provided, wherein isolation trenches are formed in the substrate, an area between adjacent isolation trenches is a high-voltage area, the isolation trenches are filled with a first dielectric layer, and a hard mask layer having an opening is formed on the substrate, wherein the opening exposes at least the high-voltage area and a portion of the surface of the first dielectric layer adjacent to the high-voltage area; performing a first etching process to etch the first dielectric layer and the substrate exposed by the opening, so that a portion of the substrate in the opening close to the first dielectric layer forms a sharp corner; performing a second etching process to continue etching the first dielectric layer exposed by the opening, so that a surface of the sharp corner close to the first dielectric layer is exposed; Oxidizing a portion of the thickness of the substrate within the opening to form a sacrificial layer, wherein the portion of the substrate forming the sacrificial layer includes at least the sharp corner; and The sacrificial layer is removed.

2. The method for manufacturing a high voltage device according to claim 1, wherein: The first etching process is a dry etching process.

3. The method for manufacturing a high voltage device according to claim 2, wherein: After performing the first etching process, the surface of the first dielectric layer in the opening is higher than the surface of the substrate in the opening.

4. The method for manufacturing a high voltage device according to claim 1 or 2, wherein: The second etching process is a wet etching process.

5. The method for manufacturing a high voltage device according to claim 4, wherein: The sacrificial layer is formed by an in-situ water vapor generation process or a thermal oxidation growth process.

6. The method for manufacturing a high voltage device according to claim 5, wherein: The sacrificial layer is removed by a wet etching process.

7. The method for manufacturing a high voltage device according to claim 5, wherein: The thickness of the sacrificial layer is in the range of 8. The method for manufacturing a high voltage device according to claim 1, wherein: After removing the sacrificial layer, the method further comprises: A second dielectric layer is formed on the surface of the substrate within the opening, and the second dielectric layer fills the opening.

9. The method for manufacturing a high voltage device according to claim 8, wherein: The second dielectric layer is formed by an in-situ water vapor generation process or a thermal oxidation growth process.

10. The method for manufacturing a high voltage device according to claim 8, wherein: The first dielectric layer and the second dielectric layer are both silicon oxide layers.

Images