Lateral diffused metal oxide semiconductor device and method of making same

Abstract

A lateral diffusion metal oxide semiconductor element and a manufacturing method thereof are disclosed. The manufacturing method of the lateral diffusion metal oxide semiconductor element comprises the following steps. First fin structures and second fin structures are formed on a substrate. A shallow trench isolation is formed between the first fin structures and the second fin structures. A first gate structure is formed on the first fin structures, and a second gate structure is formed on the second fin structures. A source region is formed on the first fin structures on a side of the first gate structure. A drain region is formed on the second fin structures on a side of the second gate structure. A contact field plate is formed above the shallow trench isolation.

Description

TECHNICAL FIELD

[0001] The present application relates to a method for fabricating a semiconductor device, and more particularly to a method for integrating a lateral diffused metal oxide semiconductor (LDMOS) with a fin structure. BACKGROUND

[0002] Lateral diffused metal oxide semiconductor (LDMOS) devices have been widely used in high voltage operating environments, such as CPU power supply, power management system, AC / DC converter, and high power or high frequency power amplifier, due to their high operating frequency and efficiency, and planar structure which is easy to integrate with other integrated circuits.

[0003] As device size continues to shrink, the development of existing planar field effect transistor devices has reached the limit of fabrication process. In order to overcome the fabrication process limitations, non-planar field effect transistor devices, such as fin field effect transistor (Fin FET) devices, have become the mainstream development trend to replace planar transistor devices. Since the three-dimensional structure of the fin field effect transistor device can increase the contact area between the gate and the fin structure, the control of the gate on the carrier channel region can be further increased, thereby reducing the drain induced barrier lowering (DIBL) effect faced by small size devices and suppressing the short channel effect (SCE). Furthermore, the fin field effect transistor device has a wider channel width under the same gate length, so that the drain drive current can be doubled. Even the threshold voltage of the transistor device can be adjusted by adjusting the work function of the gate.

[0004] However, there are still many challenges in the integration of existing lateral diffused metal oxide semiconductor devices and fin structures as device size continues to shrink, such as control of leakage current and breakdown voltage. Therefore, how to improve the existing high voltage device architecture is an important issue today. SUMMARY

[0005] An embodiment of the present application discloses a method for manufacturing a lateral diffusion metal oxide semiconductor element. First, a first fin structure and a second fin structure are formed on a substrate, then a shallow trench isolation is formed between the first fin structure and the second fin structure, a first gate structure is formed on the first fin structure and a second gate structure is formed on the second fin structure, a source region is formed on the first fin structure on one side of the first gate structure, a drain region is formed on the second fin structure on one side of the second gate structure, and a contact field plate is formed directly above the shallow trench isolation.

[0006] Another embodiment of the present application discloses a lateral diffusion metal oxide semiconductor element, which mainly comprises a first fin structure arranged on a substrate, a shallow trench isolation arranged beside the first fin structure, a first gate structure arranged on the first fin structure, and a contact field plate arranged directly above the shallow trench isolation beside the first gate structure.

[0007] Still another embodiment of the present application discloses a lateral diffusion metal oxide semiconductor element, which mainly comprises a first fin structure arranged on a substrate, a shallow trench isolation arranged beside the first fin structure, a first gate structure arranged on the first fin structure and the shallow trench isolation, and a contact field plate arranged directly above the shallow trench isolation beside the first gate structure. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figures 1 to 4 A schematic diagram of a method for manufacturing a lateral diffusion metal oxide semiconductor element according to an embodiment of the present application;

[0009] Figure 5 A schematic diagram of a structure of a lateral diffusion metal oxide semiconductor element according to an embodiment of the present application;

[0010] Figure 6 A schematic diagram of a structure of a lateral diffusion metal oxide semiconductor element according to an embodiment of the present application.

[0011] Explanation of main element symbols

[0012] 12: substrate

[0013] 14: first fin structure

[0014] 16: second fin structure

[0015] 18: P-well

[0016] 20: N-well

[0017] 22: shallow trench isolation

[0018] 24: gate structure

[0019] 26: gate structure

[0020] 28: gate structure

[0021] 30: Gate structure

[0022] 32: Gate dielectric layer

[0023] 34: Gate material layer

[0024] 36: Spacer wall

[0025] 38: Source Region

[0026] 40: Drain region

[0027] 42: Interlayer dielectric layer

[0028] 44: Dielectric layer

[0029] 46: High dielectric constant dielectric layer

[0030] 48: Work function metal layer

[0031] 50: Low-resistivity metal layer

[0032] 52: Hard Mask

[0033] 54: Interlayer dielectric layer

[0034] 56: Contact plug

[0035] 58: Contact plug

[0036] 60: Contact field plate Detailed Implementation

[0037] Please refer to Figures 1 to 4 , Figures 1 to 4 This is a schematic diagram of a method for fabricating a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present invention, wherein... Figure 1 This is a top view of a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present invention. Figures 2 to 4 Then it is Figure 1 A cross-sectional view of a laterally diffused metal-oxide-semiconductor device is fabricated along tangent AA'. (See diagram below.) Figures 1 to 2As shown, a substrate 12 is first provided, and then a plurality of fin structures, such as a first fin structure 14 and a second fin structure 16, are formed on the substrate 12, and a first well region (e.g., P-well 18) and a second well region (e.g., N-well 20) are formed within the first fin structure 14 and the second fin structure 16. Then, a shallow trench isolation (STI) 22 is formed between the first fin structure 14 and the second fin structure 20, and the upper surface of the shallow trench isolation 22 is slightly lower than the upper surfaces of the first fin structure 14 and the second fin structure 16. Herein, the first well region (e.g., P-well 18) is completely located within the first fin structure 14, and the second well region (e.g., N-well 20) is located within the second fin structure 16 and the first fin structure 14, and in addition, the contact shallow trench isolation 22 is completely located within the second well region (e.g., N-well 20).

[0038] In the present embodiment, the substrate 12 is preferably composed of a semiconductor material, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, and the shallow trench isolation 22 is preferably composed of silicon oxide, but is not limited thereto. In addition, the present embodiment Figure 1 Although seven first fin structures 14 and seven second fin structures 16 are formed on the substrate 12 in the top view of the present embodiment, the number of fin structures is not limited thereto and can be adjusted according to the manufacturing process or product requirements.

[0039] The fin structures, including the first fin structure 14 and the second fin structure 16, of the preferred embodiment of the present application are preferably formed by a sidewall image transfer (SIT) technique, and the procedure thereof generally includes: providing a layout pattern to a computer system, and performing appropriate operations to define corresponding patterns in a photomask. Subsequently, photolithography and etching manufacturing processes can be performed to form a plurality of equidistant and equal-width patterned sacrificial layers on the substrate, so that the individual appearances thereof present a strip shape. Then, deposition and etching manufacturing processes are sequentially performed to form a spacer on each sidewall of the patterned sacrificial layer. Next, the patterned sacrificial layer is removed, and an etching manufacturing process is performed under the coverage of the spacer, so that the pattern formed by the spacer is transferred into the substrate, and then a fin cut manufacturing process is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.

[0040] In addition, the fin structures can be formed by first forming a patterned mask (not shown) on the substrate 12, and then performing an etching process to transfer the pattern of the patterned mask to the substrate 12 to form the first fin structure 14 and the second fin structure 16. Alternatively, the fin structures can be formed by first forming a patterned hard mask layer (not shown) on the substrate 12, and then performing an epitaxial growth process to grow a semiconductor layer, such as a silicon germanium layer, on the substrate 12 exposed by the patterned hard mask layer, which can serve as the first fin structure 14 and the second fin structure 16. These embodiments of forming the fin structures are all within the scope of the present disclosure.

[0041] Next, a gate structure 24 is formed on the first fin structure 14, a gate structure 26 is formed on the first fin structure 14 to the left of the gate structure 24, and gate structures 28 and 30 are formed on the second fin structure 16. In this embodiment, the gate structures can be formed by a gate-first process, a gate-last process, a high-k first process, or a high-k last process, depending on the process requirements. For example, in a high-k last process, a gate dielectric layer 32 or a dielectric layer made of silicon oxide, a gate material layer 34 made of polysilicon, and a selective hard mask (not shown) are sequentially formed on the substrate 12, and then a pattern transfer process is performed using a patterned photoresist (not shown) as a mask to remove part of the gate material layer 34 and part of the gate dielectric layer 32 by a single etching or a step-by-step etching process, and then the patterned photoresist is removed to form the gate structures 24, 26, 28, and 30 on the substrate 12.

[0042] Then, at least one spacer 36 is formed on the sidewalls of each of the gate structures 24, 26, 28, and 30, and a source region 38 made of, for example, an N+ region is formed in the first fin structure 14 to the side of the gate structure 24, and a drain region 40 made of, for example, an N+ region is formed in the second fin structure 16 to the side of the gate structure 28. In this embodiment, the spacer 36 can be a single spacer or a composite spacer, such as a bias spacer and a main spacer. The bias spacer and the main spacer can be made of the same or different materials, and can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon nitride. The source region 38 and the drain region 40 can contain different dopants depending on the conductivity type of the transistors to be provided, such as P-type dopants or N-type dopants.

[0043] AsFigure 3 As shown, an interlayer dielectric layer 42 can then be formed on the gate structures 24, 26, 28, 30 and the shallow trench isolation 22, followed by a planarization process, such as chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 42 and expose the gate material layer 34 made of polysilicon, making the upper surface of each gate material layer 34 flush with the upper surface of the interlayer dielectric layer 42. Subsequently, a metal gate replacement process is performed to convert the gate structure 24 into a metal gate. For example, a patterned mask (not shown) can be selectively formed to cover the gate structures 26, 28, 30, followed by a selective dry or wet etching process, such as using an etching solution like ammonia (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 34 and even the gate dielectric layer 32 in the gate structure 24 to form a trench (not shown) in the interlayer dielectric layer 42. Then, a dielectric layer 44, a high dielectric constant dielectric layer 46, and a conductive layer containing at least a work function metal layer 48 and a low impedance metal layer 50 are sequentially formed in the groove. A planarization process is then performed to make the surfaces of the U-shaped high dielectric constant dielectric layer 46, the U-shaped work function metal layer 48, and the low impedance metal layer 50 flush with the surface of the interlayer dielectric layer 42.

[0044] In this embodiment, the high dielectric constant dielectric layer 46 comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), and strontium bismuth tantalum oxide. lead zirconate titanate (SrBi₂Ta₂O₉, SBT) and lead zirconate titanate (PbZr) xTi 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x TiO3, BST), or combinations thereof.

[0045] The work function metal layer 48 is preferably used to adjust the work function of the metal gate to be suitable for either an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 48 can be selected from a metal material having a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminum (TiAl), zirconium aluminum (ZrAl), tungsten aluminum (WAl), tantalum aluminum (TaAl), hafnium aluminum (HfAl), or TiAlC (titanium aluminum carbide), but not limited thereto. If the transistor is a P-type transistor, the work function metal layer 48 can be selected from a metal material having a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but not limited thereto. Another barrier layer (not shown) can be included between the work function metal layer 48 and the low impedance metal layer 50, wherein the barrier layer can be made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or the like. The low impedance metal layer 50 can be selected from a low resistance material such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or combinations thereof. Since the conversion of the dummy gate to the metal gate according to the metal gate replacement process is well known in the art, further description is not provided. Then, a portion of the high dielectric constant dielectric layer 46, a portion of the work function metal layer 48, and a portion of the low impedance metal layer 50 are removed to form a recess (not shown), and a hard mask 52 is then filled in the recess and planarized with the surface of the interlayer dielectric layer 42, wherein the hard mask 52 can be selected from a group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride.

[0046] As Figure 4As shown, another interlayer dielectric layer 54 can then be selectively formed on the gate structure 24 and the interlayer dielectric layer 42 formed by the metal gate, and a pattern transfer fabrication process is performed. For example, a patterned mask can be used to remove portions of the interlayer dielectric layers 42 and 54 next to the gate structures 24, 26, 28, and 30 to form multiple contact holes (not shown) and expose the source region 38, the drain region 40, and the shallow trench isolation 22. Then, the required conductive material is filled into each contact hole, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. A planarization process is then performed, such as chemical mechanical polishing to remove some conductive material, to form contact plug 56 contacting and electrically connecting the source region 38, contact plug 58 contacting and electrically connecting the drain region 40, and contact field plate 60 on the shallow trench isolation 22. This completes the fabrication of the semiconductor device according to the preferred embodiment of the present invention.

[0047] Please refer to again Figure 4 , Figure 4 This is a schematic diagram of the structure of a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present invention. Figure 4 As shown, the laterally diffused metal-oxide-semiconductor device mainly includes a first fin structure 14 and a second fin structure 16 disposed on a substrate 12, a shallow trench isolation 22 disposed between the first fin structure 14 and the second fin structure 16, a gate structure 24 disposed on the first fin structure 14, a gate structure 28 disposed on the second fin structure 16, a source region 38 disposed on the first fin structure 14 on one side of the gate structure 24, a drain region 40 disposed on the second fin structure 16 on one side of the gate structure 28, interlayer dielectric layers 42 and 54 surrounding the gate structure 24 and the gate structure 28, a contact plug 56 disposed on the source region 38, a contact plug 58 disposed on the drain region 40, and a contact field plate 60 disposed directly above and in contact with the shallow trench isolation 22 between the gate structure 24 and the gate structure 28. Figure 1 As shown, the first fin structure 14 and the second fin structure 16 preferably extend along a first direction, such as the X direction, while the contact plug 56 and the contact field plate 60 extend along a second direction, such as the Y direction, on the substrate 12.

[0048] It is noted that since the contact field plate 60 and the contact plugs 56, 58 are completed from the same manufacturing process, the contact field plate 60 and the contact plugs 56, 58 preferably comprise the same material composition. In addition, from the structural point of view, the gate structures 26, 28, 30 are preferably dummy gate structures and the width thereof is preferably smaller than the width of the gate structure 24, the bottom surface of the contact field plate 60 is preferably lower than the bottom surface of the contact plugs 56, 58 due to the contact with the surface of the shallow trench isolation 22 but the top surface of the contact field plate 60 is preferably flush with the top surface of the contact plugs 56, 58. In other words, the overall height of the contact field plate 60 is preferably greater than the height of the contact plug 56 connecting the source region 38 and the height of the contact plug 58 connecting the drain region 40.

[0049] Please continue to refer to Figure 5 , Figure 5 is a schematic diagram of a structure of a lateral diffusion metal oxide semiconductor element according to an embodiment of the present application. As shown in Figure 5 , compared to the aforementioned embodiment in which only the gate structure 24 is converted into a metal gate, according to other embodiments of the present application, the aforementioned setting of the patterned mask can be omitted during the metal gate replacement manufacturing process and at the same time the gate structures 24, 26, 28, 30 are converted into metal gate structures, that is, each of the gate structures 24, 26, 28, 30 comprises metal gate materials such as the dielectric layer 44, the high dielectric constant dielectric layer 46, the work function metal layer 48 and the low impedance metal layer 50. This variant also falls within the scope of the present application.

[0050] Please continue to refer to Figure 6 , Figure 6 is a schematic diagram of a structure of a lateral diffusion metal oxide semiconductor element according to an embodiment of the present application. As shown in Figure 6 , the lateral diffusion metal oxide semiconductor element mainly comprises the first fin structure 14 and the second fin structure 16 disposed on the substrate 12, the shallow trench isolation 22 disposed between the first fin structure 14 and the second fin structure 16, the gate structure 24 disposed on the first fin structure 14, the gate structure 28 disposed on the second fin structure 16, the source region 38 disposed on the first fin structure 14 on one side of the gate structure 24, the drain region 40 disposed on the second fin structure 16 on one side of the gate structure 28, the interlayer dielectric layer 42, 54 surrounding the gate structure 24 and the gate structure 28, the contact plug 56 disposed on the source region 38, the contact plug 58 disposed on the drain region 40 and the contact field plate 60 disposed on the shallow trench isolation 22 directly above the gate structure 24 and the gate structure 28 and in contact with the shallow trench isolation 22.

[0051] In contrast to the gate structure 24 in the foregoing embodiment being formed only on the first fin structure 14 but not extending over the shallow trench isolation 22 or the gap wall 36 beside the gate structure 24, in the present embodiment, the gate structure 24 is extended to the right and over the shallow trench isolation 22 during the formation of the gate structures 24, 26, 28, 30 by the aforementioned patterning process. Then, the gate structure 24 is converted into a metal gate by the metal gate replacement process and the contact plug formation process is performed to form the contact field plate 60 beside the gate structure 24. In the present embodiment, the gate structure 24 and the contact field plate 60 are preferably formed on the shallow trench isolation 22 and contact the shallow trench isolation 22 at the same time, wherein the bottom surface of the gate structure 24 on the shallow trench isolation 22 is preferably cut flush with the bottom surface of the contact field plate 60 and is lower than the top surfaces of the first fin structure 14 and the second fin structure 16. Figure 3 The gate structure 24 is converted into a metal gate by the metal gate replacement process and the contact plug formation process is performed to form the contact field plate 60 beside the gate structure 24. In the present embodiment, the gate structure 24 and the contact field plate 60 are preferably formed on the shallow trench isolation 22 and contact the shallow trench isolation 22 at the same time, wherein the bottom surface of the gate structure 24 on the shallow trench isolation 22 is preferably cut flush with the bottom surface of the contact field plate 60 and is lower than the top surfaces of the first fin structure 14 and the second fin structure 16.

[0052] As in the foregoing embodiment, since the contact field plate 60 and the contact plugs 56, 58 are formed from the same process, the contact field plate 60 and the contact plugs 56, 58 preferably comprise the same material composition. In terms of structure, the gate structure 28 between the contact field plate 60 and the drain region 40 is preferably a dummy gate structure and its width is preferably smaller than the width of the gate structure 24. The bottom of the contact field plate 60 contacts the surface of the shallow trench isolation 22, so the bottom surface of the contact field plate 60 is preferably lower than the bottom surfaces of the contact plugs 56, 58, but the top surface of the contact field plate 60 is preferably cut flush with the top surfaces of the contact plugs 56, 58. In other words, the overall height of the contact field plate 60 is preferably greater than the heights of the contact plug 56 connected to the source region 38 and the contact plug 58 connected to the drain region 40. In addition, although the present embodiment is described as Figure 4 The foregoing embodiment is described by way of example with the gate structure 24 comprising a metal gate and the gate structures 26, 28, 30 comprising a polysilicon gate, but is not limited thereto. According to other embodiments of the present application, the extended gate structure 24 can also be applied to Figure 5 The foregoing embodiment is described by way of example with the gate structure 24 comprising a metal gate and the gate structures 26, 28, 30 comprising a polysilicon gate, but is not limited thereto. According to other embodiments of the present application, the extended gate structure 24 can also be applied to

[0053] Generally, the gate structure or gate electrode of a conventional lateral diffusion metal oxide semiconductor device is usually extended outward to form a field plate to achieve a higher breakdown voltage. To improve the conventional design without additional cost and complicated manufacturing process, the present invention forms another contact plug on top of the shallow trench isolation simultaneously when forming the contact plug connecting the source region and the drain region, so that the lateral diffusion metal oxide semiconductor device can utilize the coupling effect among the contact field plate 60, the interlayer dielectric layer 42, 54 and the gate structure 24 to improve the breakdown voltage of the device. According to different embodiments of the present invention, in addition to forming the contact field plate, the gate structure of the lateral diffusion metal oxide semiconductor device can be extended to the shallow trench isolation as Figure 4 and Figure 5 generally not extended to the shallow trench isolation or extended to the shallow trench isolation such that the gate structure and the contact field plate both contact and stand on the shallow trench isolation, all of which are within the scope of the present invention. Figure 6

[0054] The above description is only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention should be within the scope of the present invention.​

Claims

1. A method for fabricating a laterally diffused metal-oxide-semiconductor device, characterized in that, Include: The first fin-like structure is formed on the substrate; A shallow groove is formed to isolate the area beside the first fin-like structure; A first gate structure is formed on the first fin structure; and A contact field plate is formed directly above the shallow trench isolation next to the first gate structure, wherein the shallow trench isolation has a first top surface that directly contacts the bottom surface of the contact field plate and a second top surface located around the first top surface, the first top surface being flush with the second top surface and lower than the top surface of the substrate; An interlayer dielectric layer is formed around the first gate structure, wherein a portion of the interlayer dielectric layer is located between the contact field plate and the first gate structure, and the bottom surface of this portion of the interlayer dielectric layer is lower than the top surface of the substrate.

2. The method of claim 1, further comprising: A second fin-like structure is formed next to the first fin-like structure, wherein the shallow groove is disposed between the first fin-like structure and the second fin-like structure; A second gate structure is formed on the second fin structure; A source region is formed on the first fin structure on one side of the first gate structure; A drain region is formed on the second fin structure on one side of the second gate structure; This interlayer dielectric layer surrounds the second gate structure; The first gate structure and the second gate structure are converted into a first metal gate and a second metal gate; as well as A first contact plug is formed on the source region and a second contact plug is formed on the drain region.

3. The method of claim 2, wherein the contact field plate is disposed between the first gate structure and the second gate structure.

4. The method of claim 2, wherein the width of the second gate structure is smaller than the width of the first gate structure.

5. The method of claim 2, wherein the contact field plate and the first contact plug comprise the same material.

6. The method of claim 2, wherein the bottom surface of the contact field plate is lower than the bottom surface of the first contact plug.

7. The method of claim 2, wherein the top surface of the contact field plate is flush with the top surface of the first contact plug.

8. A laterally diffused metal-oxide-semiconductor device, characterized in that, Include: The first fin-like structure is located on the substrate; Shallow trench isolation, located next to the first fin-like structure; A first gate structure is disposed on the first fin structure; and A contact field plate is disposed directly above the shallow trench isolation next to the first gate structure, wherein the shallow trench isolation has a first top surface that directly contacts the bottom surface of the contact field plate and a second top surface located around the first top surface, the first top surface being flush with the second top surface and lower than the top surface of the substrate; as well as An interlayer dielectric layer surrounds the first gate structure, wherein a portion of the interlayer dielectric layer is located between the contact field plate and the first gate structure, and the bottom surface of this portion of the interlayer dielectric layer is lower than the top surface of the substrate.

9. The laterally diffused metal-oxide-semiconductor device of claim 8, further comprising: A second fin-like structure is disposed next to the first fin-like structure, wherein the shallow groove is disposed between the first fin-like structure and the second fin-like structure; A second gate structure is disposed on the second fin structure; The source region is located on the first fin structure on one side of the first gate structure; The drain region is located on the second fin structure on one side of the second gate structure; The interlayer dielectric layer surrounds the second gate structure; and A first contact plug is disposed on the source region and a second contact plug is disposed on the drain region.

10. The laterally diffused metal-oxide-semiconductor device of claim 9, wherein the contact field plate is disposed between the first gate structure and the second gate structure.

11. The laterally diffused metal-oxide-semiconductor device of claim 9, wherein the width of the second gate structure is smaller than the width of the first gate structure.

12. The laterally diffused metal-oxide-semiconductor device of claim 9, wherein the contact field plate and the first contact plug comprise the same material.

13. The laterally diffused metal-oxide-semiconductor device of claim 9, wherein the bottom surface of the contact field plate is lower than the bottom surface of the first contact plug.

14. The laterally diffused metal-oxide-semiconductor device of claim 9, wherein the top surface of the contact field plate is flush with the top surface of the first contact plug.

15. A laterally diffused metal-oxide-semiconductor device, characterized in that, Include: The first fin-like structure is located on the substrate; Shallow trench isolation, located next to the first fin-like structure; A first gate structure is disposed on the first fin structure and the shallow trench isolation; as well as A contact field plate is disposed directly above the shallow trench isolation next to the first gate structure, wherein the shallow trench isolation has a first top surface that directly contacts the bottom surface of the contact field plate and a second top surface located around the first top surface, the first top surface being flush with the second top surface and lower than the top surface of the substrate; as well as An interlayer dielectric layer surrounds the first gate structure, wherein a portion of the interlayer dielectric layer is located between the contact field plate and the first gate structure, and the bottom surface of this portion of the interlayer dielectric layer is lower than the top surface of the substrate.

16. The laterally diffused metal-oxide-semiconductor device of claim 15, further comprising: A second fin-like structure is disposed next to the first fin-like structure, wherein the shallow groove is disposed between the first fin-like structure and the second fin-like structure; A second gate structure is disposed on the second fin structure; The source region is located on the first fin structure on one side of the first gate structure; The drain region is located on the second fin structure on one side of the second gate structure; The interlayer dielectric layer surrounds the second gate structure; and A first contact plug is disposed on the source region and a second contact plug is disposed on the drain region.

17. The laterally diffused metal-oxide-semiconductor device of claim 16, wherein the contact field plate is disposed between the first gate structure and the second gate structure.

18. The laterally diffused metal-oxide-semiconductor device of claim 16, wherein the contact field plate and the first contact plug comprise the same material.

19. The laterally diffused metal-oxide-semiconductor device of claim 16, wherein the bottom surface of the contact field plate is lower than the bottom surface of the first contact plug.

20. The laterally diffused metal-oxide-semiconductor device of claim 16, wherein the top surface of the contact field plate is flush with the top surface of the first contact plug.

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