Back-side wafer failure location fixture and method

Abstract

This invention discloses a back-side wafer failure location fixture, comprising: a wafer protective film, for attaching to the front side of the wafer, forming a first opening that exposes the surface of the failed chip on the wafer; a frame, attached to the surface of the wafer protective film surrounding the failed chip, including multiple input pins and output pins, with each I / O pin connected to its corresponding input pin via a lead; and a wafer fixing device for fixing the wafer with its front side facing down. Multiple wires connecting the output pins to an external test system are disposed below the wafer fixing device. This invention also discloses a back-side wafer failure location method. This invention enables timely, simple, and rapid back-side gripping connection, improving failure analysis and location efficiency while ensuring wafer integrity and cleanliness.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a back-side wafer failure location fixture. This invention also relates to a back-side wafer failure location method. Background Technology

[0002] like Figure 1 The diagram shown is a structural schematic of an existing back-side wafer failure location fixture; existing back-side wafer failure location fixtures employ a manual probe station, including:

[0003] Needle seat 101, probe 102 disposed at the end of needle seat 101.

[0004] The probe 102 needs to be directly inserted into the wafer cleavage 103, which has a failed chip. The probe 102 needs to make contact with the I / O pins on the failed chip.

[0005] The probe 102 is connected to the external test system 105 via the wire 104.

[0006] The shard 103 is placed on the fixing device 106. The fixing device 106 has a transparent plate 107. The back side of the shard 103 is placed on the transparent plate 107.

[0007] A failure location device is provided above the fixing device 106. The failure location device is an EMMI device or an OBIRCH device.

[0008] The failure location device includes a lens 108 that directs a laser 109 from the back side of the wafer 201 into the wafer cleavage 103. Figure 2 As can be seen, the laser 109 passes through the transparent plate 107 and enters the wafer cleavage 103. The fixing device 106 also includes a light emission microscopy and positioning system 110 for realizing EMMI or OBIRCH functions.

[0009] Manual probe stations are commonly used auxiliary devices for failure analysis and localization in conjunction with EMMI / OBIRCH, but they have many shortcomings and limitations in the back-side gripping process:

[0010] 1. Needle holder 101 takes a long time to debug, and the needle holder fixture needs to be modified.

[0011] 2. There are requirements for the test channel. It is generally best not to exceed three to four pins, otherwise pin collisions are likely to occur.

[0012] 3. Backside pin piercing test often requires cracking the wafer to accurately locate the failed chip. However, cracked wafers cannot be shipped. Even if the wafer is not cracked, the surface will be contaminated during the analysis process, making it impossible to pass OQA and thus impossible to ship.

[0013] 4. The bottom needle insertion requires repeated confirmation of probe contact, which is difficult to debug and requires high skill from engineers. Summary of the Invention

[0014] The technical problem to be solved by this invention is to provide a back-side wafer failure location fixture that can achieve back-side gripping point connection in a timely, simple, and quick manner, thereby improving the efficiency of failure analysis and location while ensuring the integrity and cleanliness of the wafer. To this end, this invention also provides a back-side wafer failure location method.

[0015] To solve the above-mentioned technical problems, the back-side wafer failure positioning fixture provided by the present invention includes:

[0016] A wafer protective film is used to attach to the front side of a wafer; the wafer protective film has a first opening that exposes the surface of a failed chip on the wafer and covers the wafer surface outside the failed chip; the failed chip includes multiple I / O pins.

[0017] A frame is attached to the surface of the wafer protective film surrounding the failed chip; the frame includes multiple input pins and multiple output pins, with the output pins and input pins having the same number connected; each I / O pin is connected to the corresponding input pin via a lead.

[0018] A wafer fixing device for fixing and placing the wafer with the front side facing down.

[0019] Multiple wires are disposed below the wafer fixing device, with the first end of each wire connected to the corresponding output pin and the second end of each wire connected to an external testing system.

[0020] A further improvement is that the frame has a ring structure and surrounds the periphery of the first opening.

[0021] A further improvement is that the frame includes: a PCB board, an internal circuit board, or a lead substrate.

[0022] A further improvement is that the wafer fixing device is provided with a retaining ring, which is used to fix the wafer.

[0023] A further improvement is that a failure positioning device is provided above the wafer fixing device.

[0024] A further improvement is that the failure location device is an EMMI device or an OBIRCH device.

[0025] A further improvement is that the failure location device includes a lens that directs laser light from the back side of the wafer into the wafer.

[0026] To solve the above-mentioned technical problems, the back-side wafer failure location method provided by the present invention includes the following steps:

[0027] Step 1: Apply a wafer protective film to the front side of the wafer to form a first opening; the first opening exposes the surface of the failed chip on the wafer, and the wafer protective film covers the wafer surface outside the failed chip; the failed chip includes multiple I / O pins.

[0028] Step 2: Attach the frame to the surface of the wafer protective film surrounding the failed chip; the frame includes multiple input pins and multiple output pins, with the output pins and input pins having the same number connected together.

[0029] Step 3: Connect each of the IO pins to the corresponding input pins by wiring.

[0030] Step 4: Fix the wafer face down on the wafer fixing device.

[0031] Step 5: Install multiple wires below the wafer fixing device. The first end of each wire is connected to the corresponding output pin, and the second end of each wire is connected to an external testing system.

[0032] A further improvement is that the frame has a ring structure and surrounds the periphery of the first opening.

[0033] A further improvement is that the frame includes: a PCB board, an internal circuit board, or a lead substrate.

[0034] A further improvement is that the wafer fixing device is provided with a retaining ring, which is used to fix the wafer.

[0035] Further improvements include the following steps:

[0036] Step 6: Install a failure location device above the wafer fixing device and perform failure location.

[0037] A further improvement is that the failure location device is an EMMI device or an OBIRCH device.

[0038] A further improvement is that the failure location device includes a lens that directs laser light from the back side of the wafer into the wafer.

[0039] Further improvements include the following steps:

[0040] Step 7: Remove the wafer from the wafer holding device; remove the frame and the wafer protective film from the wafer in sequence.

[0041] This invention eliminates the need for wafer cleaving. Instead, a wafer protective film is applied to the wafer, and a first opening is formed at the location of the failed chip. A frame is then installed, and the I / O pins of the failed chip are connected to the input pins of the frame via lead wires. After the entire wafer is fixed on the wafer mounting device, the output pins of the frame are connected to an external testing system via wires. Therefore, this invention avoids the need to insert pins into the I / O pins of the failed chip, thus avoiding various defects associated with pin insertion, such as long pin socket debugging time, limited number of pin sockets for observation vias, the need for wafer cleaving, and the difficulty of pin insertion debugging. As a result, this invention has advantages such as no limit on the number of pin sockets, high connection stability, no need for wafer cleaving, ensuring the cleanliness of the wafer surface after analysis, and meeting shipping standards. It can achieve back-side gripping connection in a timely, simple, and quick manner, improving the efficiency of failure analysis and location while ensuring the integrity and cleanliness of the wafer. Attached Figure Description

[0042] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0043] Figure 1 This is a schematic diagram of an existing back-side wafer failure location fixture;

[0044] Figure 2 This is a schematic diagram of the structure of the back-side wafer failure positioning fixture according to an embodiment of the present invention;

[0045] Figure 3A This is a top view of the wafer structure in step one of the back-side wafer failure location method according to an embodiment of the present invention;

[0046] Figure 3B This is a cross-sectional view of the wafer after step one of the back-side wafer failure location method according to an embodiment of the present invention is completed;

[0047] Figure 4A This is a cross-sectional view of the wafer after step three of the back-side wafer failure location method according to an embodiment of the present invention.

[0048] Figure 4B yes Figure 4A Enlarged view of the middle frame location;

[0049] Figure 4C yes Figure 4A Cross-sectional structural diagram;

[0050] Figure 5 This is a top view of the wafer structure after step four of the back-side wafer failure location method according to an embodiment of the present invention is completed;

[0051] Figure 6 This is a cross-sectional view of the back-side wafer failure location method after step four is completed according to an embodiment of the present invention.

[0052] Figure 7A This is a cross-sectional view of the wafer being removed from the wafer fixing device in step seven of the back-side wafer failure location method according to an embodiment of the present invention.

[0053] Figure 7B This is a cross-sectional view of the back-side wafer failure location method after step seven is completed, according to an embodiment of the present invention. Detailed Implementation

[0054] like Figure 2 The diagram shown is a structural schematic of a back-side wafer failure positioning fixture according to an embodiment of the present invention; the back-side wafer failure positioning fixture according to an embodiment of the present invention includes:

[0055] A wafer protective film 202 is used to be attached to the front side of a wafer 201; the wafer protective film 202 has a first opening 203 that exposes the surface of a failed chip 201a of the wafer 201 and covers the surface of the wafer 201 outside the failed chip 201a; the failed chip 201a includes a plurality of I / O pins.

[0056] Frame 204 is attached to the surface of the wafer protective film 202 surrounding the failed chip 201a. Please also refer to... Figure 4B As shown, the frame 204 includes multiple input pins 204a and multiple output pins 204b, with the same numbered output pins 204b connected to the input pins 204a; each IO pin is connected to the corresponding input pin 204a via a lead 205.

[0057] In this embodiment of the invention, the frame 204 has a ring structure and surrounds the periphery of the first opening 203.

[0058] The frame 204 includes: a PCB board, an internal circuit board, or a lead substrate.

[0059] The wafer fixing device 207 is used to fix the wafer 201 with the front side of the wafer 201 facing down.

[0060] Multiple wires 206 are disposed below the wafer fixing device 207. The first end of each wire 206 is connected to the corresponding output pin 204b, and the second end of each wire 206 is connected to the external test system 209.

[0061] In this embodiment of the invention, the wafer fixing device 207 is provided with a retaining ring, which is used to fix the wafer 201. The retaining ring structure is as follows: Figure 5 As shown.

[0062] A failure location device is disposed above the wafer fixing device 207. The failure location device is an EMMI device or an OBIRCH device.

[0063] The failure location device includes a lens 210, which directs a laser 211 from the back side of the wafer 201 into the wafer 201. Figure 2 As can be seen, the wafer fixing device 207 also has a transparent plate 208, through which the laser 211 passes into the wafer 201. The wafer fixing device 207 also includes a light emission microscopy and positioning system 211 for implementing EMMI or OBIRCH functions.

[0064] This invention does not require dicing the wafer 201. Instead, after protecting the wafer 201 with a wafer protective film 202, a first opening 203 is formed at the failed chip 201a. Then, a frame 204 is installed, and the I / O pins of the failed chip 201a are connected to the input pins 204a of the frame 204 via lead wires 205. After the entire wafer 201 is fixed on the wafer fixing device 207, the output pins 204b of the frame 204 are connected to an external testing system 209 via wires 206. Therefore, this invention does not require... To achieve this, pins need to be inserted into the IO pins of the failed chip 201a. This avoids various defects associated with pin insertion, such as long pin socket debugging time, limited number of pin sockets for observing vias, need for wafer cleaving, and high debugging difficulty. Therefore, the embodiments of the present invention have advantages such as no limit on the number of pin sockets, high connection stability, no need for wafer cleaving, ensuring the cleanliness of the wafer 201 surface after analysis, and meeting shipping standards. It can achieve back-side gripping connection in a timely, simple, and quick manner, improve the efficiency of failure analysis and location, and at the same time ensure the integrity and cleanliness of the wafer 201.

[0065] The back-side wafer failure location method of this invention includes the following steps:

[0066] Step 1, such as Figure 3A As shown, Figure 3A As shown on the left, a wafer 201 is provided, on which a faulty chip 201a is provided. The faulty chip 201a has a marking.

[0067] like Figure 3A As shown in the middle, a wafer protective film 202 is provided.

[0068] like Figure 3A As shown on the right and combined Figure 3BAs shown, a wafer protective film 202 is attached to the front side of the wafer 201, forming a first opening 203. The first opening 203 exposes the surface of the failed chip 201a on the wafer 201, while the wafer protective film 202 covers the surface of the wafer 201 outside the failed chip 201a. The failed chip 201a includes multiple I / O pins. The position of the first opening 203 is located using the markings, and the markings need to be cleaned after the first opening 203 is formed.

[0069] Step 2, as follows Figure 4A As shown, the frame 204 is attached to the surface of the wafer protective film 202 surrounding the failed chip 201a.

[0070] like Figure 4B As shown, the frame 204 includes multiple input pins 204a and multiple output pins 204b, with the output pins 204b and the input pins 204a having the same number.

[0071] In the method of this embodiment of the invention, the frame 204 has a ring structure and surrounds the periphery of the first opening 203.

[0072] The frame 204 includes: a PCB board, an internal circuit board, or a lead substrate.

[0073] Step 3, as follows Figure 4B As shown and simultaneously combined Figure 4C As shown, each of the IO pins is connected to the corresponding input pin 204a by means of lead wire 205.

[0074] Step 4, as follows Figure 5 As shown, the wafer 201 is fixed face down on the wafer fixing device 207.

[0075] In the method of this embodiment of the invention, the wafer fixing device 207 is provided with a retaining ring, and the wafer 201 is fixed by the retaining ring.

[0076] Step 5, as follows Figure 6 As shown, multiple wires 206 are arranged below the wafer fixing device 207. The first end of each wire 206 is connected to the corresponding output pin 204b, and the second end of each wire 206 is connected to the external test system 209.

[0077] It also includes the following steps:

[0078] Step Six, as Figure 2 As shown, a failure location device is provided above the wafer fixing device 207 to perform failure location.

[0079] In the method of this invention embodiment, the failure location device is an EMMI device or an OBIRCH device.

[0080] The failure location device includes a lens 210, which directs a laser 211 from the back side of the wafer 201 into the wafer 201. Figure 2 As can be seen, the wafer fixing device 207 also has a transparent plate 208, through which the laser 211 passes into the wafer 201. The wafer fixing device 207 also includes a light emission microscopy and positioning system 211 for implementing EMMI or OBIRCH functions.

[0081] It also includes the following steps:

[0082] Step 7, as follows Figure 7A As shown, the wafer 201 is removed from the wafer fixing device 207.

[0083] like Figure 7B As shown, the frame 204 and the wafer protective film 202 are removed from the wafer 201 in sequence. Finally, the surface of the wafer 201 remains clean.

[0084] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A back-side wafer failure positioning fixture, characterized in that, include: A wafer protective film is used to be attached to the front side of a wafer; the wafer protective film has a first opening that exposes the surface of a failed chip on the wafer and covers the wafer surface outside the failed chip; the failed chip includes multiple I / O pins; A frame is attached to the surface of the wafer protective film surrounding the failed chip; the frame includes multiple input pins and multiple output pins, with the output pins and input pins having the same number connected; each I / O pin is connected to the corresponding input pin via a lead; A wafer fixing device for fixing and placing the wafer with the front side facing down; Multiple wires are disposed below the wafer fixing device, with the first end of each wire connected to the corresponding output pin and the second end of each wire connected to an external testing system.

2. The back-side wafer failure positioning fixture as described in claim 1, characterized in that: The frame has a ring structure and surrounds the periphery of the first opening.

3. The back-side wafer failure positioning fixture as described in claim 2, characterized in that: The framework includes: a PCB board, an internal circuit board, or a lead substrate.

4. The back-side wafer failure positioning fixture as described in claim 1, characterized in that: The wafer fixing device is provided with a retaining ring, which is used to fix the wafer.

5. The back-side wafer failure positioning fixture as described in claim 1, characterized in that: A failure location device is installed above the wafer fixing device.

6. The back-side wafer failure positioning fixture as described in claim 5, characterized in that: The failure location device is an EMMI device or an OBIRCH device.

7. The back-side wafer failure positioning fixture as described in claim 6, characterized in that: The failure location device includes a lens that directs laser light from the back side of the wafer into the wafer.

8. A back-side wafer failure location method, characterized in that, Includes the following steps: Step 1: Apply a wafer protective film to the front side of the wafer to form a first opening; the first opening exposes the surface of the failed chip on the wafer, and the wafer protective film covers the wafer surface outside the failed chip; The failed chip includes multiple I / O pins; Step 2: Attach the frame to the surface of the wafer protective film surrounding the failed chip; the frame includes multiple input pins and multiple output pins, with the output pins and input pins having the same number connected together; Step 3: Connect each of the IO pins to the corresponding input pins by wiring. Step 4: Fix the wafer face down on the wafer fixing device; Step 5: Install multiple wires below the wafer fixing device. The first end of each wire is connected to the corresponding output pin, and the second end of each wire is connected to an external testing system.

9. The back-side wafer failure location method as described in claim 8, characterized in that: The frame has a ring structure and surrounds the periphery of the first opening.

10. The back-side wafer failure location method as described in claim 9, characterized in that: The framework includes: a PCB board, an internal circuit board, or a lead substrate.

11. The back-side wafer failure location method as described in claim 10, characterized in that: The wafer fixing device is provided with a retaining ring, which is used to fix the wafer.

12. The back-side wafer failure location method as described in claim 8, characterized in that: It also includes the following steps: Step 6: Install a failure location device above the wafer fixing device and perform failure location.

13. The back-side wafer failure location method as described in claim 12, characterized in that: The failure location device is an EMMI device or an OBIRCH device.

14. The back-side wafer failure location method as described in claim 13, characterized in that: The failure location device includes a lens that directs laser light from the back side of the wafer into the wafer.

15. The back-side wafer failure location method as described in claim 12, characterized in that: It also includes the following steps: Step 7: Remove the wafer from the wafer holding device; remove the frame and the wafer protective film from the wafer in sequence.

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