Method for forming overlay alignment mark

Abstract

A method for forming overlay alignment marks includes: providing a substrate, the substrate including a marking region, the marking region including a first region, a second region, a third region, and a fourth region; forming a first mask structure on the marking region; forming a plurality of mutually separate first sacrificial layers on the first mask structure; and etching the first mask structure and the substrate using the plurality of first sacrificial layers as masks to form a plurality of fin alignment marks and a plurality of dummy fin alignment marks. By ensuring that the spacing between adjacent first sacrificial layers located in the first and second regions is equal to the spacing between adjacent first sacrificial layers located in the third and fourth regions, a consistent etching environment is ensured during the etching process using the plurality of first sacrificial layers as masks, resulting in consistent feature sizes for the ultimately formed fin alignment marks. This reduces the problem of center offset of the plurality of fin alignment marks, mitigates the impact of measurement errors, and improves the performance of the ultimately formed semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming an overlay alignment mark. Background Art

[0002] Photolithography is a crucial technology in semiconductor manufacturing, enabling the transfer of patterns from a mask onto the surface of a silicon wafer, creating semiconductor products that meet design requirements. The photolithography process begins with an exposure step, where light passes through the translucent or reflective areas of the mask onto a photoresist-coated silicon wafer, reacting photochemically with the photoresist. Next, a development step utilizes the solubility of the developer in the photosensitive and unsensitive photoresists to form a photoresist pattern, enabling the transfer of the mask pattern. Finally, an etching step involves etching the silicon wafer based on the photoresist pattern, further transferring the mask pattern to the wafer.

[0003] As lithographic feature sizes continue to decrease, the requirements for overlay accuracy and critical dimension uniformity in lithography machines are also increasing. Semiconductor device manufacturing typically involves dozens of lithography steps. To ensure the correspondence between each layer, the wafer must be aligned before lithography, allowing the pattern to be accurately transferred to the wafer's photoresist layer.

[0004] However, there are still many problems with the overlay alignment marks formed by the prior art. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming an overlay alignment mark, which can effectively improve the performance of a finally formed semiconductor structure.

[0006] To solve the above problems, the present invention provides a method for forming an overlay alignment mark, comprising: providing a substrate, the substrate comprising a mark area, the mark area comprising a first area, a second area, a third area and a fourth area adjacent to each other in sequence; forming a first mask structure on the mark area; forming a plurality of mutually discrete first sacrificial layers on the first mask structure, the first sacrificial layers adjacent to each other in the first area and the second area have a first spacing dimension, the first sacrificial layers adjacent to each other in the third area and the fourth area have a second spacing dimension, and the first spacing dimension is equal to the second spacing dimension; etching the first mask structure and the substrate using the plurality of first sacrificial layers as masks, forming a plurality of fin alignment marks on the first area and the fourth area, and forming a plurality of dummy fin alignment marks on the second area and the third area.

[0007] Optionally, the second area includes a first boundary area, and the first boundary area is adjacent to the first area; the third area includes a second boundary area, and the second boundary area is adjacent to the fourth area.

[0008] Optionally, after forming a plurality of mutually independent first sacrificial layers and before etching the first mask structure and the substrate using the plurality of first sacrificial layers as masks, the method further includes: removing a plurality of first sacrificial layers located on the first boundary region and the second boundary region.

[0009] Optionally, the method for removing several portions of the first sacrificial layer located on the first boundary area and the second boundary area includes: forming a patterned layer on the first mask structure, wherein the patterned layer exposes a portion of the first sacrificial layer; and using the patterned layer as a mask, etching and removing the exposed first sacrificial layer.

[0010] Optionally, the method for forming several first sacrificial layers on the first mask structure includes: forming several mutually discrete first graphic structures on the first mask structure; forming a first sacrificial material film on the top surface of the first mask structure and the first graphic structure, and the side wall of the first graphic structure; removing the first sacrificial material film located on the top surface of the first mask structure and the first graphic structure to form several first sacrificial layers; after forming several first sacrificial layers, removing the first graphic structure.

[0011] Optionally, the process for forming the first sacrificial material film includes an atomic layer deposition process.

[0012] Optionally, the method for forming several first graphical structures on the first mask structure includes: forming a second mask structure on the first mask structure; forming several mutually separate second sacrificial layers on the second mask structure; etching the second mask structure using the second sacrificial layer as a mask until the top surface of the first mask structure is exposed, thereby forming several first graphical structures.

[0013] Optionally, the method for forming several mutually discrete second sacrificial layers on the second mask structure includes: forming several mutually discrete second graphic structures on the second mask structure; forming a second sacrificial material film on the top surface of the second mask structure and the second graphic structure, and on the side wall of the second graphic structure; removing the second sacrificial material film located on the top surface of the second mask structure and the second graphic structure to form several second sacrificial layers; and removing the second graphic structure after forming several second sacrificial layers.

[0014] Optionally, the formation process of the second sacrificial material film includes an atomic layer deposition process.

[0015] Optionally, the method for forming a plurality of second graphical structures on the second mask structure includes: forming a third mask structure on the second mask structure; forming a plurality of third sacrificial layers separated from each other on the third mask structure; etching the third mask structure using the third sacrificial layer as a mask until the top surface of the second mask structure is exposed, thereby forming a plurality of second graphical structures.

[0016] Optionally, the dummy fin alignment mark includes a reserved area and a redundant area located on the reserved area.

[0017] Optionally, the method of etching the dummy fin alignment mark includes: removing a redundant area of ​​the dummy fin alignment mark.

[0018] Optionally, after etching the dummy fin alignment mark, the method further includes forming a spacer material film on the sidewalls and top surfaces of the fin alignment mark and the reserved area, and the top surface of the mark area.

[0019] Optionally, after forming the spacer material film, the method further includes: forming a dielectric layer on the spacer material film.

[0020] Optionally, the substrate further includes a device area, and the marking area surrounds the device area.

[0021] Optionally, in the process of forming a plurality of fin alignment marks and a plurality of dummy fin alignment marks, the method further includes: forming a plurality of mutually separate fins on the device region.

[0022] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0023] In the formation method of the technical solution of the present invention, a plurality of mutually separate first sacrificial layers are formed on the first mask structure, with adjacent first sacrificial layers located in the first and second regions having a first spacing dimension, and adjacent first sacrificial layers located in the third and fourth regions having a second spacing dimension, the first spacing dimension being equal to the second spacing dimension. This ensures that during the etching of the first mask structure and the substrate using the plurality of first sacrificial layers as masks, the etching environment remains consistent, resulting in consistent feature dimensions of the ultimately formed fin alignment marks. This reduces the problem of center offset of the plurality of fin alignment marks in the first and fourth regions, reduces the impact of measurement errors, and improves the performance of the ultimately formed semiconductor structure.

[0024] Furthermore, after forming a plurality of mutually separate first sacrificial layers and before etching the first mask structure and the substrate using the plurality of first sacrificial layers as masks, the method further includes removing a plurality of first sacrificial layers located in the boundary regions. By removing the plurality of first sacrificial layers located in the first boundary regions and the second boundary regions, the spacing between adjacent fin alignment marks and dummy fin alignment marks formed subsequently is increased, and during the subsequent removal of the dummy fin alignment marks, damage to the fin alignment marks is reduced, thereby alleviating the problem of center shift of the plurality of fin alignment marks in the first region and the fourth region.

[0025] Furthermore, the pseudo-fin alignment mark includes a reserved area and a redundant area located on the reserved area; the method for etching the pseudo-fin alignment mark includes: removing the redundant area of ​​the pseudo-fin alignment mark. As the process gradually advances to the back end, the film layers stacked on the overlay alignment mark become more and more complex, and the transmittance becomes lower and lower, which causes the signal of the overlay alignment mark to become weaker and weaker, and even reaches the limit of the machine's detection capability in the middle stage. The machine needs to extend the measurement time to accumulate sufficient measurement light intensity, which will greatly affect the working efficiency of the machine. By retaining the reserved area of ​​the pseudo-fin alignment mark, the reserved area can be used to enhance the signal strength of the overlay alignment mark, reduce the difficulty of machine detection, and effectively improve process efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1 to 2 It is a schematic diagram of the structure of an overlay alignment mark;

[0027] Figures 3 to 15 It is a schematic structural diagram of each step of an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0028] As described in the background art, the overlay alignment marks formed by the prior art still have many problems, which will be described in detail below with reference to the accompanying drawings.

[0029] Please refer to Figure 1 and Figure 2 , Figure 1 A top view of an overlay alignment mark. Figure 2 yes Figure 1In the cross-sectional schematic diagram along line AA, a substrate 100 is provided, wherein the substrate 100 includes a marking area, wherein the marking area includes a plurality of first areas I, and second areas II located between adjacent first areas I; a first mask structure (not shown) is formed on the substrate 100; a plurality of mutually separate first sacrificial layers (not shown) are formed on the first mask structure on the first areas I; after forming the first sacrificial layers, the first mask structure and the substrate 100 are etched using the plurality of first sacrificial layers as masks to form a plurality of fin alignment marks 101 on the first areas I.

[0030] In this embodiment, a number of mutually separate fin alignment marks 101 are formed in the mark region so that subsequent processes can find alignment positions, thereby ensuring etching accuracy.

[0031] However, in this embodiment, adjacent first sacrificial layers have a first dimension D1 between them in a direction parallel to the surface of the substrate 100, and the second region II has a second dimension D2, which is larger than the first dimension D1. When etching the first mask structure and the substrate 100 using the first sacrificial layers as masks, the sudden change in etching environment from the first dimension D1 to the second dimension D2 can easily increase the characteristic size of the fin alignment mark 100 located at the edge.

[0032] When the characteristic size of the fin alignment mark 100 located at the edge increases, the centers of several fin alignment marks 100 on the first region I are offset, which is likely to cause measurement errors during subsequent overlay alignment, thereby affecting the performance of the ultimately formed semiconductor structure.

[0033] On this basis, the present invention provides a method for forming an overlay alignment mark, by forming a plurality of mutually discrete first sacrificial layers on the first mask structure, and the first sacrificial layers adjacent to each other in the first area and the second area have a first spacing dimension, and the first sacrificial layers adjacent to each other in the third area and the fourth area have a second spacing dimension, and the first spacing dimension is equal to the second spacing dimension, ensuring that the etching environment remains consistent during the process of etching the substrate, so that the characteristic dimensions of each of the fin alignment marks finally formed remain consistent, thereby reducing the problem of center offset of the plurality of fin alignment marks on the first area, reducing the impact of measurement errors, and improving the performance of the finally formed semiconductor structure.

[0034] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] Figures 3 to 15 It is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0036] Please refer to Figure 3 and Figure 4 , Figure 3 A top view of an overlay alignment mark. Figure 4 yes Figure 3 In the cross-sectional view along line BB, a substrate 200 is provided. The substrate 200 includes a marking area A1. The marking area A1 includes a first area I, a second area II, a third area III and a fourth area IV that are adjacent to each other in sequence.

[0037] In this embodiment, the substrate 200 further includes a device area A2 ; and the marking area A1 surrounds the device area A2 .

[0038] Marking area A1 is used to form alignment marks during each photolithography process, providing a measurement reference for the device structures formed in device area A2. Device area A2 is used to form functional device structures. While device structures are being formed in device area A2, corresponding device structures are also formed in marking area A1 due to global process flow. However, the device structures formed in marking area A1 do not have any practical function.

[0039] In this embodiment, the second area II includes a first boundary area A1, which is adjacent to the first area I; the third area III includes a second boundary area A2, which is adjacent to the fourth area IV.

[0040] Please refer to Figure 5 , forming a first mask structure 201 on the marking area A1.

[0041] In this embodiment, the first mask structure 201 is also located on the device area A2 , and the first mask structure 201 also provides a mask for forming a device structure with actual functions on the device area A2 .

[0042] In this embodiment, the first mask structure 201 adopts a multi-layer structure; in other embodiments, the first mask structure may also adopt a single-layer structure.

[0043] After forming the first mask structure 201, the method further includes: forming a plurality of mutually separated first sacrificial layers on the first mask structure 201, wherein the first sacrificial layers adjacent to each other on the first region I and the second region II have a first spacing dimension, and the first sacrificial layers adjacent to each other on the third region III and the fourth region IV have a second spacing dimension, and the first spacing dimension is equal to the second spacing dimension. For the specific formation process of the first sacrificial layer, please refer to Figures 6 to 10 .

[0044] Please refer to Figure 6 A second mask structure 202 is formed on the first mask structure 201 ; a third mask structure 203 is formed on the second mask structure 202 ; and a plurality of separate third sacrificial layers 204 are formed on the third mask structure 203 .

[0045] Since the spacing between the first sacrificial layers finally formed is small, it is necessary to use a patterning process for pattern transfer multiple times to meet the spacing requirement between the first sacrificial layers.

[0046] In this embodiment, the second mask structure 202 and the third mask structure 203 both adopt a multi-layer structure; in other embodiments, the second mask structure and the third mask structure may also adopt a single-layer structure.

[0047] In this embodiment, the third sacrificial layer 204 is an initial pattern for subsequent pattern transfer.

[0048] Please refer to Figure 7 After forming the third sacrificial layer 204, the third mask structure 203 is etched using the third sacrificial layer 204 as a mask until the top surface of the second mask structure 202 is exposed, thereby forming a plurality of second graphical structures 205; a second sacrificial material film 206 is formed on the top surfaces of the second mask structure 202 and the second graphical structure 205, as well as on the sidewalls of the second graphical structure 205.

[0049] In this embodiment, the second sacrificial material film 206 is formed by an atomic layer deposition process.

[0050] In this embodiment, the material of the second sacrificial material film 206 is different from that of the second patterned structure 205 , so as to reduce damage to the subsequently formed second sacrificial layer during the subsequent removal of the second patterned structure 205 , thereby ensuring the accuracy of pattern transfer.

[0051] Please refer to Figure 8After forming the second sacrificial material film 206, the second sacrificial material film 206 located on the top surface of the second mask structure 202 and the second graphic structure 205 is removed to form a plurality of second sacrificial layers 207; after forming a plurality of second sacrificial layers 207, the second graphic structure 205 is removed.

[0052] In this embodiment, the process of removing the second sacrificial material film 206 located on the top surfaces of the second mask structure 202 and the second patterned structure 205 is a dry etching process.

[0053] In this embodiment, the process of removing the second patterned structure 205 adopts a wet etching process.

[0054] Please refer to Figure 9 After forming the second sacrificial layer 207, the second mask structure 202 is etched using the second sacrificial layer 207 as a mask until the top surface of the first mask structure 201 is exposed, thereby forming a plurality of first graphic structures 208; a first sacrificial material film 209 is formed on the top surfaces of the first mask structure 201 and the first graphic structure 208, as well as on the sidewalls of the first graphic structure 208.

[0055] In this embodiment, the first sacrificial material film 209 is formed by an atomic layer deposition process.

[0056] In this embodiment, the material of the first sacrificial material film 209 is different from that of the first patterned structure 208 , so as to reduce damage to the subsequently formed first sacrificial layer during the subsequent removal of the first patterned structure 208 , thereby ensuring the accuracy of pattern transfer.

[0057] Please refer to Figure 10 After forming the first sacrificial material film 209, the first sacrificial material film 209 located on the top surface of the first mask structure 201 and the first graphic structure 208 is removed to form several first sacrificial layers 210; after forming several first sacrificial layers 210, the first graphic structure 208 is removed.

[0058] In this embodiment, the first sacrificial layers 210 adjacent to each other on the first region I and the second region II have a first spacing dimension d1, and the first sacrificial layers 210 adjacent to each other on the third region III and the fourth region IV have a second spacing dimension d2, and the first spacing dimension d1 is equal to the second spacing dimension d2.

[0059] In this embodiment, the process of removing the first sacrificial material film 209 located on the top surfaces of the first mask structure 201 and the first patterned structure 208 is a dry etching process.

[0060] In this embodiment, the process of removing the first patterned structure 208 adopts a wet etching process.

[0061] Please refer to Figure 11 After forming a plurality of mutually separated first sacrificial layers 210 , a plurality of first sacrificial layers 210 located on the first boundary area A1 and the second boundary area A2 are removed.

[0062] In this embodiment, by removing several of the first sacrificial layers 210 located on the first boundary area A1 and the second boundary area A2, the spacing between the adjacent fin alignment marks and the pseudo fin alignment marks formed subsequently is increased. In the process of subsequently removing the pseudo fin alignment marks, the damage to the fin alignment marks is reduced, and the problem of center offset of several of the fin alignment marks on the first area I and the fourth area IV is reduced.

[0063] In this embodiment, the method for removing several portions of the first sacrificial layer 210 located on the first boundary area A1 and the boundary area A2 includes: forming a patterned layer on the first mask structure 201, wherein the patterned layer exposes a portion of the first sacrificial layer 210; and using the patterned layer as a mask, etching and removing the exposed first sacrificial layer 210.

[0064] In this embodiment, the process of etching and removing the exposed first sacrificial layer 210 is a wet etching process; in other embodiments, the process of etching and removing the exposed first sacrificial layer may also be a dry etching process.

[0065] Please refer to Figure 12 After removing several of the first sacrificial layers 210 located on the first boundary area A1 and the boundary area A2, the first mask structure 201 and the substrate 200 are etched using the several first sacrificial layers 210 as masks to form several fin alignment marks 211 on the first area I and the fourth area IV, and several dummy fin alignment marks 212 on the second area II and the third area III.

[0066] In this embodiment, by forming a plurality of mutually separate first sacrificial layers 210 on the first mask structure 201, with a first spacing dimension d1 between adjacent first sacrificial layers 210 located in the first region I and the second region II, and a second spacing dimension d2 between adjacent first sacrificial layers 210 located in the third region III and the fourth region IV, and the first spacing dimension d1 being equal to the second spacing dimension d2, a consistent etching environment is ensured during the etching process of the first mask structure 201 and the substrate 200 using the plurality of first sacrificial layers 210 as masks, resulting in consistent feature dimensions of the ultimately formed fin alignment marks 211. This reduces the problem of center offset of the plurality of fin alignment marks 211 in the first region I and the fourth region IV, reduces the impact of measurement errors, and improves the performance of the ultimately formed semiconductor structure.

[0067] In this embodiment, the process of forming the plurality of fin alignment marks 211 and the plurality of dummy fin alignment marks 212 also includes forming a plurality of separate fins (not shown) on the device area A2. Simultaneously forming the plurality of fins through a global process can effectively reduce the number of manufacturing steps and improve production efficiency.

[0068] In this embodiment, the dummy fin alignment mark 211 includes a reserved area B1 and a redundant area B2 located on the reserved area B1 .

[0069] Please refer to Figure 13 , the dummy fin alignment mark 212 is etched to reduce the height of the dummy fin alignment mark 212 .

[0070] In this embodiment, the method of etching the dummy fin alignment mark 212 includes: removing a redundant region B2 of the dummy fin alignment mark 212 .

[0071] As the process gradually advances to the back end, the film layers stacked on the overlay alignment mark become more and more complex, and the transmittance becomes lower and lower, which in turn causes the signal of the overlay alignment mark to become weaker and weaker. In the middle stage, it even reaches the limit of the machine's detection capability. The machine needs to extend the measurement time to accumulate sufficient measurement light intensity, which will greatly affect the machine's working efficiency. By retaining the reserved area B1 of the dummy fin alignment mark 212, the height of the reserved area B1 can meet the following requirements:

[0072]

[0073] Assume that there are m dielectric layers from the reserved area B1 upward to the shared dielectric plane, where n i is the refractive index of the i-th layer, T iis the thickness of the i-th dielectric layer; assuming that there are k dielectric layers from the fin alignment mark 211 upward to the shared dielectric plane, where n j ' is the refractive index of the jth layer, T j ' is the thickness of the j-th dielectric layer; λ is the wavelength of the OVL detection light.

[0074] According to the formula, the phase difference between the diffracted light from the top and the diffracted light from the bottom is half the wavelength λ (the one-way phase difference is one-quarter the wavelength, considering the round trip). Therefore, they interfere with each other at the boundary of the overlay mark, forming a sharper boundary and improving contrast. Therefore, using the reserved area B1 can enhance the signal strength of the overlay alignment mark, reduce the difficulty of tool detection, and effectively improve process efficiency.

[0075] Please refer to Figure 14 After the dummy fin alignment mark 212 is etched, a spacer material film 213 is formed on the sidewalls and top surfaces of the fin alignment mark 211 and the reserved area B1 , and the top surface of the mark area A1 .

[0076] In this embodiment, the spacer material film 213 is formed by an atomic layer deposition process.

[0077] Please refer to Figure 15 After forming the spacer material film 213 , the method further includes: forming a dielectric layer 214 on the spacer material film 213 .

[0078] In this embodiment, the dielectric layer 214 covers the fin alignment mark 211 and the reserved area B1 .

[0079] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming an overlay alignment mark, characterized in that: include: Providing a substrate, the substrate comprising a marking area, the marking area comprising a first area, a second area, a third area, and a fourth area adjacent to each other in sequence; forming a first mask structure on the marking area; forming a plurality of mutually separated first sacrificial layers on the first mask structure, wherein adjacent first sacrificial layers located on the first region and the second region have a first spacing dimension, and adjacent first sacrificial layers located on the third region and the fourth region have a second spacing dimension, and the first spacing dimension is equal to the second spacing dimension; Etching the first mask structure and the substrate using the first sacrificial layers as masks to form a plurality of fin alignment marks on the first region and the fourth region, and a plurality of dummy fin alignment marks on the second region and the third region; The dummy fin alignment mark is etched to reduce the height of the dummy fin alignment mark; wherein, The second area includes a first boundary area, and the first boundary area is adjacent to the first area; the third area includes a second boundary area, and the second boundary area is adjacent to the fourth area; After forming a plurality of mutually independent first sacrificial layers and before etching the first mask structure and the substrate using the plurality of first sacrificial layers as masks, the method further includes: removing a plurality of first sacrificial layers located on the first boundary region and the second boundary region.

2. The method for forming an overlay alignment mark according to claim 1, wherein: The method for removing several portions of the first sacrificial layer located on the first boundary area and the second boundary area includes: forming a patterned layer on the first mask structure, wherein the patterned layer exposes a portion of the first sacrificial layer; and etching and removing the exposed first sacrificial layer using the patterned layer as a mask.

3. The method for forming an overlay alignment mark according to claim 1, wherein: The method for forming several first sacrificial layers on the first mask structure includes: forming several mutually discrete first graphic structures on the first mask structure; forming a first sacrificial material film on the top surface of the first mask structure and the first graphic structure, and the side wall of the first graphic structure; removing the first sacrificial material film located on the top surface of the first mask structure and the first graphic structure to form several first sacrificial layers; after forming several first sacrificial layers, removing the first graphic structure.

4. The method for forming an overlay alignment mark according to claim 3, wherein: The first sacrificial material film is formed by an atomic layer deposition process.

5. The method for forming an overlay alignment mark according to claim 3, wherein: The method for forming a plurality of first graphical structures on the first mask structure includes: forming a second mask structure on the first mask structure; forming a plurality of mutually separate second sacrificial layers on the second mask structure; etching the second mask structure using the second sacrificial layer as a mask until the top surface of the first mask structure is exposed, thereby forming a plurality of first graphical structures.

6. The method for forming an overlay alignment mark according to claim 5, wherein: The method for forming a plurality of mutually discrete second sacrificial layers on the second mask structure includes: forming a plurality of mutually discrete second graphic structures on the second mask structure; forming a second sacrificial material film on the top surface of the second mask structure and the second graphic structure, and on the sidewall of the second graphic structure; removing the second sacrificial material film located on the top surface of the second mask structure and the second graphic structure to form a plurality of second sacrificial layers; and removing the second graphic structure after forming the plurality of second sacrificial layers.

7. The method for forming an overlay alignment mark according to claim 6, wherein: The second sacrificial material film is formed by an atomic layer deposition process.

8. The method for forming an overlay alignment mark according to claim 6, wherein: The method for forming a plurality of second graphical structures on the second mask structure includes: forming a third mask structure on the second mask structure; forming a plurality of third sacrificial layers separated from each other on the third mask structure; etching the third mask structure using the third sacrificial layer as a mask until the top surface of the second mask structure is exposed, thereby forming a plurality of second graphical structures.

9. The method for forming an overlay alignment mark according to claim 1, wherein: The dummy fin alignment mark includes a reserved area and a redundant area located on the reserved area.

10. The method for forming an overlay alignment mark according to claim 9, wherein: The method of etching the dummy fin alignment mark includes removing a redundant area of ​​the dummy fin alignment mark.

11. The method for forming an overlay alignment mark according to claim 10, wherein: After etching the dummy fin alignment mark, the method further includes forming a spacer material film on the sidewalls and top surfaces of the fin alignment mark and the reserved area, and the top surface of the mark area.

12. The method for forming an overlay alignment mark according to claim 11, wherein: After forming the spacer material film, the method further includes: forming a dielectric layer on the spacer material film.

13. The method for forming an overlay alignment mark according to claim 1, wherein: The substrate further includes a device region, and the mark region surrounds the device region.

14. The method for forming an overlay alignment mark according to claim 13, wherein: The process of forming a plurality of fin alignment marks and a plurality of dummy fin alignment marks further includes: forming a plurality of fins separated from each other on the device region.

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