Array substrate, manufacturing method thereof, and display panel

Abstract

The present application provides an array substrate, a manufacturing method thereof, and a display panel. The manufacturing method includes: providing a substrate including a functional region and a peripheral region; forming a gate located in the functional region and a first alignment mark located in the peripheral region; forming a gate insulating layer, with the first alignment mark exposed from the gate insulating layer; forming an active layer and a plurality of second alignment marks, when different second alignment marks are aligned with the first alignment mark, the stacked position of the active layer relative to the gate is different; forming a source-drain layer partially stacked on the active layer, and a third alignment mark for aligning with the first alignment mark to ensure a fixed stacked position of the source-drain layer relative to the gate, the gate, the active layer, and the source-drain layer together form a plurality of transistor groups, and each transistor group includes a main thin-film transistor and a secondary thin-film transistor. By using this manufacturing method, an array substrate including a main thin-film transistor and a secondary thin-film transistor with a target size difference can be manufactured to meet the viewing angle performance requirements of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to an array substrate, a manufacturing method thereof, and a display panel. Background Art

[0002] With the continuous development of display technologies, people's demand for the quality of display panels has been continuously increasing, especially the demand for large viewing angle displays is particularly obvious. In order to improve the viewing angle performance of display panels, display panels with a multi-domain pixel structure (hereinafter referred to as multi-domain display panels) have emerged and have been widely used.

[0003] In related technologies, a multi-domain display panel includes a main pixel region and a sub-pixel region each having at least one display picture domain, and also includes a main thin film transistor for controlling the domain of the main pixel region, a sub-thin film transistor for controlling the domain of the sub-pixel region, and a voltage dividing thin film transistor. As is well known to those skilled in the art, the size difference between the main thin film transistor and the sub-thin film transistor cannot be too large, otherwise the sub-thin film transistor is undercharged, resulting in low brightness and insufficient light transmittance in the sub-pixel region, affecting the display effect; the size difference between the main thin film transistor and the sub-thin film transistor cannot be too small either, otherwise the brightness in the sub-pixel region is not low enough, resulting in poor viewing angle of the display panel.

[0004] Therefore, how to reasonably design the size difference between the main thin film transistor and the sub-thin film transistor to improve the viewing angle performance of multi-domain display panels has become one of the key issues studied by those skilled in the art. Summary of the Invention

[0005] The present application provides an array substrate, a manufacturing method thereof, and a display panel. When manufacturing the array substrate of the display panel by using this method, the relative stacking positions of the source-drain layer and the active layer can be controlled during the process as needed, so as to manufacture an array substrate including a main thin film transistor and a sub-thin film transistor with a target size difference to meet the viewing angle performance requirements of the display panel.

[0006] To achieve the above object, in a first aspect, the present application provides a manufacturing method of an array substrate, including the following steps:

[0007] Provide a substrate, which includes a functional area and a peripheral area located outside the functional area;

[0008] Form a gate in the functional area and a first alignment mark in the peripheral area on the substrate;

[0009] Form a gate insulating layer on the gate and the substrate other than the gate, and the first alignment mark is exposed outside the gate insulating layer;

[0010] An active layer and a plurality of second alignment marks are formed on the gate insulating layer, and a target alignment mark among the plurality of second alignment marks is aligned with the first alignment mark. Wherein, when any of the second alignment marks is aligned with the first alignment mark, the active layer is stacked on the gate, and when different second alignment marks are aligned with the first alignment mark, the stacking position of the active layer relative to the gate is different;

[0011] A source-drain layer and a third alignment mark are formed on the active layer and the gate insulating layer outside the active layer. The third alignment mark is aligned with the target alignment mark and the first alignment mark. Wherein, the source-drain layer includes a source and a drain, and the source-drain layer is partially stacked on the active layer and jointly forms a plurality of transistor groups with the gate. Each transistor group includes a main thin-film transistor and a corresponding sub-thin-film transistor. When different second alignment marks are aligned with the first alignment mark, the stacking position of the source-drain layer relative to the active layer is different, the orthographic projection area of the channel region of the sub-thin-film transistor on the active layer is different, and the orthographic projection area of the channel region of the main thin-film transistor on the active layer remains unchanged;

[0012] A passivation layer is formed on the source-drain layer, and a first via hole and a second via hole penetrating through to the source-drain layer are formed in the passivation layer; and

[0013] A main pixel electrode and a sub-pixel electrode are formed on the passivation layer. The main pixel electrode is connected to the drain of the main thin-film transistor through the first via hole, and the sub-pixel electrode is connected to the drain of the sub-thin-film transistor through the second via hole.

[0014] In one embodiment, the main thin-film transistor and its corresponding sub-thin-film transistor are arranged in the horizontal direction, the first alignment mark, the third alignment mark, and the plurality of second alignment marks are located on at least one side of the peripheral area in the horizontal direction, and the plurality of second alignment marks are spaced apart in the vertical direction;

[0015] Alternatively, the main thin-film transistor and its corresponding sub-thin-film transistor are arranged in the vertical direction, the first alignment mark, the third alignment mark, and the plurality of second alignment marks are located on at least one side of the peripheral area in the vertical direction, and the plurality of second alignment marks are spaced apart in the horizontal direction.

[0016] In one embodiment, the manufacturing method further includes: when forming the gate and the first alignment mark, a plurality of scan lines located in the functional area are further formed on the substrate, and the plurality of scan lines extend in the horizontal direction and are parallel and spaced apart in the vertical direction;

[0017] When forming the source-drain layer and the third alignment mark, a plurality of data lines located in the functional region are further formed on the gate insulating layer. The plurality of data lines extend in the vertical direction and are parallelly and spaced apart in the horizontal direction. Each data line intersects with the plurality of scan lines;

[0018] Among them, the plurality of scan lines and the plurality of data lines intersect to define a plurality of pixel regions distributed in an array. The functional region includes the plurality of pixel regions. Each row of pixel regions corresponds to one scan line, each column of pixel regions corresponds to one data line. A transistor group is formed in each pixel region, and the gate in each pixel region is connected to the corresponding scan line, and the source of the source-drain layer in each pixel region is connected to the corresponding data line.

[0019] In one embodiment, the manufacturing method further includes: when forming the gate and the first alignment mark, a plurality of common electrode lines located in the functional region are further formed on the substrate. One common electrode line is provided on each side of the scan line corresponding to each pixel region;

[0020] Each transistor group further includes a voltage-dividing thin-film transistor. When different second alignment marks are aligned with the second alignment mark, the orthographic projection area of the channel region of the voltage-dividing thin-film transistor on the active layer remains unchanged;

[0021] Among them, the source of the voltage-dividing thin-film transistor is connected to the drain of the sub-thin-film transistor, and the two ends of the drain of the voltage-dividing thin-film transistor are respectively connected to two common electrode lines on the opposite sides of the scan line corresponding to the pixel region where it is located.

[0022] In a second aspect, the present application further provides another manufacturing method of an array substrate. The manufacturing method includes the following steps:

[0023] Provide a substrate including a functional region and a peripheral region located outside the functional region;

[0024] Form a gate located in the functional region and a first alignment mark located in the peripheral region on the substrate;

[0025] Form a gate insulating layer on the gate and the substrate outside the gate, and the first alignment mark is exposed outside the gate insulating layer;

[0026] Form an active layer and a second alignment mark on the gate insulating layer. The active layer is stacked on the gate. The second alignment mark is used to align with the first alignment mark to ensure the relative position of the active layer and the gate is fixed;

[0027] A source-drain layer and a plurality of third alignment marks are formed on the active layer and the gate insulating layer outside the active layer, and a target alignment mark among the plurality of third alignment marks is aligned with the second alignment mark. Wherein, the source-drain layer includes a source electrode and a drain electrode. When any one of the third alignment marks is aligned with the second alignment mark, the source-drain layer partially overlaps the active layer and jointly forms a plurality of transistor groups with the gate. Each transistor group includes a main thin-film transistor and a corresponding sub-thin-film transistor. When different third alignment marks are aligned with the second alignment mark, the area of the channel region of the sub-thin-film transistor projected onto the active layer is different, and the area of the channel region of the main thin-film transistor projected onto the active layer remains unchanged;

[0028] A passivation layer is formed on the source-drain layer, and a first via hole and a second via hole penetrating through to the source-drain layer are opened in the passivation layer; and

[0029] A main pixel electrode and a sub-pixel electrode are formed on the passivation layer. The main pixel electrode is connected to the drain electrode of the main thin-film transistor through the first via hole, and the sub-pixel electrode is connected to the drain electrode of the sub-thin-film transistor through the second via hole.

[0030] In one embodiment, the main thin-film transistor and its corresponding sub-thin-film transistor are arranged in a horizontal direction. The first alignment mark, the second alignment mark, and the plurality of third alignment marks are located on at least one side of the peripheral region in the horizontal direction, and the plurality of third alignment marks are spaced apart vertically;

[0031] Alternatively, the main thin-film transistor and its corresponding sub-thin-film transistor are arranged in a vertical direction. The first alignment mark, the second alignment mark, and the plurality of third alignment marks are located on at least one side of the peripheral region in the vertical direction, and the plurality of third alignment marks are spaced apart horizontally.

[0032] In one embodiment, the manufacturing method further includes: when forming the gate and the first alignment mark, a plurality of scan lines located in the functional region are further formed on the substrate. The plurality of scan lines extend in the horizontal direction and are parallel and spaced apart vertically;

[0033] When forming the source-drain layer and the third alignment mark, a plurality of data lines located in the functional region are further formed on the gate insulating layer. The plurality of data lines extend in the vertical direction and are parallel and spaced apart horizontally, and each data line intersects with the plurality of scan lines;

[0034] Among them, the multiple scanning lines and the multiple data lines intersect to define a plurality of pixel regions distributed in an array. The functional region includes the plurality of pixel regions. Each row of pixel regions corresponds to one of the scanning lines, and each column of pixel regions corresponds to one of the data lines. A transistor group is formed in each pixel region, and the gate in each pixel region is connected to the corresponding scanning line, and the source of the source-drain layer in each pixel region is connected to the corresponding data line.

[0035] In one embodiment, the manufacturing method further includes: when forming the gate and the first alignment mark, a plurality of common electrode lines located in the functional region are further formed on the substrate. One of the common electrode lines is provided on each side of the scanning line corresponding to each pixel region.

[0036] Each transistor group further includes a voltage-dividing thin-film transistor. When different third alignment marks are aligned with the second alignment mark, the orthographic projection area of the channel region of the voltage-dividing thin-film transistor on the active layer remains unchanged.

[0037] Among them, the source of the voltage-dividing thin-film transistor is connected to the drain of the sub-thin-film transistor, and the two ends of the drain of the voltage-dividing thin-film transistor are respectively connected to two of the common electrode lines on the opposite sides of the scanning line corresponding to the pixel region where it is located.

[0038] In a third aspect, the present application provides an array substrate manufactured by using the manufacturing method of the array substrate according to any one of the above embodiments.

[0039] In a fourth aspect, the present application provides a display panel, including a color filter substrate, a liquid crystal layer, and the above array substrate. The color filter substrate and the array substrate are disposed opposite to each other, and the liquid crystal layer is disposed between the color filter substrate and the array substrate.

[0040] Compared with the prior art, the beneficial effects of the present application are as follows: When manufacturing the array substrate of the display panel by using the manufacturing method provided by the present application, the relative stacking position of the source-drain layer and the active layer can be controlled during the manufacturing process as needed, so as to manufacture an array substrate including a main thin-film transistor and a sub-thin-film transistor with a target size difference, so as to meet the viewing angle performance requirements of the display panel.

[0041] The additional aspects and advantages of the present application will be partially given in the following description, partially become obvious from the following description, or be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] To more clearly illustrate the technical solutions of the embodiments of the present application, the accompanying drawings required for use in the embodiments of the present application will be briefly introduced below. Obviously, the accompanying drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0043] Figure 1 It is a flowchart of a method for manufacturing an array substrate provided by an embodiment of the present application.

[0044] Figure 2 It is a schematic diagram of an array substrate provided by an embodiment of the present application.

[0045] Figure 3 It is Figure 2 A structural diagram of one sub-pixel of the array substrate shown.

[0046] Figure 4 It is Figure 3 A partial cross-sectional view of the sub-pixel shown.

[0047] Figure 5 It is Figure 1 A schematic diagram corresponding to step S11 shown.

[0048] Figure 6 It is Figure 1 A schematic diagram corresponding to step S12 shown.

[0049] Figure 7 It is Figure 1 A schematic diagram corresponding to step S14 in one embodiment shown.

[0050] Figure 8 It is Figure 1 A schematic diagram corresponding to step S14 in another embodiment shown.

[0051] Figure 9 It is Figure 1 A schematic diagram corresponding to step S15 in one embodiment shown.

[0052] Figure 10 It is Figure 1 A schematic diagram corresponding to step S15 in another embodiment shown.

[0053] Figure 11 It is Figure 3 A partial enlarged view of the device area in one embodiment shown.

[0054] Figure 12 It is Figure 3 A partial enlarged view of the device area in another embodiment shown.

[0055] Figure 13It is a flowchart of another method for manufacturing an array substrate provided by an embodiment of the present application.

[0056] Figure 14 It is a schematic diagram of a display panel provided by an embodiment of the present application.

[0057] Figure 15 It is a schematic diagram of an electronic device provided by an embodiment of the present application.

[0058] Main component symbol description:

[0059] Substrate substrate 30

[0060] Functional area 31

[0061] Peripheral area 32

[0062] Gate 40

[0063] Gate insulating layer 50

[0064] Active layer 60

[0065] Source-drain layer 70

[0066] Source 71

[0067] Drain 72

[0068] Passivation layer 80

[0069] Array substrate 100

[0070] Color filter substrate 200

[0071] Liquid crystal layer 300

[0072] Pixel area 311

[0073] Housing 400

[0074] Display panel 1000

[0075] Electronic device 2000

[0076] Scan line Gate

[0077] Data line Data

[0078] Sub-pixel Px

[0079] Main pixel area MP

[0080] Sub-pixel area SP

[0081] Transistor group TG

[0082] Main thin film transistor T1

[0083] The secondary thin-film transistor T2

[0084] The voltage-dividing thin-film transistor T3

[0085] The first source electrode S1

[0086] The second source electrode S2

[0087] The third source electrode S3

[0088] The first drain Dr1

[0089] The second drain Dr2

[0090] The third drain Dr3

[0091] The device area DA

[0092] The pixel electrode layer P

[0093] The main pixel electrode P1

[0094] The secondary pixel electrode P2

[0095] The main trunk electrode P01

[0096] The branch electrode P02

[0097] The main common electrode line C1

[0098] The secondary common electrode line C2

[0099] The first via hole H1

[0100] The second via hole H2

[0101] The first channel area A1

[0102] The second channel area A2

[0103] The third channel area A3

[0104] The first alignment mark Mk1

[0105] The second alignment mark Mk2

[0106] The third alignment mark Mk3

[0107] The following specific embodiments will further illustrate the present application in conjunction with the above-mentioned drawings. Specific embodiments

[0108] Embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where like or similar reference numerals denote like or similar elements or elements having like or similar functions throughout. It can be understood that the embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as a limitation of the present application.

[0109] Please refer to Figures 1 to 4 , the present application provides a method for manufacturing an array substrate for manufacturing an array substrate 100. The array substrate 100 includes a substrate 30 and a pixel structure (not labeled in the figure) disposed on the substrate 30. The pixel structure includes a scan line Gate, a data line Data, a gate 40, a common electrode line, a gate insulating layer 50, an active layer 60, a source-drain layer 70, a passivation layer 80, and a pixel electrode layer P stacked on the substrate 30.

[0110] Specifically, as Figure 1 shown, the method for manufacturing the array substrate includes steps S11 to S17. Each step in the manufacturing method will be described in detail below with reference to Figures 2 to 12 .

[0111] Step S11, as Figure 2 and Figure 5 shown, provide a substrate 30, including a functional area 31 and a peripheral area 32 located outside the functional area 31. Among them, the functional area 31 includes a plurality of pixel areas 311 distributed in an array. Each pixel area 311 is used to correspondingly set a sub-pixel Px (Pixel, abbreviated as Px). The specific structure of the sub-pixel Px will be described in subsequent content.

[0112] In an embodiment of the present application, the substrate 30 may be a hard substrate made of a light-guiding and non-metallic material with a certain firmness such as glass, quartz, or common resin, or a flexible substrate made of a flexible material such as polyimide, which is not limited herein.

[0113] Step S12, as Figure 6 shown, form a gate 40 in the functional area 31 and a first alignment mark Mk1 (Mark1, abbreviated as Mk1) in the peripheral area 32 on the substrate 30. Preferably, as Figure 2 shown, in an embodiment of the present application, when forming the gate 40 and the first alignment mark Mk1, a plurality of scan lines Gate are also formed on the substrate 30 in the functional area 31. The plurality of scan lines Gate extend in the horizontal direction and are parallel and spaced apart in the vertical direction; further, as Figure 3As shown, when forming the gate 40 and the first alignment mark Mk1, a plurality of common electrode lines are also formed on the substrate 30 in the functional region 31. Specifically, a main common electrode line C1 and a secondary common electrode line C2 are correspondingly provided for each sub-pixel Px in each pixel region 311.

[0114] The specific formation process of the gate 40, the first alignment mark Mk1, the plurality of scan lines Gate, and the common electrode lines is as follows: A first metal layer is formed on the substrate 30, and the first metal layer is patterned through a first photomask process to obtain the gate 40, the first alignment mark Mk1, the plurality of scan lines Gate, and the common electrode lines. In the embodiment of the present application, the plurality of scan lines Gate, the gate 40, the common electrode lines, and the first alignment mark Mk1 are formed on the same first metal layer through the same photomask process, which is convenient for simplifying the manufacturing process and reducing the process difficulty.

[0115] Among them, the material of the first metal layer can be, but is not limited to, one or a combination of aluminum, molybdenum, chromium, copper, titanium, and molybdenum nitride, and is formed on the substrate 30 by physical vapor deposition or the like. Those skilled in the art can understand that the first photomask process specifically includes depositing a photoresist layer on the first metal layer, then providing a first photomask to expose the photoresist layer, and then developing the exposed photoresist layer to remove part of the material of the photoresist layer, so as to obtain a protection pattern corresponding to the scan line Gate, the gate 40, the common electrode lines, and the first alignment mark Mk1. Finally, the first metal layer is wet-etched to etch away the part of the first metal layer not covered by the protection pattern and retain the part covered by the protection pattern, thereby obtaining the scan line Gate, the gate 40, the common electrode lines, and the first alignment mark Mk1. Among them, as Figure 3 shown, the formed gate 40 and the scan line Gate are connected integrally.

[0116] Step S13, as Figure 4 shown, a gate insulating layer 50 is formed on the substrate 30 outside the gate 40 and the gate 40, and the first alignment mark Mk1 (not shown in the figure) is exposed outside the gate insulating layer 50. Optionally, the gate insulating layer 50 can cover the functional region 31 and the peripheral region 32 and expose the first alignment mark Mk1 by opening a via, or can only cover the functional region 31 to expose the first alignment mark Mk1, and this is not limited.

[0117] It should be noted that, in the embodiments of the present application, the gate insulating layer 50 covers the gate 40 and simultaneously covers the common electrode line (not shown in the figure) located on the substrate 30. The material of the gate insulating layer 50 can be, but is not limited to, at least one of silicon nitride and silicon oxide, and is formed on the substrate 30 by means such as chemical vapor deposition.

[0118] Step S14, please refer to Figure 4 、 Figure 7 and Figure 8 , an active layer 60 and a plurality of second alignment marks Mk2 (Mark2, hereinafter referred to as Mk2) are formed on the gate insulating layer 50, and the target alignment mark among the plurality of second alignment marks Mk2 is aligned with the first alignment mark Mk1. Among them, as Figure 4 shown, the active layer 60 is laminated on the gate 40 when any of the second alignment marks Mk2 is aligned with the first alignment mark Mk1, specifically on the surface of the gate insulating layer 50 covering the gate 40. The target alignment mark refers to the second alignment mark Mk2 among the plurality of second alignment marks Mk2 that is used to align with the first alignment mark Mk1 so that the active layer 60 is laminated at a specific or preset position on the gate 40. Depending on the relative position of the active layer 60 laminated on the gate 40, the target alignment mark is a different second alignment mark Mk2 among the plurality of second alignment marks Mk2.

[0119] The active layer 60 and the plurality of second alignment marks Mk2 can be obtained by forming a semiconductor layer on the gate insulating layer 50 and patterning the semiconductor layer through a second photomask process.

[0120] Among them, the material of the semiconductor layer can be, but is not limited to, amorphous silicon or polycrystalline silicon, and is formed on the gate insulating layer 50 by means such as chemical vapor deposition. Similar to the first photomask process, the second photomask process specifically includes depositing a photoresist layer on the semiconductor layer, then providing a second photomask to expose the photoresist layer, and then developing the exposed photoresist layer to remove part of the material of the photoresist layer, so as to obtain a protection pattern corresponding to the active layer 60 and the plurality of second alignment marks Mk2. Finally, the semiconductor layer is wet-etched to etch away the part of the semiconductor layer not covered by the protection pattern and retain the part covered by the protection pattern, thereby obtaining the active layer 60 and the plurality of second alignment marks Mk2.

[0121] It can be understood that the gate 40 and the first alignment mark Mk1 are respectively transferred from different protective patterns with fixed relative positions on the first photomask, and the positional relationship between the gate 40 and the first alignment mark Mk1 is relatively fixed; similarly, the active layer 60 and the multiple second alignment marks Mk2 are respectively transferred from different protective patterns with fixed relative positions on the second photomask, and the positional relationship between the active layer 60 and the multiple second alignment marks Mk2 is also relatively fixed; therefore, when different second alignment marks Mk2 are aligned with the first alignment mark Mk1, the stacking position of the active layer 60 relative to the gate 40 is different. That is to say, when performing step S14, by aligning the target alignment mark (which can be any of the second alignment marks Mk2) among the multiple second alignment marks Mk2 with the first alignment mark Mk1, the active layer 60 can be made to be in a specific or preset relative stacking position with respect to the gate 40. Specifically, as Figure 7 shown, in an embodiment of the present application, when the m-th second alignment mark Mk2 among the multiple second alignment marks Mk2 is aligned with the first alignment mark Mk1, the active layer 60 is relatively stacked at a first position ( Figure 7 the central region shown) of the gate 40; as Figure 8 shown, in another embodiment of the present application, when the n-th second alignment mark Mk2 (different from the m-th second alignment mark Mk2) among the multiple second alignment marks Mk2 is aligned with the first alignment mark Mk1, the active layer 60 is relatively stacked at a second position ( Figure 8 the top region shown) of the gate 40, and the second position is offset by a certain distance compared to the aforementioned first position. It is not difficult to understand that the offset distance and direction are the same as the interval distance and direction of the n-th second alignment mark Mk2 relative to the m-th second alignment mark Mk2.

[0122] Step S15, please refer to Figure 3 、 Figure 4 、 Figure 9 and Figure 10 to form a source-drain layer 70 and a third alignment mark Mk3 (Mark3, abbreviated as Mk3) on the gate insulating layer 50 outside the active layer 60 and the active layer 60, and the third alignment mark Mk3 is aligned with the target alignment mark and the first alignment mark Mk1. It should be noted that the third alignment mark Mk3 and the aforementioned first alignment mark Mk1 and second alignment marks Mk2 can all be but are not limited to marks of any shape such as cross-shaped marks, one-shaped marks, and star-shaped marks, as long as they can achieve the alignment function, and there is no limitation in this regard. In the embodiments of the present application, any of the alignment marks is a cross-shaped mark.

[0123] It should also be noted that, in combination with Figures 2 to 4 , in step S15, when forming the source-drain layer and the third alignment mark, a plurality of data lines Data located in the functional area 31 are further formed on the gate insulating layer 50. The plurality of data lines Data extend in the vertical direction and are parallelly and spaced apart in the horizontal direction. Each data line Data intersects with the plurality of scan lines Gate. Thus, the plurality of scan lines Gate and the plurality of data lines Data intersect to define the aforementioned plurality of pixel areas 311 distributed in an array. Specifically, as Figure 1 shown, in the embodiment of the present application, each pixel area 311 is located between two adjacent data lines Data and corresponds to one scan line Gate. The scan line Gate extends horizontally across the corresponding pixel area 311; furthermore, each row of pixel areas 311 corresponds to the same scan line Gate, and each column of pixel areas 311 corresponds to the same data line Data.

[0124] The specific formation process of the source-drain layer 70, the third alignment mark Mk3, and the plurality of data lines Data is as follows: A second metal layer is formed on the active layer 60 and the gate insulating layer 50 outside the active layer 60, and the second metal layer is patterned through a third photomask process to obtain the source-drain layer 70, the third alignment mark Mk3, and the plurality of data lines Data. In the embodiment of the present application, the source-drain layer 70 and the plurality of data lines Data are formed in the same second metal layer through the same photomask process, which is also beneficial to simplifying the manufacturing process and reducing the process difficulty.

[0125] Among them, the material of the second metal layer can be, but is not limited to, one or a combination of aluminum, molybdenum, chromium, copper, titanium, and molybdenum nitride, and is formed on the active layer 60 and the gate insulating layer 50 outside the active layer 60 by physical vapor deposition or other methods. Similar to the aforementioned first photomask process and second photomask process, the third photomask process specifically includes depositing a photoresist layer on the second metal layer, then providing a third photomask to expose the photoresist layer, and then developing the exposed photoresist layer to remove part of the material of the photoresist layer, so as to obtain a protection pattern corresponding to the source-drain layer 70 and the plurality of data lines Data. Finally, the second metal layer is wet-etched to etch away the part of the second metal layer not covered by the protection pattern and retain the part covered by the protection pattern, thereby obtaining the source-drain layer 70 and the plurality of data lines Data.

[0126] As Figure 4As shown, the formed source-drain layer 70 includes a source 71 and a drain 72, and the source-drain layer 70 is partially stacked on the active layer 60. It can be understood that the source-drain layer 70 and the third alignment mark Mk3 are respectively transferred from different protection patterns with fixed relative positions on the third photomask, and the positional relationship between the source-drain layer 70 and the third alignment mark Mk3 is relatively fixed. As described above, the positional relationship between the gate 40 and the first alignment mark Mk1 is also relatively fixed. Therefore, when the third alignment mark Mk3 is aligned with the first alignment mark Mk1, the stacking position of the source-drain layer 70 relative to the gate 40 is relatively fixed; further, as described above, when different second alignment marks Mk2 are aligned with the first alignment mark Mk1, the stacking position of the active layer 60 relative to the gate 40 is different. It can be seen that when different second alignment marks Mk2 are used as the target alignment marks to align with the first alignment mark Mk1, and the third alignment mark Mk3 is aligned with the first alignment mark Mk1 and the target alignment mark, the stacking position of the source-drain layer 70 relative to the active layer 60 is different.

[0127] That is to say, after performing step S14, by aligning the target alignment mark (which can be any one of the second alignment marks Mk2) with the first alignment mark Mk1, the active layer 60 and the gate 40 can be in a specific or preset relative stacking position. Furthermore, after performing step S15, the source-drain layer 70 and the active layer 60 are also in a specific or preset relative stacking position. Specifically, please refer to Figure 7 and Figure 9 , in an embodiment of the present application, when the m-th second alignment mark Mk2 among the plurality of second alignment marks Mk2 is aligned with the first alignment mark Mk1, the active layer 60 is relatively stacked at the first position of the gate 40 ( Figure 7 the central region shown), after the source-drain layer 70 fixed relative to the gate 40 is stacked on the active layer 60, the source-drain layer 70 and the active layer 60 have a first relative stacking position (see Figure 9 ); please refer to Figure 8 and Figure 10 , in another embodiment of the present application, when the n-th second alignment mark Mk2 (different from the m-th second alignment mark Mk2) among the plurality of second alignment marks Mk2 is aligned with the first alignment mark Mk1, the active layer 60 is relatively stacked at the second position of the gate 40 ( Figure 8 the top region shown), after the source-drain layer 70 fixed relative to the gate 40 is stacked on the active layer 60, the source-drain layer 70 and the active layer 60 have a second relative stacking position (seeFigure 10 )。From Figure 9 and Figure 10 it can be seen that the first relative stacking position and the second relative stacking position between the source-drain layer 70 and the active layer 60 are significantly different. Similar to the offset of the aforementioned second position relative to the first position, the second relative stacking position is also offset by a certain distance compared to the first relative stacking position. It is not difficult to understand that the distance and direction of the offset are the same as the interval distance and direction of the nth second alignment mark Mk2 relative to the mth second alignment mark Mk2.

[0128] Please refer to Figure 3 , Figure 4 and Figure 11 . Those skilled in the art will understand that the source-drain layer 70 includes a source electrode 71 and a drain electrode 72 arranged at intervals. The mutually stacked source-drain layer 70, the active layer 60 and the gate electrode 40 together form a plurality of transistor groups TG (Transistor Group, abbreviated as TG). Specifically, as Figure 11 shown, each transistor group TG includes a main thin-film transistor T1 and its corresponding sub-thin-film transistor T2 and voltage-dividing thin-film transistor T3. Each transistor in the transistor group TG includes a gate electrode, a source electrode and a drain electrode. The gate electrode of each transistor is connected to the scan line Gate corresponding to the sub-pixel Px where it is located, so as to control the conduction or cut-off of the corresponding transistor through the level state of the scan signal transmitted by the scan line Gate. Among them, the source electrodes of the main thin-film transistor T1, the sub-thin-film transistor T2 and the voltage-dividing thin-film transistor T3 are respectively defined as the first source electrode S1, the second source electrode S2 and the third source electrode S3, and the drain electrodes of the main thin-film transistor T1, the sub-thin-film transistor T2 and the voltage-dividing thin-film transistor T3 are respectively defined as the first drain electrode Dr1, the second drain electrode Dr2 and the third drain electrode Dr3. It should be noted that, as Figure 11 shown, in the embodiment of the present application, the second source electrode S2 is connected to the first source electrode S1, and the first source electrode S1 is connected to the data line Data corresponding to the sub-pixel Px where it is located.

[0129] Step S16, please refer to Figure 3 , Figure 4 and Figure 11 . A passivation layer 80 is formed on the source-drain layer 70, and a first via hole H1 (see Figure 11 ) and a second via hole H2 (see Figure 11 ) penetrating through the source-drain layer 70 are opened on the passivation layer 80. Among them, a part of the first drain electrode Dr1 of the main thin-film transistor T1 is exposed in the first via hole H1, and a part of the second drain electrode Dr2 of the sub-thin-film transistor T2 is exposed in the second via hole H2.

[0130] Specifically, the first vias H1 and the second vias H2 can be obtained by patterning the passivation layer 80 through a fourth photomask process. The material of the passivation layer 80 includes at least one of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, titanium oxide, and zinc oxide, and is formed on the source-drain layer 70 by chemical vapor deposition or the like. Similar to the previous photomask processes, the fourth photomask process specifically includes depositing a photoresist layer on the passivation layer 80, then providing a fourth photomask to expose the photoresist layer, and then developing the exposed photoresist layer to remove some of the material of the photoresist layer, so as to obtain a protection pattern corresponding to the first vias H1 and the second vias H2. Finally, the passivation layer 80 is wet-etched to etch away the portion of the passivation layer 80 not covered by the protection pattern and retain the portion covered by the protection pattern, thereby obtaining the first vias H1 and the second vias H2. It should be noted that in the embodiments of the present application, the passivation layer 80 on the source-drain layer 70 corresponding to each transistor group TG is provided with the first vias H1 and the second vias H2.

[0131] Step S17, please refer to Figure 3 , Figure 4 and Figure 11 , to form a main pixel electrode P1 and a sub-pixel electrode P2 on the passivation layer 80. The main pixel electrode P1 is connected to the first drain Dr1 of the main thin-film transistor T1 through the first via H1, and the sub-pixel electrode P2 is connected to the second drain Dr2 of the sub-thin-film transistor T2 through the second via H2.

[0132] As Figure 4As shown, the main pixel electrode P1 and the sub-pixel electrode P2 can be obtained by patterning a pixel electrode layer P covering the passivation layer 80 through a fifth photomask process. Among them, the material of the pixel electrode layer P includes, but is not limited to, indium tin oxide, indium zinc oxide, or aluminum zinc oxide, preferably indium tin oxide, and is formed on the passivation layer 80 (including in the first via hole H1 and the second via hole H2 in the passivation layer 80) by physical vapor deposition or the like. Similar to the foregoing photomask process, the fifth photomask process specifically includes depositing a photoresist layer on the pixel electrode layer P, then providing a fifth photomask to expose the photoresist layer, and then developing the exposed photoresist layer to remove part of the material of the photoresist layer, so as to obtain a protection pattern corresponding to the main pixel electrode P1 and the sub-pixel electrode P2. Finally, the pixel electrode layer P is wet-etched to etch away the part of the pixel electrode layer P not covered by the protection pattern and retain the part covered by the protection pattern, thereby obtaining the main pixel electrode P1 and the sub-pixel electrode P2. The parts of the pixel electrode layer P located in the first via hole H1 and the second via hole H2 are respectively connected to the first drain Dr1 and the second drain Dr2.

[0133] It should be noted that, as Figure 3 shown, in the embodiment of the present application, each sub-pixel Px in each pixel region 311 includes a main pixel region MP (Main Pixel, abbreviated as MP), a sub-pixel region SP (Sub Pixel, abbreviated as SP), and a device region DA (Device Area, abbreviated as DA) arranged in the vertical direction. The device region DA is located between the main pixel region MP and the sub-pixel region SP. The main pixel region MP and the sub-pixel region SP are respectively located on opposite sides of the scan line Gate corresponding to the sub-pixel Px where they are located. Among them, the main pixel electrode P1 is provided in the main pixel region MP, the sub-pixel electrode P2 is provided in the sub-pixel region SP, and the aforementioned transistor group TG is provided in the device region DA. The transistor group TG is used to control the charging of the main pixel electrode P1 and the sub-pixel electrode P2, and to adjust the voltage difference between the main pixel electrode P1 and the sub-pixel electrode P2, thereby changing the display state (including brightness and color level) of the sub-pixel Px. Each sub-pixel Px is any one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The multiple sub-pixels Px cooperate with each other to display a picture with different color levels.

[0134] Specifically, as Figure 11As shown, the gate of the main thin-film transistor T1 is integrally connected to the corresponding scan line Gate. The first source electrode S1 and the first drain electrode Dr1 are respectively connected to the data line Data corresponding to the sub-pixel Px where they are located and the main pixel electrode P1. In this way, the main pixel electrode P1 is connected to the corresponding data line Data and scan line Gate through the main thin-film transistor T1, and the main thin-film transistor T1 can control the charging of the main pixel electrode P1. Specifically, the on or off state of the main thin-film transistor T1 is controlled by the level state of the scan signal transmitted through the scan line Gate. When the main thin-film transistor T1 is on, the main pixel electrode P1 accesses the data signal transmitted by the data line Data for charging, and the potential in the main pixel electrode P1 can be changed. On the contrary, when the main thin-film transistor T1 is off, the main pixel electrode P1 cannot access the data signal and stops charging. Similarly, the gate of the secondary thin-film transistor T2 is integrally connected to the corresponding scan line Gate. The second source electrode S2 and the second drain electrode Dr2 are respectively connected to the data line Data corresponding to the sub-pixel Px where they are located and the secondary pixel electrode P2, so that the secondary pixel electrode P2 is connected to the corresponding data line Data and scan line Gate through the secondary thin-film transistor T2, and the secondary thin-film transistor T2 can control the charging of the secondary pixel electrode P2, which will not be elaborated here. In addition, the gate of the voltage-dividing thin-film transistor T3 is integrally connected to the corresponding scan line Gate. The third source electrode S3 is connected to the second drain electrode Dr2 and then connected to the secondary pixel electrode P2. The opposite ends of the third drain electrode Dr3 are respectively connected to two common electrode lines on the opposite sides of the scan line Gate corresponding to the pixel region 311 where it is located. Specifically, the opposite ends of the third drain electrode Dr3 are respectively connected to the main common electrode line C1 and the secondary common electrode line C2. The voltage-dividing thin-film transistor T3 is used to transfer the charge in the secondary pixel electrode P2 of the sub-pixel Px to the common electrode line when it is on, so as to realize the potential adjustment of the secondary pixel electrode P2 of the sub-pixel Px, and further adjust the voltage difference between the main pixel electrode P1 and the secondary pixel electrode P2 of the sub-pixel Px, so as to achieve the purpose of changing the display state of the sub-pixel Px.

[0135] Preferably, as Figure 3 shown, in the embodiment of the present application, the main pixel electrode P1 and the secondary pixel electrode P2 of each sub-pixel Px both include a main trunk electrode P01 and a branch electrode P02 connected to each other. The main trunk electrode P01 divides the main pixel region MP and the secondary pixel region SP into multiple domain regions (not limited to Figure 3 shown 4). The branch electrodes P02 in each domain region are parallel and spaced apart and form a predetermined angle with the main trunk electrode P01 (not limited to Figure 3Set at 45 degrees as shown, the orientations of the branch electrodes P02 in different domains are different, so that the main pixel electrode P1 and the sub-pixel electrode P2 form a pixel electrode structure in a cross shape. As is well known to those skilled in the art, when the main pixel electrode P1 and the sub-pixel electrode P2 are respectively connected to the corresponding scan signal and data signal to achieve charging, the deflection angles of the liquid crystal molecules corresponding to the multiple domains included in the main pixel region MP are different, and the deflection angles of the liquid crystal molecules corresponding to the multiple domains included in the sub-pixel region SP are also different. Since the potentials of the main pixel electrode P1 and the sub-pixel electrode P2 of each sub-pixel Px are different, the deflection angles of the liquid crystal molecules corresponding to the multiple domains included in the main pixel region MP and the deflection angles of the liquid crystal molecules corresponding to the multiple domains included in the sub-pixel region SP are different. In other words, in Figure 3 In the example of, there are multiple different deflection angles of the liquid crystal molecules corresponding to the multiple domains in each sub-pixel Px, so that multi-domain display can be achieved, which is beneficial to improving the color shift problem.

[0136] As is well known to those skilled in the art, for each sub-pixel Px, the size of the main thin-film transistor T1 will affect its own charging ability, and thus affect the display brightness when the main pixel electrode P1 works. Similarly, the size of the sub-thin-film transistor T2 will affect the display brightness when the sub-pixel electrode P2 works, and the difference between the display brightness when the main pixel electrode P1 works and the display brightness when the sub-pixel electrode P2 works will affect the viewing angle performance of the display panel including the array substrate 100. Therefore, the size difference between the main thin-film transistor T1 and the sub-thin-film transistor T2 needs to be reasonably designed.

[0137] The size of any thin-film transistor in the transistor group TG is positively correlated with the area of the positive projection of its channel region on the active layer 60. In other words, when the other sizes of the thin-film transistor (such as the thickness of each layer structure) remain unchanged, the larger the area of the positive projection of the channel region on the active layer 60, the larger the size of the thin-film transistor. As Figure 4 shown, the channel region of each thin-film transistor refers to the part of the active layer 60 located between the source electrode 71 and the drain electrode 72, and the area of the positive projection of the channel region on the active layer 60 is also the area of the interval region between the source electrode 71 and the drain electrode 72 of the corresponding thin-film transistor located on the active layer 60 and spaced relatively. Specifically, as Figure 11As shown, in the transistor group TG of each sub-pixel Px, the area of the interval region between the relatively spaced-apart portions of the first source electrode S1 and the first drain electrode Dr1 of the main thin-film transistor T1 on the active layer (not labeled in the figure), that is, the area of the positive projection of the channel region of the main thin-film transistor T1 on the active layer (not labeled in the figure) (defined as the first channel area A1); the area of the interval region between the relatively spaced-apart portions of the second source electrode S2 and the second drain electrode Dr2 of the secondary thin-film transistor T2 on the active layer, that is, the area of the positive projection of the channel region of the secondary thin-film transistor T2 on the active layer (defined as the second channel area A2); the area of the interval region between the relatively spaced-apart portions of the third source electrode S3 and the third drain electrode Dr3 of the voltage-dividing thin-film transistor T3 on the active layer, that is, the area of the positive projection of the channel region of the voltage-dividing thin-film transistor T3 on the active layer (defined as the third channel area A3).

[0138] It should be emphasized that, as Figure 9 and Figure 10 shown, in the embodiment of the present application, when performing step S14, different second alignment marks Mk2 can be correspondingly controlled to align with the first alignment mark Mk1 according to different viewing angle performance requirements, so that the stacking position of the source-drain layer 70 relative to the active layer 60 is different, thereby keeping the first channel area A1 and the third channel area A3 unchanged while the second channel area A2 is different.

[0139] It can be understood that during the process of manufacturing the array substrate 100, if only the corresponding channel area of any one of the thin-film transistors in the transistor group TG changes, the second channel area A2 is determined, and the size of the secondary thin-film transistor T2 is determined. Since the size of the main thin-film transistor T1 remains unchanged, the size difference between the main thin-film transistor T1 and the secondary thin-film transistor T2 is determined, and the display brightness difference between the main pixel electrode P1 and the secondary pixel electrode P2 is also determined. That is, the display panel including the array substrate 100 has a corresponding specific viewing angle performance. That is to say, during the process of manufacturing the array substrate 100 by using the manufacturing method provided in the present application, there is a one-to-one mapping relationship among the second channel area A2, the size difference between the main thin-film transistor T1 and the secondary thin-film transistor T2, and the viewing angle performance of the multi-domain display panel including the manufactured array substrate 100.

[0140] Among them, when different second alignment marks Mk2 are aligned with the first alignment mark Mk1, the second channel area A2 will also correspond differently. Therefore, when any second alignment mark Mk2 is aligned with the first alignment mark Mk1, the size difference between the main thin film transistor T1 and the secondary thin film transistor T2 is unique, and the viewing angle performance of the display panel of the manufactured array substrate 100 is also unique. It is not difficult to understand that through a large number of statistical tests, different second alignment marks Mk2 are aligned with the first alignment mark Mk1 to manufacture a variety of different array substrates 100, and further statistically analyze the viewing angle performance of the display panels including different array substrates 100, and the corresponding mapping relationship can be obtained.

[0141] For different manufacturers, the viewing angle performance requirements of the display panels they produce are mostly different. When the display panel needs to meet specific viewing angle performance, it can be inversely deduced from the above mapping relationship that there should be a corresponding target size difference (or specific size difference) between the main thin film transistor T1 and the secondary thin film transistor T2 included in the array substrate 100 of the display panel. Further backtracking shows that the secondary thin film transistor T2 has a corresponding second channel area A2, and the corresponding second channel area A2 is obtained by aligning a specific second alignment mark Mk2 (i.e., the target alignment mark) among the multiple second alignment marks Mk2 with the first alignment mark Mk1 and performing the aforementioned steps S14 and S15. Therefore, when manufacturing the array substrate 100 using the manufacturing method provided in this application, based on the mapping relationship obtained from the above statistical tests, the target alignment mark among the multiple second alignment marks Mk2 can be aligned with the first alignment mark Mk1 to control the source-drain layer 70 and the active layer 60 to be in a preset relative stacked position, and further manufacture a secondary thin film transistor T2 with a second channel area A2 of a specific size, and further manufacture an array substrate 100 including the main thin film transistor T1 and the secondary thin film transistor T2 with a target size difference, so that the display panel including the array substrate 100 meets specific viewing angle performance requirements. Among them, the target size difference between the main thin film transistor T1 and the secondary thin film transistor T2 refers to the size difference between the main thin film transistor T1 and the secondary thin film transistor T2 in the array substrate 100 when the display panel including the array substrate 100 has specific viewing angle performance. It can be understood that for different display panels that meet different viewing angle performances, the target size differences between the main thin film transistor T1 and the secondary thin film transistor T2 in each display panel included are different, which will not be elaborated here.

[0142] Specifically, please refer to again Figure 3 、 Figure 9 and Figure 11, in an embodiment of the present application, the main thin-film transistor T1 and its corresponding sub-thin-film transistor T2 are arranged in a horizontal direction and are located on one side of the device region DA of the corresponding sub-pixel Px in the horizontal direction, and the voltage-dividing thin-film transistor T3 is disposed on the other side of the device region DA in the horizontal direction.

[0143] As Figure 11 shown, both the first source electrode S1 and the second source electrode S2 are U-shaped and have different opening directions. After the first source electrode S1 and the second source electrode S2 are connected together, they are connected to the corresponding data line Data. Among them, the positive projection of the first source electrode S1 on the active layer is located in the active layer corresponding to the main thin-film transistor T1, and the positive projection of the second source electrode S2 on the active layer is partially located on the active layer corresponding to the sub-thin-film transistor T2 and partially located outside the corresponding active layer. Specifically, one end of the second source electrode S2 close to the U-shaped opening is located outside the active layer. The first drain electrode Dr1 extends in the vertical direction and partially extends into the first source electrode S1, and the second drain electrode Dr2 extends in the vertical direction and partially extends into the second source electrode S2. One end of the third source electrode S3 is connected to the second drain electrode Dr2, and the other end extends in the vertical direction to cross the active layer corresponding to the voltage-dividing thin-film transistor T3, and the third drain electrode Dr3 extends substantially in the vertical direction and crosses the active layer corresponding to the voltage-dividing thin-film transistor T3. In this embodiment, by arranging the main thin-film transistor T1, the sub-thin-film transistor T2, and the voltage-dividing thin-film transistor T3 in this way, it is beneficial to reduce the occupied area of the device region DA, increase the effective light-transmitting area of the main pixel region MP and the sub-pixel region SP, and thus improve the aperture ratio of the sub-pixel Px.

[0144] As Figure 9 shown, in this embodiment, the first alignment mark Mk1, the third alignment mark Mk3, and the plurality of second alignment marks Mk2 are located on at least one side of the peripheral region 32 in the horizontal direction, and the plurality of second alignment marks Mk2 are spaced apart in the vertical direction. Preferably, the plurality of second alignment marks Mk2 are spaced apart in a straight line in the vertical direction. It can be understood that when different second alignment marks Mk2 are aligned with the first alignment mark Mk1 during the execution of step S14, it is equivalent to offsetting the active layer 60 in the vertical direction, thereby changing the relative stacking position between the active layer 60 and the source-drain electrode layer 70.

[0145] Among them, it should be noted that the distance between the two outermost second alignment marks Mk2 in the vertical direction among the multiple second alignment marks Mk2 is smaller than the distance between any end of the first source electrode S1 in the vertical direction and the corresponding side edge of the active layer, and is also smaller than the distance between one end of the second source electrode S2 close to the U-shaped opening and the corresponding side edge of the active layer, and the distance between any end of the third source electrode S3 in the vertical direction and the corresponding side edge of the active layer. It can be understood that in this embodiment, since the orthographic projection of the first source electrode S1 on the active layer is located in the active layer corresponding to the main thin-film transistor T1, the orthographic projection of the second source electrode S2 on the active layer is partially located on the active layer corresponding to the sub-thin-film transistor T2 and the other part is located outside the active layer, the third source electrode S3 straddles the active layer corresponding to the voltage-dividing thin-film transistor T3, and the distances between the first source electrode S1, the second source electrode S2, and the third source electrode S3 and the corresponding edges of the active layer are designed as defined above. When different second alignment marks Mk2 are aligned with the first alignment mark Mk1, that is, when the relative stacked position between the active layer 60 and the source-drain layer 70 is offset in the vertical direction, the orthographic projection of the first source electrode S1 is always located in the active layer (i.e., the overlapping area between the first source electrode S1 and the active layer remains unchanged), the overlapping area between the second source electrode S2 and the active layer corresponding to the sub-thin-film transistor T2 is different, and the overlapping area between the third source electrode S3 and the active layer corresponding to the voltage-dividing thin-film transistor T3 also remains unchanged. As a result, the first channel area A1 of the main thin-film transistor T1 remains unchanged, the second channel area A2 of the sub-thin-film transistor T2 is different, and the third channel area A3 of the voltage-dividing thin-film transistor T3 also remains unchanged. In this way, according to different viewing angle performance requirements, by controlling the target alignment mark among the multiple second alignment marks Mk2 to be aligned with the first alignment mark Mk1 so that the second channel area A2 is a specific value, a sub-thin-film transistor T2 with a specific size of the second channel area A2 can be fabricated, so that the finally fabricated array substrate 100 includes the main thin-film transistor T1 and the sub-thin-film transistor T2 with target size differences to meet the viewing angle performance requirements of the display panel including the array substrate 100.

[0146] Specifically, in Figure 11In the illustrated embodiment, when the active layer 60 is vertically upwardly offset, the first channel area A1 and the third channel area A3 remain unchanged, while the second channel area A2 increases. Thus, the charging ability of the main thin film transistor T1 and the discharging ability of the voltage dividing thin film transistor T3 remain unchanged, and the charging ability of the secondary thin film transistor T2 becomes stronger as its size increases, making the display brightness of the secondary pixel electrode P2 brighter, and the overall brightness of the array substrate 100 can be improved; conversely, when the active layer 60 is vertically downwardly offset, the first channel area A1 and the third channel area A3 still remain unchanged, while the second channel area A2 decreases. Thus, the charging ability of the secondary thin film transistor T2 becomes weaker as its size decreases, making the display brightness of the secondary pixel electrode P2 darker, and thus the viewing angle performance of the array substrate 100 can be improved.

[0147] Please refer to again Figure 3 、 Figure 9 and Figure 12 , in another embodiment of the present application, the main thin film transistor T1 and its corresponding secondary thin film transistor T2 are arranged vertically and are located on one side in the horizontal direction of the device area DA of the corresponding sub-pixel Px, and the voltage dividing thin film transistor T3 is arranged on the other side in the horizontal direction of the device area DA.

[0148] As Figure 12 shown, the first source electrode S1 and the second source electrode S2 are source electrode sheets connected together. The source electrode sheet extends horizontally to one end and is connected to the corresponding data line Data. The first drain electrode Dr1 and the second drain electrode Dr2 are respectively arranged on opposite sides of the source electrode sheet in the vertical direction. The overall of the first drain electrode Dr1 and the second drain electrode Dr2 extends substantially horizontally. The source electrode sheet and the first drain electrode Dr1 horizontally span the active layer corresponding to the thin film transistor. The second drain electrode Dr2 is partially stacked on the active layer, and the end of the second drain electrode Dr2 close to the data line Data extends beyond the active layer. One end of the third source electrode S3 is connected to the second drain electrode Dr2, and the other end extends vertically to cross the active layer corresponding to the voltage dividing thin film transistor T3. The third drain electrode Dr3 extends substantially vertically and crosses the active layer corresponding to the voltage dividing thin film transistor T3. In Figure 12 the example of, by arranging the main thin film transistor T1, the secondary thin film transistor T2 and the voltage dividing thin film transistor T3 in this way, the occupied area of the device area DA can also be reduced, the effective light-transmitting area of the main pixel area MP and the secondary pixel area SP can be increased, and thus the aperture ratio of the sub-pixel Px can be increased. In addition, compared with Figure 11In the example, the first source electrode S1 and the second source electrode S2 are both U-shaped and arranged with different opening directions. In Figure 12 the example, the first source electrode S1 and the second source electrode S2 are source electrode sheets connected integrally and extending in the horizontal direction, with a simpler shape, which is convenient for reducing the process difficulty.

[0149] In Figure 12 the example, since the main thin film transistor T1 and the secondary thin film transistor T2 are arranged in the vertical direction, therefore, the first alignment mark Mk1, the third alignment mark Mk3, and the plurality of second alignment marks Mk2 are located on at least one side of the peripheral area 32 in the vertical direction, and the plurality of second alignment marks Mk2 are spaced apart in the horizontal direction. Preferably, the plurality of second alignment marks Mk2 are spaced apart in the horizontal direction on the same straight line. Thus, when performing step S14, when aligning different second alignment marks Mk2 with the first alignment mark Mk1, it is equivalent to offsetting the active layer 60 in the horizontal direction, thereby changing the relative stacking position between the active layer 60 and the source-drain electrode layer 70.

[0150] Among them, it should be noted that the distance between the two outermost second alignment marks Mk2 among the multiple second alignment marks Mk2 in the horizontal direction is smaller than the distance between any end of the first source electrode S1 in the horizontal direction and the corresponding side edge of the active layer, and is smaller than the distance between the end of the second source electrode S2 far from the data line Data and the corresponding side edge of the active layer, and the distance between the side of the third source electrode S3 close to the data line Datad in the horizontal direction and the corresponding side edge of the active layer. It can be understood that in this embodiment, since the source electrode sheet and the first drain electrode Dr1 span the active layer corresponding to the thin film transistor in the horizontal direction, the second drain electrode Dr2 is partially stacked on the active layer and the end of the second drain electrode Dr2 close to the data line Data extends beyond the active layer, the third source electrode S3 extends vertically to span the active layer corresponding to the voltage dividing thin film transistor T3, and the distances between the first source electrode S1, the second source electrode S2, and the third source electrode S3 and the corresponding edges of the active layer are defined as above, it can be ensured that when different second alignment marks Mk2 are aligned with the first alignment mark Mk1, that is, when the relative stacking position between the active layer 60 and the source-drain electrode layer 70 is offset in the horizontal direction, the source electrode sheet and the first drain electrode Dr1 always span the active layer, the overlapping area between the second drain electrode Dr2 and the active layer corresponding to the sub-thin film transistor T2 is different, and the overlapping area between the third source electrode S3 and the active layer corresponding to the voltage dividing thin film transistor T3 remains unchanged, so that the first channel area A1 of the main thin film transistor T1 remains unchanged, the second channel area A2 of the sub-thin film transistor T2 is different, and the third channel area A3 of the voltage dividing thin film transistor T3 also remains unchanged. Similarly, in Figure 12 In the example of

[0151] Specifically, in Figure 12In the illustrated embodiment, when the active layer 60 is horizontally offset to the right, the first channel area A1 and the third channel area A3 remain unchanged, while the second channel area A2 increases. Thus, the charging ability of the main thin film transistor T1 and the discharging ability of the voltage dividing thin film transistor T3 remain unchanged, and the charging ability of the secondary thin film transistor T2 becomes stronger as its size increases, making the display brightness of the secondary pixel electrode P2 brighter, and the overall brightness of the array substrate 100 can be improved. Conversely, when the active layer 60 is vertically offset to the left, the first channel area A1 and the third channel area A3 still remain unchanged, while the second channel area A2 decreases. Thus, the charging ability of the secondary thin film transistor T2 becomes weaker as its size decreases, making the display brightness of the secondary pixel electrode P2 darker, thereby improving the viewing angle performance of the array substrate 100.

[0152] In summary, when manufacturing the array substrate 100 using the manufacturing method of the array substrate provided by one embodiment of the present application, the relative stacking positions of the source-drain layer 70 and the active layer 60 in the array substrate 100 can be controlled during the manufacturing process as needed, so that on the premise of keeping the sizes of the main thin film transistor T1 and the voltage dividing thin film transistor T3 unchanged, a secondary thin film transistor T2 with a specific size can be manufactured, and then an array substrate 100 including the main thin film transistor T1 and the secondary thin film transistor T2 with a target size difference can be manufactured to meet the viewing angle performance requirements of the display panel.

[0153] Please refer to Figure 13 , the manufacturing method of the array substrate provided by another embodiment of the present application can also be used to manufacture the array substrate 100. Specifically, as Figure 13 shown, the manufacturing method of the array substrate provided by another embodiment of the present application includes steps S21 to S27. Among them, the contents of steps S21 - S23, S26, and S27 respectively correspond to and are the same as the contents of steps S11 - S13, S16, and S17 in the manufacturing method of the array substrate shown in Figure 1 and will not be elaborated here.

[0154] Different from Figure 1 the steps S14 and S15 in the manufacturing method of the array substrate shown, in the manufacturing method of the array substrate provided by another embodiment of the present application, the steps S24 and S25 specifically include:

[0155] Step S24, please refer to Figure 4, an active layer 60 and a second alignment mark Mk2 are formed on the gate insulating layer 50. The active layer 60 is stacked on the gate 40, and the second alignment mark Mk2 is used to align with the first alignment mark Mk1 to ensure the relative positions of the active layer 60 and the gate 40 are fixed. Similar to the foregoing step S14, the active layer 60 and the second alignment mark Mk2 can be obtained by forming a semiconductor layer on the gate insulating layer 50 and patterning the semiconductor layer through a second photomask process. The formation and patterning process of the semiconductor layer can refer to the description of step S14 in the foregoing embodiments and will not be elaborated herein.

[0156] Step S25, please refer to Figure 4 , a source-drain layer 70 and a plurality of third alignment marks Mk3 are formed on the active layer 60 and the gate insulating layer 50 outside the active layer 60. The target alignment mark among the plurality of third alignment marks Mk3 aligns with the second alignment mark Mk2. The source-drain layer 70 includes a source electrode 71 and a drain electrode 72. When any one of the third alignment marks Mk3 aligns with the second alignment mark Mk2, the source-drain layer 70 partially overlaps the active layer 60 and together with the gate 40 forms a plurality of transistor groups TG (see Figure 11 ). Each transistor group TG includes a main thin-film transistor T1 and corresponding sub-thin-film transistors T2 and voltage-dividing thin-film transistors T3. Similar to the foregoing step S15, the source-drain layer 70 and the plurality of third alignment marks Mk3 can be obtained by forming a second metal layer on the active layer 60 and the gate insulating layer 50 outside the active layer 60 and patterning the second metal layer through a third photomask process. The formation and patterning process of the second metal layer can refer to the description of step S15 in the foregoing embodiments and will not be elaborated herein either.

[0157] In Figure 13 the embodiment shown, the structures and functions of the first alignment mark Mk1, the second alignment mark Mk2, and the third alignment mark Mk3 can refer to the relevant descriptions in the foregoing embodiments and will not be elaborated herein.

[0158] It should be emphasized that in Figure 13 the manufacturing method of the array substrate shown, the number of the second alignment marks Mk2 is set to one, while the number of the third alignment marks Mk3 is set to multiple. Thus, there is only one stacking position of the formed active layer 60 relative to the gate 40, while there can be multiple stacking positions of the formed source-drain layer 70 relative to the active layer 60. Those skilled in the art can understand that by using Figure 13When fabricating the array substrate 100 by the method for fabricating the array substrate as shown, during the execution of step S25, by aligning the target alignment mark (which can be any one of the third alignment marks Mk3) with the second alignment mark Mk2, the source-drain layer 70 and the active layer 60 can be made to be in a specific or preset relative stacked position. Therefore, in Figure 13 In the embodiment as shown, different third alignment marks Mk3 can be correspondingly controlled to align with the second alignment mark Mk2 according to different viewing angle performance requirements, so that the stacked position of the source-drain layer 70 relative to the active layer 60 is different, and further the second channel area A2 corresponding to the sub-thin film transistor T2 is different, while the first channel area A1 corresponding to the main thin film transistor T1 and the third channel area A3 corresponding to the voltage-dividing thin film transistor T3 remain unchanged. Similar to the foregoing embodiment, based on the mapping relationship obtained through statistical experiments, the target alignment mark among the multiple third alignment marks Mk3 is aligned with the first alignment mark Mk1 to control the source-drain layer 70 and the active layer 60 to be in a preset relative stacked position, and further fabricate a sub-thin film transistor T2 having a second channel area A2 of a specific size, and further fabricate an array substrate 100 including the main thin film transistor T1 and the sub-thin film transistor T2 having a target size difference, so that the display panel including the array substrate 100 can meet specific viewing angle performance requirements.

[0159] In this application, when Figure 1 fabricating the array substrate 100 by the method for fabricating the array substrate as shown, the stacked position of the active layer 60 relative to the gate 40 can be controlled during the manufacturing process as needed, and further the source-drain layer 70 and the active layer 60 can be controlled to be in a preset relative stacked position, so as to fabricate an array substrate 100 including a main thin film transistor T1 and a sub-thin film transistor T2 having a target size difference to meet the viewing angle performance requirements of the display panel. Different from Figure 1 the method for fabricating the array substrate as shown, when Figure 13 fabricating the array substrate 100 by the method for fabricating the array substrate as shown, the source-drain layer 70 and the active layer 60 can be directly controlled to be in a preset relative stacked position during the manufacturing process as needed, and an array substrate 100 including a main thin film transistor T1 and a sub-thin film transistor T2 having a target size difference can also be fabricated to meet the viewing angle performance requirements of the display panel.

[0160] It should be noted that the array substrate 100 fabricated by Figure 13 the method for fabricating the array substrate as shown also includes the structure and functions of the array substrate 100 in any of the foregoing embodiments. For more detailed content, reference can be made to the foregoing relevant descriptions, and details will not be elaborated herein.

[0161] Based on the same inventive concept, an embodiment of the present application further provides an array substrate 100, which includes an array substrate 100 having a main thin film transistor T1 and a secondary thin film transistor T2 with a preset size difference to meet the viewing angle performance requirements of the display panel. Among them, the array substrate 100 can be made by using the manufacturing method of the array substrate shown in Figure 1 or can be made by using the manufacturing method of the array substrate shown in Figure 13 , and there is no limitation in this regard. The array substrate 100 at least has all the beneficial effects brought by the technical solutions of any of the above embodiments. For a more specific description, reference can be made to the foregoing related content, and details will not be repeated here.

[0162] Please refer to Figure 14 . The present application further provides a display panel 1000, which includes an array substrate 100, a color filter substrate 200, and a liquid crystal layer 300. The color filter substrate 200 and the array substrate 100 are disposed opposite to each other, and the liquid crystal layer 300 is disposed between the color filter substrate 200 and the array substrate 100.

[0163] Among them, the array substrate 100 can be made by using the manufacturing method of the array substrate described in any of the above embodiments, and thus at least has all the beneficial effects brought by the technical solutions of the above embodiments. For a more specific description, reference can be made to the foregoing related content, and details will not be repeated here.

[0164] It should be noted that the color filter substrate 200 and the liquid crystal layer 300 respectively have the same structures and functions as the existing color filter substrate and liquid crystal layer, and details will not be repeated here.

[0165] Among them, the display panel 1000 can be but is not limited to a TN (Twisted Nematic) display panel, an IPS (In-Plane Switching) display panel, and there is no specific limitation in this regard.

[0166] Further, please refer to Figure 15 . The present application further provides an electronic device 2000, which includes a housing 400 and the display panel 1000 described above, and the display panel 1000 is disposed on the housing 400. It can be understood that in the electronic device 2000 provided by the present application, since the array substrate 100 of its display panel 1000 is made by using the manufacturing method of the array substrate described in any of the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments. For a more specific description, reference can be made to the foregoing related content, and details will not be repeated here.

[0167] Among them, the electronic device 2000 may be a mobile terminal. For example, a mobile phone, a laptop computer, a tablet computer, a wrist-worn device, etc. The electronic device 2000 may also be a household electronic device with a display panel, such as a television, an air conditioner, etc., or any other electronic device with a display panel, which is not limited herein.

[0168] In the description of this specification, the description referring to terms such as "embodiment", "specific embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in a suitable manner in any one or more embodiments or examples.

[0169] Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present application. The scope of the present application is defined by the claims and their equivalents.

Claims

1. A manufacturing method of an array substrate, characterized in that, it includes: providing a substrate, which includes a functional area and a peripheral area located outside the functional area; forming a gate in the functional area and a first alignment mark in the peripheral area on the substrate; forming a gate insulating layer on the gate and the substrate outside the gate, and the first alignment mark is exposed outside the gate insulating layer; forming an active layer and a plurality of second alignment marks on the gate insulating layer, and a target alignment mark among the plurality of second alignment marks is aligned with the first alignment mark. Wherein, when any of the second alignment marks is aligned with the first alignment mark, the active layer is stacked on the gate, and when different second alignment marks are aligned with the first alignment mark, the stacking position of the active layer relative to the gate is different; forming a source-drain layer and a third alignment mark on the active layer and the gate insulating layer outside the active layer, and the third alignment mark is aligned with the target alignment mark and the first alignment mark. Wherein, the source-drain layer includes a source and a drain, and the source-drain layer is partially stacked on the active layer and together with the gate forms a plurality of transistor groups. Each transistor group includes a main thin-film transistor and a corresponding sub-thin-film transistor. When different second alignment marks are aligned with the first alignment mark, the stacking position of the source-drain layer relative to the active layer is different, the positive projection area of the channel region of the sub-thin-film transistor on the active layer is different, and the positive projection area of the channel region of the main thin-film transistor on the active layer remains unchanged; forming a passivation layer on the source-drain layer, and forming a first via hole and a second via hole penetrating through to the source-drain layer on the passivation layer; and forming a main pixel electrode and a sub-pixel electrode on the passivation layer, the main pixel electrode is connected to the drain of the main thin-film transistor through the first via hole, and the sub-pixel electrode is connected to the drain of the sub-thin-film transistor through the second via hole.

2. The manufacturing method of the array substrate according to claim 1, characterized in that, the main thin-film transistor and its corresponding sub-thin-film transistor are arranged in the horizontal direction, the first alignment mark, the third alignment mark and the plurality of second alignment marks are located on at least one side in the horizontal direction of the peripheral area, and the plurality of second alignment marks are spaced apart in the vertical direction; or, the main thin-film transistor and its corresponding sub-thin-film transistor are arranged in the vertical direction, the first alignment mark, the third alignment mark and the plurality of second alignment marks are located on at least one side in the vertical direction of the peripheral area, and the plurality of second alignment marks are spaced apart in the horizontal direction.

3. The manufacturing method of the array substrate according to claim 1 or 2, characterized in that, the manufacturing method further includes: when forming the gate and the first alignment mark, a plurality of scan lines located in the functional area are further formed on the substrate, and the plurality of scan lines extend in the horizontal direction and are parallel and spaced apart in the vertical direction; When forming the source-drain layer and the third alignment mark, a plurality of data lines located in the functional region are further formed on the gate insulating layer. The plurality of data lines extend in the vertical direction and are parallelly and spacedly distributed in the horizontal direction. Each of the data lines intersects with the plurality of scan lines; Wherein, the plurality of scan lines and the plurality of data lines intersect to define a plurality of pixel regions distributed in an array. The functional region includes the plurality of pixel regions. Each row of pixel regions corresponds to one of the scan lines, and each column of pixel regions corresponds to one of the data lines. A transistor group is formed in each pixel region, and the gate in each pixel region is connected to the corresponding scan line, and the source of the source-drain layer in each pixel region is connected to the corresponding data line.

4. The manufacturing method of the array substrate according to claim 3, characterized in that, the manufacturing method further includes: When forming the gate and the first alignment mark, a plurality of common electrode lines located in the functional region are further formed on the substrate. A common electrode line is provided on each side of the scan line corresponding to each pixel region; Each transistor group further includes a voltage-dividing thin-film transistor. When different second alignment marks are aligned with the second alignment mark, the area of the positive projection of the channel region of the voltage-dividing thin-film transistor on the active layer remains unchanged; Wherein, the source of the voltage-dividing thin-film transistor is connected to the drain of the sub-thin-film transistor, and the two ends of the drain of the voltage-dividing thin-film transistor are respectively connected to two common electrode lines on the opposite sides of the scan line corresponding to the pixel region where it is located.

5. A manufacturing method of an array substrate, characterized in that, comprising: providing a substrate including a functional region and a peripheral region located outside the functional region; forming a gate located in the functional region and a first alignment mark located in the peripheral region on the substrate; forming a gate insulating layer on the gate and the substrate other than the gate, and the first alignment mark is exposed from the gate insulating layer; forming an active layer and a second alignment mark on the gate insulating layer. The active layer is stacked on the gate, and the second alignment mark is used to align with the first alignment mark to ensure the relative position of the active layer and the gate is fixed; forming a source-drain layer and a plurality of third alignment marks on the active layer and the gate insulating layer other than the active layer. The target alignment mark among the plurality of third alignment marks is aligned with the second alignment mark. Wherein, the source-drain layer includes a source and a drain. When any one of the third alignment marks is aligned with the second alignment mark, the source-drain layer partially overlaps with the active layer and jointly forms a plurality of transistor groups with the gate. Each transistor group includes a main thin-film transistor and a corresponding sub-thin-film transistor. When different third alignment marks are aligned with the second alignment mark, the area of the positive projection of the channel region of the sub-thin-film transistor on the active layer is different, and the area of the positive projection of the channel region of the main thin-film transistor on the active layer remains unchanged; A passivation layer is formed on the source-drain layer, and a first via hole and a second via hole penetrating through the passivation layer to the source-drain layer are formed on the passivation layer; and A main pixel electrode and a sub-pixel electrode are formed on the passivation layer. The main pixel electrode is connected to the drain of the main thin-film transistor through the first via hole, and the sub-pixel electrode is connected to the drain of the sub-thin-film transistor through the second via hole.

6. The method for manufacturing an array substrate according to claim 5, characterized in that the main thin-film transistor and its corresponding sub-thin-film transistor are arranged in the horizontal direction, the first alignment mark, the second alignment mark and the plurality of third alignment marks are located on at least one side of the peripheral area in the horizontal direction, and the plurality of third alignment marks are spaced apart vertically; alternatively, the main thin-film transistor and its corresponding sub-thin-film transistor are arranged in the vertical direction, the first alignment mark, the second alignment mark and the plurality of third alignment marks are located on at least one side of the peripheral area in the vertical direction, and the plurality of third alignment marks are spaced apart horizontally.

7. The method for manufacturing an array substrate according to claim 5 or 6, characterized in that the manufacturing method further includes: when forming the gate and the first alignment mark, a plurality of scan lines located in the functional area are further formed on the substrate. The plurality of scan lines extend in the horizontal direction and are parallel and spaced apart in the vertical direction; when forming the source-drain layer and the third alignment mark, a plurality of data lines located in the functional area are further formed on the gate insulating layer. The plurality of data lines extend in the vertical direction and are parallel and spaced apart in the horizontal direction, and each data line intersects with the plurality of scan lines; wherein, the plurality of scan lines and the plurality of data lines intersect to define a plurality of pixel areas distributed in an array. The functional area includes the plurality of pixel areas. Each row of pixel areas corresponds to one scan line, each column of pixel areas corresponds to one data line, a transistor group is formed in each pixel area, and the gate in each pixel area is connected to the corresponding scan line, and the source of the source-drain layer in each pixel area is connected to the corresponding data line.

8. The method for manufacturing an array substrate according to claim 7, characterized in that the manufacturing method further includes: when forming the gate and the first alignment mark, a plurality of common electrode lines located in the functional area are further formed on the substrate. One common electrode line is provided on each side of the scan line corresponding to each pixel area; each transistor group further includes a voltage-dividing thin-film transistor. When different third alignment marks are aligned with the second alignment mark, the area of the projection of the channel region of the voltage-dividing thin-film transistor on the active layer remains unchanged; wherein, the source of the voltage-dividing thin-film transistor is connected to the drain of the sub-thin-film transistor, and the two ends of the drain of the voltage-dividing thin-film transistor are respectively connected to the two common electrode lines on the opposite sides of the scan line corresponding to the pixel area where the voltage-dividing thin-film transistor is located.

9. An array substrate, characterized in that The array substrate is fabricated by using the fabrication method of the array substrate according to any one of claims 1 to 8.

10. A display panel, characterized in that it includes a color filter substrate, a liquid crystal layer, and the array substrate according to claim 9, the color filter substrate and the array substrate are disposed opposite to each other, and the liquid crystal layer is disposed between the color filter substrate and the array substrate.

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