Semiconductor package and method of manufacturing the same
By employing a level insulating layer structure in semiconductor packaging, the problem of incomplete conductive trace structure is solved, resulting in stronger conductive traces and more stable semiconductor packaging, simplifying the manufacturing process and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MEDIATEK INC
- Filing Date
- 2022-03-04
- Publication Date
- 2026-07-07
AI Technical Summary
In traditional semiconductor packaging, the structure of conductive traces is incomplete, resulting in reduced strength and affecting the stability and transmission speed of electrical connections.
By forming first and second insulating layers with the same horizontal plane on the substrate, and forming conductive traces thereon, an uneven structure is avoided, and the strength and stability of the conductive traces are enhanced.
It improves the flatness and structural stability of conductive traces, enhances the electrical performance of semiconductor packages, simplifies the manufacturing process, reduces costs, and decreases package size and weight.
Smart Images
Figure CN115206924B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor package and its manufacturing method. Background Technology
[0002] Traditional semiconductor packaging includes conductive vias, conductive traces, and a substrate containing conductive components, where the conductive vias electrically connect the conductive traces and the conductive components. The conductive traces typically conform to the shape of the vias beneath them to form recesses. However, these recesses can lead to reduced strength or structural incompleteness. Therefore, achieving a complete structure for the conductive traces has become a prominent task in the industry.
[0003] Therefore, figuring out how to connect to semiconductor devices to improve transmission speed has become a prominent task in the industry. Summary of the Invention
[0004] In view of this, the present invention provides a semiconductor package and a method for manufacturing the same, in order to solve the above problems.
[0005] According to a first aspect of the present invention, a semiconductor package is disclosed, comprising:
[0006] substrate;
[0007] A first insulating layer is formed on the substrate and has a first through-hole;
[0008] A conductive pad is formed on the substrate through the first through-hole;
[0009] A second insulating layer has a first surface and a second through-hole, wherein the second through-hole extends from the first surface to the conductive pad; and
[0010] A conductive trace having a second surface and connected to the conductive pad through the second through-hole;
[0011] The entire first surface is on the same horizontal plane, and the entire second surface is on the same horizontal plane.
[0012] According to a second aspect of the present invention, a method for manufacturing a semiconductor package is disclosed, comprising:
[0013] Provide substrate;
[0014] A first insulating layer is formed on the substrate, wherein the first insulating layer has a first through-hole;
[0015] A conductive pad is formed on the substrate through the first through-hole;
[0016] A second insulating layer is formed having a first surface and a second through-hole, wherein the second through-hole extends from the first surface to the conductive pad, and wherein the entire first surface is on the same horizontal plane; and
[0017] A conductive trace having a second surface and connected to the conductive pad through the second through-hole is formed, wherein the entire second surface is on the same horizontal plane.
[0018] The semiconductor package of the present invention includes: a substrate; a first insulating layer formed on the substrate and having a first through-hole; a conductive pad formed on the substrate through the first through-hole; a second insulating layer having a first surface and a second through-hole, wherein the second through-hole extends from the first surface to the conductive pad; and a conductive trace having a second surface and connected to the conductive pad through the second through-hole; wherein the entire first surface and the entire second surface are on the same horizontal plane. By setting the first surface of the second insulating layer to be on the same horizontal plane, the present invention allows the conductive trace formed directly above the second insulating layer to be smoother and flatter, thereby avoiding unevenness or incomplete structure of the conductive trace, increasing the strength and structural stability of the conductive trace and the semiconductor package structure, and ensuring the stability of the electrical performance of the semiconductor package. Attached Figure Description
[0019] Figure 1 A schematic diagram of a semiconductor package according to an embodiment of the present invention is shown.
[0020] Figure 2 A schematic diagram of a semiconductor package according to another embodiment of the present invention is shown.
[0021] Figure 3 This is a schematic diagram of a semiconductor package according to another embodiment of the present invention.
[0022] Figures 4A to 4F It shows Figure 1 The manufacturing process of semiconductor packaging. Detailed Implementation
[0023] In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form part of the invention, and which illustrate specific preferred embodiments in which the invention can be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice them, and it should be understood that other embodiments may be utilized, and mechanical, structural, and procedural changes may be made, without departing from the spirit and scope of the invention. Therefore, the following detailed description should not be construed as limiting, and the scope of the embodiments of the invention is defined only by the appended claims.
[0024] It will be understood that although the terms “first,” “second,” “third,” “primary,” “secondary,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the teachings of the inventive concept, the first or primary element, component, region, layer, or portion discussed below may be referred to as a second or secondary element, component, region, layer, or portion.
[0025] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “under,” “above,” and “above” may be used herein to describe the relationship of an element or feature to it. Another element or feature is shown in the figure. In addition to the orientation described in the figure, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly. Additionally, it will be understood that when a “layer” is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more intermediate layers.
[0026] The terms “about,” “roughly,” and “about” generally mean a range of ±20%, ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of a specified value. The specified values in this invention are approximate. Unless otherwise specified, the specified values include the meanings of “about,” “roughly,” and “about.” The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular terms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.
[0027] It will be understood that when an “element” or “layer” is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, connected to, coupled to, or adjacent to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element or layer, there are no intermediate elements or layers.
[0028] Note: (i) the same features will be represented by the same reference numerals throughout the figures and will not necessarily be described in detail in every figure in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear throughout the series or only in selected figures of the series.
[0029] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a semiconductor package 100 according to an embodiment of the present invention. The semiconductor package 100 includes a substrate 110, a first insulating layer 120, a second insulating layer 125, at least one conductive pad (or conductive solder pad) 130, at least one conductive trace 140, an encapsulation 150, and at least one contact 160. The semiconductor package 100 is, for example, a wafer-level chip-scale package (WLCSP).
[0030] A first insulating layer 120 is formed on a substrate 110 and has at least one first through-hole 120a. A conductive pad 130 is formed on the substrate 110 through the first through-hole 120a. A second insulating layer 125 has a first surface (or a first upper surface) 125u and at least one second through-hole 125a, wherein the second through-hole 125a extends from the first surface 125u to the conductive pad 130. A conductive trace 140 has a second surface (or a second upper surface) 140u and is connected to the conductive pad 130 through the second through-hole 125a. The entire first surface 125u is on the same horizontal plane (or the entire first surface 125u is a flat plane), and the entire second surface 140u is on the same horizontal plane (or the entire second surface 140u is a flat plane). In other words, the first surface 125u does not have a stepped surface (structure), and the second surface 140u does not have a stepped surface (structure). In this embodiment, the entire second surface 140u is on the same horizontal plane, meaning that there is no depression in the second surface 140u of the conductive trace 140, thus providing stronger or sufficient strength. In the prior art, a filling material such as molding compound is provided between the second insulating layer 125 and the conductive trace 140 to make the subsequently formed conductive trace 140 smoother. In this embodiment of the invention, no filling material such as molding compound is provided between the second insulating layer 125 and the conductive trace 140. By reducing the aperture of the connecting portion 141, the first surface 125u of the second insulating layer 125 has almost no depressions or unevenness, so the entire first surface 125u is on the same horizontal plane. This eliminates the need for filling materials such as molding compound between the second insulating layer 125 and the conductive trace 140, simplifying the process, reducing steps, and resulting in a thinner structure, saving costs and reducing the size and weight of the semiconductor package.
[0031] like Figure 1 As shown, the first surface 125u is, for example, a plane, and the second surface 140u is, for example, a plane. In one embodiment, the second surface 140u is a completely flat plane that is substantially without depressions, protrusions, or projections. The first surface 125u, except for the portion forming the second through-hole 125a, is also a flat plane that is substantially without depressions, protrusions, or projections.
[0032] like Figure 1 As shown, substrate 110 is, for example, a wafer. The conductive element 111 of substrate 110 may include, for example, at least one metal layer, at least one conductive trace, at least one conductive via, and / or at least one transistor electrically connected to the metal layer, conductive trace, and / or conductive via.
[0033] like Figure 1As shown, the first insulating layer 120 includes a first layer 121 and a second layer 122. The first layer 121 is formed on the substrate 110, and the second layer 122 is formed on the first layer 121. A first via 120a passes through the first layer 121 and the second layer 122. Furthermore, the first layer 121 is made of a material including, for example, silicon nitride (SiN), and the second layer 122 is made of a material including, for example, oxides. Furthermore, the width W1 of the first via 120a is greater than 5 micrometers (μm), or between 5 micrometers and 300 micrometers, or even greater than 300 micrometers, preferably between 5 micrometers and 300 micrometers to obtain a suitable width, wherein the width W1 is, for example, a width dimension or a diameter. In top view, the first via 120a can be circular, polygonal, elliptical, etc.
[0034] like Figure 1 As shown, a second insulating layer 125 covers the first insulating layer 120 and a portion of the conductive pad 130. The second insulating layer 125 includes a third layer 1251 and a fourth layer 1252. The third layer 1251 covers the first insulating layer 120 and a portion of the conductive pad 130, and the fourth layer 1252 is formed on the third layer 1251. A second through hole 125a penetrates the third layer 1251 and the fourth layer 125 to expose a portion of the conductive layer 125. Furthermore, the third layer 1251 has at least one first hole 1251a, and the fourth layer 1252 has at least one second hole 1252a, wherein the first hole 1251a and the second hole 1252a form a second through hole 125a to expose the conductive pad 130. The first hole 1251a and the second hole 1252a can be formed in the same manufacturing process, such as an etching process. In this embodiment, a plurality of second vias 125a extend from the first surface (or the first upper surface) 125u to the same (or the same) conductive pad 130. Furthermore, the third layer 1251 may be made of a material including, for example, oxides, and the fourth layer 1252 may be made of a material including, for example, silicon nitride (SiN).
[0035] like Figure 1As shown, the second via 125a has a width W2. The width W2 is between 2 μm and 12 μm, or even less than 2 μm or greater than 12 μm, where the width W2 is, for example, a dimension of width or diameter. The width W2 is sufficiently small, preferably less than or equal to 12 μm, thus preventing the formation / generation of depressions, voids, recesses, and / or cracks in the extension 142 above the connection 141. In this way, the conductive trace 140 has sufficient strength. Furthermore, viewed from above, the second via 125a can be circular, polygonal, elliptical, etc. By setting the first surface of the second insulating layer to the same horizontal plane, the conductive trace formed directly above the second insulating layer can be smoother and flatter, thereby avoiding unevenness (e.g., grooves) or structural incompleteness of the conductive trace, thus increasing the strength and structural stability of the conductive trace and the semiconductor package structure, and ensuring the stability of the electrical performance of the semiconductor package. Meanwhile, in this invention, the pitch (or width W2) of the second through hole 125a (and the connecting portion 141) is set to be sufficiently small (e.g., less than or equal to 12 μm), thereby further avoiding unevenness and other defects on the upper surface of the conductive trace, and enhancing the strength and stability of the conductive trace 140.
[0036] like Figure 1As shown, the first surface 125u is the upper surface of the fourth layer 1252, and the third layer 1251 has a third surface (or third upper surface) 1251u, wherein the third surface 1251u is at the same horizontal plane. In another embodiment, the third surface 1251u is, for example, a polished surface formed by a process such as CMP (Chemical-Mechanical Planarization). In this embodiment, the third layer 1251 can be, for example, an oxide layer, such as silicon oxide, and the fourth layer 1252 can be a nitride layer, such as silicon nitride. In this embodiment, the second insulating layer 125 can be a single-layer structure, such as consisting only of an oxide layer; or it can be a multi-layer structure, such as consisting of an oxide layer and a nitride layer, such that the oxide layer exerts less stress on the underlying layer while the nitride layer can prevent moisture (water vapor) from entering the semiconductor package. When the second insulating layer 125 is a single-layer structure, such as the third layer 1251 consisting only of an oxide layer, the upper surface of the third layer 1251 (i.e., the third surface 1251u) is at the same horizontal plane. Therefore, except for the area where the second through-hole 125a (the first hole 1251a) is formed, the remaining portion of the third surface 1251u is a flat plane with essentially no depressions, protrusions, or projections. When the second insulating layer 125 has a multilayer structure, such as including a third layer 1251 and a fourth layer 1252, the third surface 1251u of the third layer 1251 is on the same horizontal plane. Therefore, the upper surface of the fourth layer 1252 (i.e., the first surface 125u) formed on the third surface 1251u is also on the same horizontal plane. Similarly, when the second insulating layer 125 includes more layers, such as three or more layers, since the upper surface of the third layer 1251 (i.e., the third surface 1251u) is on the same horizontal plane, the upper surfaces of the other layers and the final first surface 125u are also on the same horizontal plane.
[0037] like Figure 1 As shown, each conductive pad 130 includes a conductive via 131 and a protrusion layer 132. The conductive via 131 is formed directly on the conductive element 111 of the substrate 110 through a first via 120a. In other words, there is no physical material (e.g., direct contact) between the conductive element 111 and the conductive via 131. Furthermore, at least a portion of the conductive via 131 may be formed within the first via 120a. The conductive via 131 has an upper surface 131u that protrudes relative to the upper surface 120u of the first insulating layer 120. In another embodiment, the upper surface 131u may be recessed relative to the upper surface 120u of the first insulating layer 120, or flush with the upper surface 120u of the first insulating layer 120.
[0038] like Figure 1As shown, the conductive via 131 fills the first via 120a and can accommodate or support multiple connecting portions 141, such as four connecting portions 141. The conductive via 131 has a width Wl formed within the first via 120a. Furthermore, viewed from the top, the conductive via 131 can be circular, polygonal, elliptical, etc.
[0039] like Figure 1 As shown, the protruding layer 132 is connected to the conductive via 131. The protruding layer 132 protrudes from the upper surface 131u of the conductive via 131 and extends beyond the side surface 131s of the conductive via 131.
[0040] In one embodiment, the conductive via 131 and the protruding layer 132 can be formed in the same manufacturing process, such as a sputtering process. In this way, the conductive via 131 and the protruding layer 132 can form an integral structure. Furthermore, due to sputtering, the protruding layer 132 has curved sides 132s connecting to the upper surface 131u of the conductive via 131. Additionally, the protruding layer 132 has an opening 132a exposing the conductive via 131, through which the conductive trace 140 connects to the conductive via 131. In terms of material, the conductive via 131 and the protruding layer 132 can, for example, include aluminum, copper, or combinations thereof. Furthermore, viewed from above, the protruding layer 132 can be a closed loop or an open loop, exposing the upper surface 131u of the conductive via 131. The protruding layer 132 helps the side surface 131s of the conductive via 131 to be in close and direct contact with the inner wall of the first via 120a when the conductive via 130 is formed (the two are tightly fitted without gaps), thus making the structure of the conductive via 130 more stable and the structure of the semiconductor package stronger.
[0041] like Figure 1 As shown, at least one conductive trace 140 is, for example, at least one part of a redistribution layer (RDL). The conductive trace 140 includes at least one connecting portion 141 and an extension 142 connected to the at least one connecting portion 141, wherein each connecting portion 141 fills a corresponding second via 125a to connect to a conductive via 131. The conductive trace 140 and the conductive via 131 overlap vertically. Furthermore, the entire connecting portion 141, a portion of the extension 142, and the conductive via 131 overlap vertically. Additionally, the first via 120a, the connecting portion 141, and the conductive via 131 overlap vertically. In terms of materials, the conductive trace 140 can be made of materials including, for example, aluminum, copper, or combinations thereof.
[0042] like Figure 1As shown, the connecting portion 141 that fills the second through hole 125a has a width W2. The width W2 of the connecting portion 141 is smaller than the width W1 of the conductive through hole 131 formed in the first through hole 120a.
[0043] like Figure 1 As shown, the conductive trace 140 is directly connected to the conductive pad 130 located directly above the first through-hole 120a. For example, the connection portion 141 of the conductive trace 140 is located directly above the first through-hole 120a. In this way, the conductive path P1 between the conductive element 111, the conductive trace 140, and the conductive through-hole 130 is shorter or minimized (e.g., vertical distance), thereby reducing parasitic resistance.
[0044] like Figure 1 As shown, there is no solid layer or physical layer between the conductive trace 140 and the second insulating layer 125. For example, there is no molding compound between the conductive trace 140 and the second insulating layer 125, and the conductive trace 140 and the second insulating layer 125 are in direct contact. Therefore, the manufacturing process of this embodiment is simpler, with fewer steps, and the structure is thinner, saving costs and reducing the size and weight of the semiconductor package. The conductive trace 140 and the second insulating layer 125 are in direct contact, for example, the lower surface of the extension portion 142 of the conductive trace 140 is in direct contact with the upper surface 125u of the second insulating layer 125. In other words, in this embodiment, no molding compound covers the conductive pad 130 and the second insulating layer 125. The molding compound is, for example, polybenzoxazole (PBO). Compared to the second via 125a formed on the molding compound, the width W2 of the second via 125a formed on the second insulating layer 125 in this embodiment can be smaller.
[0045] Package 150 covers conductive trace 140. Package 150 has at least one opening 150a exposing an extension 142 of conductive trace 140. Package 150 may be made of materials including, for example, PBO (polybenzoxazole) or molding compound materials. Each contact 160 is physically or electrically connected to conductive trace 140 through a corresponding opening 150a. In one embodiment, contact 160 is, for example, a solder ball, conductive post, etc.
[0046] Please refer to Figure 2 , Figure 2 This is a schematic diagram of a semiconductor package 200 according to another embodiment of the present invention. The semiconductor package 200 includes a substrate 110, a first insulating layer 220, a second insulating layer 225, at least one conductive pad 230, at least one conductive trace 240, a package 150, and at least one contact 160.
[0047] Semiconductor package 200 includes features similar to or the same as those of semiconductor package 100, except that the conductive pad 230 of semiconductor package 200 accommodates or carries a connection portion 141, that is, a connection portion 141 is connected to a conductive pad 230. Figure 2 This embodiment can be used in applications with low current (e.g., signal transmission). Figure 1 The embodiments can be used in applications with large current (e.g., transmitting power supply voltage), and the number of connection parts 141 can also be freely designed as needed in the embodiments of the present invention.
[0048] like Figure 2 As shown, in this embodiment, the first insulating layer 220 has at least one first through-hole 220a. The width W2 of the second through-hole 125a is smaller than the width W1' of the first through-hole 220a. In this embodiment, the width W1' of the first through-hole 220a is smaller than the width W1 of the first through-hole 120a of the semiconductor package 100. The width W1' of the first through-hole 220a is greater than 5 μm, or between 5 μm and 300 μm, or even greater than 300 μm. The conductive via 131 within the first through-hole 220a can accommodate or carry a connection portion 141.
[0049] like Figure 2 As shown, the second insulating layer 225 has at least one second through-hole 125a extending from the first surface 125u of the second insulating layer 225 to the conductive pad 230. The connecting portion 141 fills the corresponding second through-hole 125a to connect the conductive through-hole 131 of the conductive pad 230.
[0050] Please refer to Figure 3 , Figure 3 This is a schematic diagram of a semiconductor package 300 according to another embodiment of the present invention. The semiconductor package 300 includes a substrate 110, a first insulating layer 220, a second insulating layer 225, at least one conductive pad 230, at least one conductive trace 240, a package body 150, and at least one contact 160.
[0051] Semiconductor package 300 includes features similar to or identical to those of semiconductor package 200, except that the plurality of conductive pads 230 of semiconductor package 300 are arranged adjacently. Furthermore, as... Figure 3 As shown, the substrate 110 includes a plurality of conductive elements 111, which are electrically connected to a plurality of conductive traces 240.
[0052] In addition, such as Figure 3 As shown, multiple conductive pads 230 are arranged adjacent to each other in the semiconductor package 300 within the same width Wl, and as... Figure 1As shown, only one conductive pad 230 is disposed in the semiconductor package 200. In other words, the semiconductor package 300 can provide more I / O ports and / or voltage levels within the same width W1.
[0053] Figures 4A to 4F It shows Figure 1 The manufacturing process of semiconductor packaging 100.
[0054] like Figure 4A As shown, a substrate 110 is provided, wherein the substrate 110 is, for example, a chip. The substrate 110 includes at least one conductive element 111, at least one metal layer (not shown), at least one conductive trace (not shown), at least one conductive via (not shown), and / or at least one transistor (not shown) electrically connected to the metal layer, conductive trace, and / or conductive via.
[0055] like Figure 4A As shown, a first insulating layer 120, including a first layer 121 and a second layer 122, is formed on a substrate 110 by methods such as coating or application. The first insulating layer 120 has at least one first through-hole 120a exposing a corresponding conductive element 111. The first through-hole 120a is formed, for example, by etching.
[0056] like Figure 4A As shown, at least one conductive via 131 and at least one protruding layer 132 are formed within a corresponding first via 120a. The at least one protruding layer 132 and the at least one conductive via 131 form at least one conductive pad 130. In this embodiment, the conductive via 131 and the protruding layer 132 can be formed in the same process, such as a sputtering process, and thus the conductive via 131 and the protruding layer 132 can form an integral structure. Due to the sputtering process, the protruding layer 132 forms a curved side surface 132s that connects to the upper surface 131u of the conductive via 131. Furthermore, the protruding layer 132 has an opening 132a exposing the conductive via 131, and the conductive trace 140 connects to the conductive via 131 through the opening 132a. In terms of material, the conductive via 131 and the protruding layer 132 may, for example, include aluminum, copper, or combinations thereof. Furthermore, viewed from above, the protruding layer 132 may be a closed loop or an open loop, exposing the upper surface 131u of the conductive via 131. The protruding layer 132 is connected to the conductive via 131 and protrudes relative to the upper surface. The surface 131u of the conductive via 131 extends beyond the side surface 131s of the conductive via 131.
[0057] like Figure 4B As shown, the third layer material 1251' covering the conductive pad 130 and the first insulating layer 120 is formed, for example, by coating, plating or the like.
[0058] like Figure 4BAs shown, the third layer material 1251' is planarized to form a third surface 1251u of the third layer material 1251', which is formed by, for example, CMP. The third surface 1251u is, for example, a planar surface. Furthermore, the third layer material 1251' may be made of a material including, for example, oxides.
[0059] like Figure 4C As shown, the fourth layer material 1252' covering the third layer material 1251' is formed by means of, for example, coating, application, etc. The fourth layer material 1252' and the third layer material 1251' form the second insulating layer material 125'. Furthermore, the fourth layer material 1252' can be made of, for example, a material including silicon nitride (SiN).
[0060] like Figure 4D As shown, at least one second through-hole 125a penetrates the third layer material 1251' and the fourth layer material 1252' to form a second insulating layer 125 and expose a portion of the conductive pad 130. Furthermore, the third layer 1251 has at least one first through-hole 1251a, and the fourth layer 1252 has at least one second through-hole 1252a, wherein the first through-hole 1251a and the second through-hole 1252a form the second through-hole 125a. The first through-hole 1251a and the second through-hole 1252a can be formed in the same manufacturing process, such as an etching process. In this embodiment, a plurality of second through-holes 125a extend from the first surface 125u to the same (or the same) conductive pad 130.
[0061] like Figure 4E As shown, at least one conductive trace 140 covers the second insulating layer 125, and is formed on the package 150, for example, by sputtering, electroplating, or other methods. The conductive trace 140 includes at least one connecting portion 141 and an extension portion 142, the extension portion 142 being connected to at least one connecting portion 141, wherein each connecting portion 141 fills a corresponding second through-hole 125a to connect with a conductive through-hole 131. The conductive trace 140 and the conductive through-hole 131 overlap vertically. Furthermore, the entire connecting portion 141, a portion of the extension portion 142, and the conductive through-hole 131 overlap vertically. Additionally, the first through-hole 120a, the connecting portion 141, and the conductive through-hole 131 overlap vertically. In terms of materials, the conductive trace 140 can be made of materials including, for example, aluminum, copper, or combinations thereof.
[0062] like Figure 4F As shown, the package 150 covering the conductive trace 140 is formed, for example, by coating or plating. The package 150 has at least one opening 150a that exposes the extension 142 of the conductive trace 140. The material of the package 150 may be, for example, PBO (Polybenzoxazole) or molding compound.
[0063] Then, at least one physical connection or electrical connection is formed through the corresponding opening 150a to the contact 160 of the conductive trace 140, such as Figure 1 As shown. In one embodiment, contact 160 is, for example, a solder ball, a conductive post, etc.
[0064] Those skilled in the art will readily observe that numerous modifications and alterations can be made to the apparatus and method while maintaining the teachings of this invention. Therefore, the foregoing disclosure should be interpreted as being limited only by the scope and limits of the appended claims.
Claims
1. A semiconductor package, characterized in that, include: substrate; A first insulating layer is formed on the substrate and has a first through-hole; A conductive pad is formed on the substrate through the first through-hole; The second insulating layer has a first surface and a second through-hole, wherein the second through-hole extends from the first surface to the conductive pad; as well as A conductive trace having a second surface and connected to the conductive pad through the second through-hole; The entire first surface is on the same horizontal plane, and the entire second surface is on the same horizontal plane; The conductive pad includes a conductive through-hole and a protruding layer. The conductive through-hole is formed in the first through-hole, and the protruding layer is connected to the conductive through-hole and extends beyond the side of the conductive through-hole. The conductive trace includes a connecting portion and an extension portion connected to the connecting portion. The connecting portion is formed in the second through-hole, and the connecting portion is located directly above the first through-hole. The entire connecting portion overlaps vertically with the conductive through-hole.
2. The semiconductor package as described in claim 1, characterized in that, The second insulating layer has a plurality of second through holes extending from the first surface to the conductive pad.
3. The semiconductor package as described in claim 1, characterized in that, There is no physical layer between the conductive trace and the second insulating layer.
4. The semiconductor package as claimed in claim 1, characterized in that, The conductive pad and the second insulating layer are not covered with molding compound.
5. The semiconductor package as described in claim 1, characterized in that, The second insulating layer comprises multiple layers, one of which has a third surface, and the third surface is located on the same horizontal plane.
6. The semiconductor package as described in claim 1, characterized in that, The width of the first through-hole is greater than 5 micrometers.
7. The semiconductor package as described in claim 1, characterized in that, The width of the second through-hole is between 2 micrometers and 12 micrometers.
8. The semiconductor package as described in claim 1, characterized in that, The conductive trace is directly connected to the conductive pad located directly above the first through hole.
9. The semiconductor package as claimed in claim 1, characterized in that, The conductive trace includes a connecting portion and an extension portion connecting the connecting portion. The connecting portion is directly connected to the conductive pad, and the connecting portion overlaps the conductive pad vertically.
10. The semiconductor package as claimed in claim 9, characterized in that, The protruding layer protrudes relative to the upper surface of the conductive via; The conductive trace is directly connected to the conductive via.
11. A method for manufacturing a semiconductor package, characterized in that, include: Provide substrate; A first insulating layer is formed on the substrate, wherein the first insulating layer has a first through-hole; A conductive pad is formed on the substrate through the first through hole, wherein the conductive pad includes a conductive through hole and a protruding layer. The conductive through hole is formed in the first through hole, and the protruding layer is connected to the conductive through hole and extends beyond the side of the conductive through hole. A second insulating layer is formed having a first surface and a second through-hole, wherein the second through-hole extends from the first surface to the conductive pad, and wherein the entire first surface is on the same horizontal plane; as well as A conductive trace having a second surface and connected to the conductive pad through the second through hole is formed, wherein the entire second surface is on the same horizontal plane, the conductive trace includes a connecting portion and an extension connected to the connecting portion, the connecting portion is formed in the second through hole, the connecting portion is located directly above the first through hole, and the entire connecting portion overlaps vertically with the conductive through hole.
12. The manufacturing method as described in claim 11, characterized in that, The steps for forming the second insulating layer include: Forming a third layer covering the conductive pad and the first insulating layer; and The third layer is planarized to form a third surface of the third layer, wherein the third surface is a planar surface.
13. The manufacturing method as described in claim 12, characterized in that, After the step of planarizing the third layer, the manufacturing method further includes: A fourth layer is formed to cover the third layer; and A second through-hole is formed to pass through the third and fourth layers to expose part of the conductive pad.