Semiconductor structure and method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure and a semiconductor structure, the method comprising: providing a substrate; forming an initial bottom electrode material layer on the substrate; performing a nitrogen-containing surface treatment on the surface of the initial bottom electrode material layer to form a bottom electrode material layer and a passivation material layer located on the bottom electrode material layer; forming a dielectric structure material layer on the passivation material layer; and forming a top electrode material layer on the dielectric structure material layer. The semiconductor structure formed by the method has improved performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] In the field of semiconductor integrated circuit manufacturing technology, with the development of semiconductor technology, the requirements for the performance of semiconductor devices are getting higher and higher. Capacitors are important components in integrated circuits and are widely used in memory, microwave, radio frequency, smart cards, high voltage and filtering chips. Specific uses include bandpass filters, phase-locked loops, dynamic random access memories, etc. With the development of semiconductor technology, it is hoped that capacitors in integrated circuits have the characteristics of high capacitance density, low leakage and low voltage linearity, which has also become a challenge in the production of capacitors in integrated circuits.

[0003] There are many different capacitor structures in integrated circuit chips, such as MOS field effect transistor capacitors, PIP (poly-insulator-poly) capacitors, variable junction capacitors, and metal-insulator-metal (MIM) capacitors and metal-oxide-metal (MOM) capacitors in the back-end interconnection. The capacitor structure in the back-end interconnection layer does not occupy the area of ​​the device layer, and the linear characteristics of the capacitor are much better than other types of capacitors.

[0004] However, the performance of currently common back-end capacitor structures such as MIM capacitors and MOM capacitors still needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of the back-end capacitor.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming an initial bottom electrode material layer on the substrate; performing a nitrogen-containing surface treatment on the surface of the initial bottom electrode material layer to form a bottom electrode material layer and a passivation material layer located on the bottom electrode material layer; forming a dielectric structure material layer on the passivation material layer; and forming a top electrode material layer on the dielectric structure material layer.

[0007] Optionally, the process of performing nitrogen-containing surface treatment on the surface of the initial bottom electrode material layer includes: a nitrogen-containing plasma treatment process; and the gas of the nitrogen-containing plasma treatment process includes ammonia.

[0008] Optionally, the material of the passivation material layer includes a bottom electrode material layer material containing nitrogen.

[0009] Optionally, the material of the bottom electrode material layer includes metal or metal nitride, the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum, and the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0010] Optionally, the material of the passivation material layer includes nitrogen-rich titanium nitride.

[0011] Optionally, before performing nitrogen-containing surface treatment on the surface of the initial bottom electrode material layer, the method further includes: performing a planarization treatment on the initial bottom electrode material layer to form a transition bottom electrode material layer.

[0012] Optionally, the process for planarizing the initial bottom electrode material layer includes a chemical mechanical polishing process; the parameters of the chemical mechanical polishing process include: the polishing liquid is an acidic solution, and the pH value of the acidic solution ranges from 5 to 9; the grinding rate is 3 angstroms per second to 5 angstroms per second; and the grinding time is 6 seconds to 10 seconds.

[0013] Optionally, the thickness of the bottom electrode material layer ranges from 350 angstroms to 450 angstroms.

[0014] Optionally, the thickness of the passivation material layer ranges from 2 angstroms to 3 angstroms.

[0015] Optionally, after forming the top electrode material layer, it also includes: etching the top electrode material layer, the dielectric structure material layer and the bottom electrode material layer to form a capacitor structure on the substrate, the capacitor structure includes a bottom electrode layer, a passivation layer located on the bottom electrode layer, a dielectric structure located on the passivation layer, and a top electrode layer located on the dielectric structure, the dielectric structure and the top electrode layer expose a portion of the surface of the bottom electrode layer.

[0016] Optionally, after forming the capacitor structure, the method further includes: forming a dielectric layer and a conductive structure located in the dielectric layer on the substrate, wherein the conductive structure is electrically connected to the bottom electrode layer, and the capacitor structure is located in the dielectric layer.

[0017] Optionally, the method for forming the capacitor structure includes: forming a first mask structure on the top electrode material layer, the first mask structure exposing a portion of the surface of the top electrode material layer; etching the top electrode material layer and the dielectric structure material layer using the first mask structure as a mask until the surface of the passivation material layer is exposed, thereby forming a dielectric structure and a top electrode layer located on the dielectric structure; forming a second mask structure on the passivation material layer, the dielectric structure and the top electrode layer, the second mask structure exposing a portion of the surface of the passivation material layer on the bottom electrode material layer; etching the passivation material layer and the bottom electrode material layer using the second mask structure as a mask until the surface of the substrate is exposed, thereby forming the bottom electrode layer and the passivation layer located on the bottom electrode layer.

[0018] Optionally, the method for forming the conductive structure includes: forming an opening in the dielectric layer, the opening exposing the surface of the passivation layer on the bottom electrode layer; forming a conductive structure in the opening, the conductive structure being located on the passivation layer and electrically connected to the bottom electrode layer.

[0019] Optionally, the conductive structure includes a barrier layer located on the sidewall surface and the bottom surface of the opening and a conductive layer located on the barrier layer.

[0020] Optionally, the material of the barrier layer includes metal nitride, and the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride; the material of the conductive layer includes metal, and the metal includes a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum.

[0021] Optionally, the dielectric structure includes several dielectric layers; the several layers include a single layer, a double layer or a triple layer.

[0022] Optionally, the dielectric structure includes three layers; the dielectric structure includes: a first dielectric layer, a second dielectric layer located on the first dielectric layer, and a third dielectric layer located on the second dielectric layer.

[0023] Optionally, the material of the top electrode material layer includes metal or metal nitride, the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum, and the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0024] Optionally, the substrate includes: a base; a device layer located on the base, the device layer includes an isolation structure and a device structure located within the isolation structure, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure.

[0025] Correspondingly, the technical solution of the present invention also provides a semiconductor structure, including: a substrate; a capacitor structure located on the substrate, the capacitor structure including a bottom electrode layer, a passivation layer located on the bottom electrode layer, a dielectric structure located on the passivation layer, and a top electrode layer located on the dielectric structure, the dielectric structure and the top electrode layer expose a portion of the surface of the passivation layer.

[0026] Optionally, it also includes: a dielectric layer located on the substrate and a conductive structure located in the dielectric layer, wherein the conductive structure is located on the passivation layer, the conductive structure is electrically connected to the bottom electrode layer, and the capacitor structure is located in the dielectric layer.

[0027] Optionally, the conductive structure is in contact with the passivation layer.

[0028] Optionally, the material of the passivation layer includes a nitrogen-containing bottom electrode layer material, and the nitrogen-containing bottom electrode layer material is a material obtained by nitrogen-containing plasma treatment.

[0029] Optionally, the material of the bottom electrode layer includes metal or metal nitride, the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum, and the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0030] Optionally, the material of the passivation layer includes nitrogen-rich titanium nitride.

[0031] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0032] The technical solution of the present invention forms a bottom electrode material layer and a passivation material layer located on the bottom electrode material layer by performing a nitrogen-containing surface treatment on the surface of the initial bottom electrode material layer. The nitrogen-containing surface treatment can reduce the natural oxide layer on the initial bottom material layer and fill the oxygen vacancy defects on the initial bottom material layer caused by environmental factors, so that the formed passivation material layer is chemically stable. After the capacitor structure is subsequently formed, when the device is working, it is not easy to leak or even be broken down at the defects on the surface of the bottom electrode material layer, thereby improving the reliability of the semiconductor structure.

[0033] Furthermore, the method for passivating the surface of the initial bottom electrode material layer includes a plasma containing ammonia gas, and the nitrogen ions in the plasma containing ammonia gas can reduce the natural oxide layer on the initial bottom material layer and fill the oxygen vacancy defects on the initial bottom material layer caused by environmental factors, so that the formed passivation material layer is chemically stable. When the device is working subsequently, it is not easy to leak or even be broken down at the defects on the surface of the bottom electrode material layer, thereby improving the reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 and Figure 2 is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment;

[0035] Figures 3 to 8 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0036] As described in the background art, the performance of existing back-end capacitor structures such as MIM capacitors and MOM capacitors still needs to be improved.

[0037] Figure 1 and Figure 2It is a schematic cross-sectional structure diagram of a semiconductor structure forming process in one embodiment.

[0038] Please refer to Figure 1 , providing a substrate 100; forming a first dielectric layer 101 on the substrate 100; forming a bottom electrode material layer 102 on the first dielectric layer 101; forming a dielectric structure material layer 103 on the bottom electrode material layer 102; and forming a top electrode material layer 104 on the dielectric structure material layer 103.

[0039] Please refer to Figure 2 , forming a first mask structure (not shown) on the top electrode material layer 104, wherein the first mask structure exposes a portion of the surface of the top electrode material layer 104; etching the top electrode material layer 104 and the dielectric structure material layer 103 using the first mask structure as a mask until the surface of the bottom electrode material layer 102 is exposed, thereby forming a dielectric structure 105 and a top electrode layer 106 located on the dielectric structure 105; forming a second mask structure (not shown) on the bottom electrode material layer 102, the dielectric structure 105 and the top electrode layer 106, wherein the second mask structure (not shown) is formed on the bottom electrode material layer 102, the dielectric structure 105 and the top electrode layer 106. The second mask structure exposes part of the surface of the bottom electrode material layer 102; the bottom electrode material layer 102 is etched using the second mask structure as a mask until the surface of the first dielectric layer 101 is exposed to form the bottom electrode layer 107; a second dielectric layer 108 is formed on the first dielectric layer 101, and the top electrode layer 106, the dielectric structure 105 and the bottom electrode layer 107 are located in the second dielectric layer 108; a conductive structure 109 is formed in the second dielectric layer 108, and the conductive structure 109 is electrically connected to the bottom electrode layer 107.

[0040] During the formation of the semiconductor structure, after the bottom electrode material layer 102 is formed, it needs to be transferred to other cavities to form a dielectric structure material layer 103. During the transfer process, the surface of the bottom electrode material layer 102 is exposed to the air and is easily oxidized by the air, thereby forming defects such as a natural oxide layer and oxygen vacancies on the surface of the bottom electrode material layer 102. When the bottom electrode layer 107 is subsequently pressurized by the conductive structure 109, leakage or even breakdown is likely to occur at the defects on the surface of the bottom electrode layer 107, thereby affecting the reliability of the semiconductor structure.

[0041] In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming a semiconductor structure, by performing a nitrogen-containing surface treatment on the surface of the initial bottom electrode material layer to form a bottom electrode material layer and a passivation material layer located on the bottom electrode material layer, the nitrogen-containing surface treatment can reduce the natural oxide layer on the initial bottom material layer, and fill the oxygen vacancy defects on the initial bottom material layer caused by environmental factors, so that the formed passivation material layer is chemically stable, and after the capacitor structure is subsequently formed, when the device is working, it is not easy to leak or even be broken down at the defects on the surface of the bottom electrode material layer, thereby improving the reliability of the semiconductor structure.

[0042] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Figures 3 to 8 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0044] Please refer to Figure 3 , providing a substrate.

[0045] The substrate includes: a base 200; a device layer 201 located on the base 200, the device layer 201 includes an isolation structure (not shown) and a device structure (not shown) located within the isolation structure, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure.

[0046] In this embodiment, the material of the substrate 200 is silicon.

[0047] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0048] The material of the isolation structure includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0049] Please continue to refer to Figure 3 , an initial bottom electrode material layer 202 is formed on the substrate.

[0050] The initial bottom electrode material layer 202 is used for subsequently forming a bottom electrode layer.

[0051] The material of the initial bottom electrode material layer 202 includes metal or metal nitride, the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum, and the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0052] In this embodiment, the material of the initial bottom electrode material layer 202 includes titanium nitride. The titanium nitride material has a high melting point, so the titanium nitride material has better performance under high temperature conditions; at the same time, the titanium nitride material has relatively good chemical stability compared to pure metal.

[0053] The process of forming the initial bottom electrode material layer 202 includes a chemical vapor deposition process or an atomic layer deposition process. In the present embodiment, the process of forming the initial bottom electrode material layer 202 includes a chemical vapor deposition process, and the chemical vapor deposition process makes the surface of the formed initial bottom electrode material layer 202 relatively rough, which may affect the contact between the subsequently formed dielectric structure and the bottom electrode layer.

[0054] After the initial bottom electrode material layer 202 is formed, the material needs to be transferred to form a dielectric structure material layer on the bottom electrode material layer 202. During the material transfer process, the initial bottom electrode material layer 202 is exposed to the air and is affected by the environment. It is easily oxidized by the air, thereby forming defects such as a natural oxide layer and oxygen vacancies on the surface of the initial bottom electrode material layer 202.

[0055] Please refer to Figure 4 , the initial bottom electrode material layer 202 is planarized to form a transition bottom electrode material layer 203 .

[0056] The initial bottom electrode material layer 202 is planarized to improve the surface flatness of the transition bottom electrode material layer 203 , so that the subsequently formed dielectric structure has good contact with the bottom electrode layer.

[0057] In this embodiment, the process for planarizing the initial bottom electrode material layer 202 includes a chemical mechanical polishing process; the parameters of the chemical mechanical polishing process include: the polishing liquid is an acidic solution, and the pH value of the acidic solution ranges from 5 to 9; the grinding rate is 3 angstroms per second to 5 angstroms per second; and the grinding time is 6 seconds to 10 seconds.

[0058] The grinding rate of the chemical mechanical polishing process is 3 angstroms per second to 5 angstroms per second. If the grinding rate is too fast, the chemical mechanical polishing process will easily grind away the thicker initial bottom electrode material layer 202, making the formed transition bottom electrode material layer 203 thinner. At the same time, the faster grinding rate makes the surface flatness of the obtained transition bottom electrode material layer 203 poor, and the fine grinding effect cannot be achieved; if the grinding rate is too slow, the production efficiency is slow.

[0059] The grinding time of the chemical mechanical polishing process is 6 seconds to 10 seconds. If the grinding time is too long, the chemical mechanical polishing process will easily grind away the thicker initial bottom electrode material layer 202, making the formed transition bottom electrode material layer 203 thinner. At the same time, the longer grinding time makes the surface flatness of the obtained transition bottom electrode material layer 203 poor, and the effect of fine grinding cannot be achieved; if the grinding time is too short, the flattening effect cannot be achieved.

[0060] In other embodiments, the initial bottom electrode material layer may not be planarized.

[0061] After the planarization treatment, the material needs to be transferred to form a dielectric structure material layer on the transition bottom electrode material layer 203. During the material transfer process, the transition bottom electrode material layer 203 is exposed to the air and is affected by the environment. It is easily oxidized by the air, thereby forming defects such as a natural oxide layer and oxygen vacancies on the surface of the transition bottom electrode material layer 203.

[0062] Please refer to Figure 5 , a nitrogen-containing surface treatment is performed on the surface of the transition bottom electrode material layer 203 to form a bottom electrode material layer 204 and a passivation material layer 205 located on the bottom electrode material layer 204 .

[0063] By performing a nitrogen-containing surface treatment on the surface of the transition bottom electrode material layer 203, a bottom electrode material layer 204 and a passivation material layer 205 located on the bottom electrode material layer 204 are formed. The nitrogen-containing surface treatment can reduce the natural oxide layer on the transition bottom electrode material layer 203 and fill the oxygen vacancy defects on the transition bottom electrode material layer 203 caused by environmental factors, so that the formed passivation material layer 205 is chemically stable. After the capacitor structure is subsequently formed, when the device is working, it is not easy to leak or even be broken down at the defects on the surface of the bottom electrode material layer 204, thereby improving the reliability of the semiconductor structure.

[0064] The process of performing nitrogen-containing surface treatment on the surface of the transition bottom electrode material layer 203 includes: a nitrogen-containing plasma treatment process.

[0065] In this embodiment, the gas of the nitrogen-containing plasma treatment process includes ammonia. The method for passivating the surface of the transition bottom electrode material layer 203 includes a plasma containing ammonia, and the nitrogen ions in the plasma containing ammonia can reduce the natural oxide layer on the transition bottom electrode material layer 203, and fill the oxygen vacancy defects on the transition bottom electrode material layer 203 caused by environmental factors, so that the formed passivation material layer is chemically stable. When the device is working later, it is not easy to leak or even be broken down at the defects on the surface of the transition bottom electrode material layer 203, thereby improving the reliability of the semiconductor structure.

[0066] In this embodiment, the nitrogen-containing plasma treatment process lasts for 30 seconds to 40 seconds. If the nitrogen-containing plasma treatment time is too short, the surface of the transition bottom electrode material layer 203 cannot be passivated; if the nitrogen-containing plasma treatment time is too long, the thickness uniformity of the formed passivation material layer 205 is poor because the plasma has a certain amount of energy to impact the surface of the transition bottom electrode material layer 203.

[0067] The material of the passivation material layer 205 includes the material of the bottom electrode material layer 204 containing nitrogen.

[0068] In this embodiment, the material of the passivation material layer 205 includes nitrogen-rich titanium nitride. At this time, the titanium nitride of the passivation material layer 205 has better chemical stability than the titanium nitride of the bottom electrode material layer 204.

[0069] The thickness of the bottom electrode material layer 204 is in the range of 350 angstroms to 450 angstroms. The thickness range of each layer of the capacitor structure formed subsequently is fixed. If the thickness of the bottom electrode material layer 204 is too large or too small, it will affect the distribution of the thickness of each layer of the capacitor structure formed subsequently. If the thickness of the bottom electrode material layer 204 is too small, the resistance of the bottom electrode layer formed subsequently will be too high, thereby affecting the performance of the formed capacitor structure.

[0070] The thickness of the passivation material layer 205 is in the range of 2 angstroms to 3 angstroms. After the transition bottom electrode material layer 203 is subjected to nitrogen-containing surface treatment for an appropriate period of time, the passivation material layer 205 within the thickness range is formed. At this time, the natural oxide layer and oxygen vacancy defects on the surface of the transition bottom electrode material layer 203 are effectively treated, so that the chemical properties of the passivation material layer 205 are relatively stable.

[0071] In other embodiments, the surface of the initial bottom electrode material layer is subjected to a nitrogen-containing surface treatment.

[0072] Please refer to Figure 6 , a dielectric structure material layer is formed on the passivation material layer 205 .

[0073] The dielectric structure material layer is used to subsequently form a dielectric structure.

[0074] The dielectric structural material layer includes a plurality of dielectric material layers; the plurality of layers include a single layer, a double layer or a triple layer.

[0075] The material of the dielectric structural material layer includes a dielectric material, and the dielectric material includes zirconium oxide, tantalum oxide, aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide or silicon oxide. The materials of the dielectric material layers may be all the same, all different or partially the same.

[0076] Several layers of the dielectric material layer can be combined arbitrarily according to the requirements of device performance, and the dielectric constant of the dielectric material layer is not limited.

[0077] The process of forming the dielectric material layer includes a chemical vapor deposition process, a low pressure chemical vapor deposition process, an ion enhanced chemical vapor deposition process or an atomic layer deposition process.

[0078] In this embodiment, the dielectric structural material layer includes three dielectric material layers, including a first dielectric structural material layer 206 , a second dielectric structural material layer 207 located on the first dielectric structural material layer 206 , and a third dielectric structural material layer 208 located on the second dielectric structural material layer 207 .

[0079] The first dielectric structure material layer 206 is used to subsequently form a first dielectric layer, the second dielectric structure material layer 207 is used to subsequently form a second dielectric layer, and the third dielectric structure material layer 208 is used to subsequently form a third dielectric layer.

[0080] In this embodiment, the material of the first dielectric structural material layer 206 includes zirconium oxide; the material of the second dielectric structural material layer 207 includes aluminum oxide; and the material of the third dielectric structural material layer 208 includes zirconium oxide.

[0081] Since the bottom electrode material layer 204 and the passivation material layer 205 located on the bottom electrode material layer 204 are formed by performing a nitrogen-containing surface treatment on the surface of the transition bottom electrode material layer 203, the nitrogen-containing surface treatment can reduce the natural oxide layer on the initial bottom material layer, and fill the oxygen vacancy defects on the initial bottom material layer caused by environmental factors, so that the formed passivation material layer is chemically stable, and after the capacitor structure is subsequently formed, when the device is working, it is not easy to leak or even be broken down at the defects on the surface of the bottom electrode material layer. Therefore, the dielectric structure material layer does not need to be formed with a thicker thickness in order to improve the device's anti-breakthrough capability, thereby avoiding the situation where the capacitance density of the capacitor structure needs to be weakened to improve the device's anti-breakthrough capability, so that the device can maintain a good anti-breakthrough capability and have a higher current density, thereby improving the performance of the device.

[0082] Please continue to refer to Figure 6 , a top electrode material layer 209 is formed on the dielectric structure material layer.

[0083] The material of the top electrode material layer 209 includes metal or metal nitride, the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum, and the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0084] In this embodiment, the material of the top electrode material layer 209 includes titanium nitride.

[0085] Please refer to Figure 7 , the top electrode material layer 209, the dielectric structure material layer and the bottom electrode material layer 204 are etched to form a capacitor structure on the substrate, wherein the capacitor structure includes a bottom electrode layer 215, a passivation layer 214 located on the bottom electrode layer 215, a dielectric structure located on the passivation layer 214, and a top electrode layer 210 located on the dielectric structure, wherein the dielectric structure and the top electrode layer 210 expose a portion of the surface of the passivation layer 214.

[0086] The method for forming the capacitor structure includes: forming a first mask structure (not shown) on the top electrode material layer 209, wherein the first mask structure exposes a portion of the surface of the top electrode material layer; etching the top electrode material layer 209 and the dielectric structure material layer using the first mask structure as a mask until the surface of the passivation material layer 205 is exposed, thereby forming a dielectric structure and a top electrode layer 210 located on the dielectric structure; forming a second mask structure (not shown) on the passivation material layer 205, the dielectric structure and the top electrode layer 210, wherein the second mask structure exposes a portion of the surface of the passivation material layer 205 on the bottom electrode material layer 204; etching the passivation material layer 204 and the bottom electrode material layer 205 using the second mask structure as a mask until the substrate surface is exposed, thereby forming the bottom electrode layer 215 and the passivation layer 214 located on the bottom electrode layer 215.

[0087] The dielectric structure includes a first dielectric layer 213 , a second dielectric layer 212 located on the first dielectric layer 213 , and a third dielectric layer 211 located on the second dielectric layer 212 .

[0088] Please refer to Figure 8 , a dielectric layer 216 and a conductive structure 217 located in the dielectric layer 216 are formed on the substrate, the conductive structure 217 is electrically connected to the bottom electrode layer 215 , and the capacitor structure is located in the dielectric layer 216 .

[0089] The method for forming the conductive structure 217 includes: forming an opening (not shown) in the dielectric layer 216 , wherein the opening exposes the surface of the passivation layer 214 on the bottom electrode layer 215 ; and forming a conductive structure 217 in the opening, wherein the conductive structure 217 is electrically connected to the bottom electrode layer 215 .

[0090] The conductive structure 217 includes a barrier layer (not shown) located on the sidewall surface and the bottom surface of the opening and a conductive layer (not shown) located on the barrier layer.

[0091] The material of the barrier layer includes metal nitride, and the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride; the material of the conductive layer includes metal, and the metal includes a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum.

[0092] In this embodiment, the material of the barrier layer includes titanium nitride, and the material of the conductive layer includes tungsten.

[0093] Since the surface of the transition bottom electrode material layer 203 is subjected to a nitrogen-containing surface treatment to form a bottom electrode material layer 204 and a passivation material layer 205 located on the bottom electrode material layer 204, the nitrogen-containing surface treatment can reduce the natural oxide layer on the transition bottom electrode material layer 203 and fill the oxygen vacancy defects on the transition bottom electrode material layer 203 caused by environmental factors, so that the formed passivation material layer 205 is chemically stable. After the capacitor structure is formed, after the conductive structure 217 electrically connected to the bottom electrode layer 215 is formed, when the device is working, it is not easy to leak or even be broken down at the defects on the surface of the bottom electrode layer 215, thereby improving the reliability of the semiconductor structure.

[0094] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 8 ,include:

[0095] substrate;

[0096] A capacitor structure located on a substrate, the capacitor structure includes a bottom electrode layer 215, a passivation layer 214 located on the bottom electrode layer 215, a dielectric structure located on the passivation layer 214, and a top electrode layer 210 located on the dielectric structure, wherein the dielectric structure and the top electrode layer 210 expose a portion of the surface of the passivation layer 214 on the bottom electrode layer 215.

[0097] In this embodiment, it also includes: a dielectric layer 216 located on the substrate and a conductive structure 217 located in the dielectric layer 216 , the conductive structure 217 is located on the passivation layer 214 , the conductive structure 217 is electrically connected to the bottom electrode layer 215 , and the capacitor structure is located in the dielectric layer 216 .

[0098] In this embodiment, the conductive structure 217 is in contact with the passivation layer 214 .

[0099] In this embodiment, the material of the passivation layer 214 includes a nitrogen-containing bottom electrode layer material, and the nitrogen-containing bottom electrode layer material is a material obtained by nitrogen-containing plasma treatment.

[0100] In this embodiment, the material of the bottom electrode layer 215 includes metal or metal nitride, the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum, and the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0101] In this embodiment, the material of the passivation layer 214 includes nitrogen-rich titanium nitride.

[0102] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, It is characterized in that include: providing a substrate; forming an initial bottom electrode material layer on the substrate; forming a natural oxide layer on the surface of the initial bottom electrode material layer; Performing nitrogen-containing surface treatment on the natural oxide layer to form a bottom electrode material layer and a passivation material layer located on the bottom electrode material layer; forming a dielectric structural material layer on the passivation material layer; forming a top electrode material layer on the dielectric structure material layer; Etching the top electrode material layer, the dielectric structure material layer and the bottom electrode material layer to form a capacitor structure on the substrate, wherein the capacitor structure includes a bottom electrode layer, a passivation layer on the bottom electrode layer, a dielectric structure on the passivation layer and a top electrode layer on the dielectric structure, wherein the dielectric structure and the top electrode layer expose a portion of the surface of the bottom electrode layer; A conductive structure is formed on the bottom electrode layer, wherein the conductive structure is located on the passivation layer and is electrically connected to the bottom electrode layer, and the passivation layer has conductivity.

2. The method for forming a semiconductor structure according to claim 1, It is characterized in that The process of performing nitrogen-containing surface treatment on the natural oxide layer includes: a nitrogen-containing plasma treatment process; the gas of the nitrogen-containing plasma treatment process includes ammonia.

3. The method for forming a semiconductor structure according to claim 2, It is characterized in that The material of the passivation material layer includes a bottom electrode material layer material containing nitrogen.

4. The method for forming a semiconductor structure according to claim 3, It is characterized in that The material of the bottom electrode material layer includes metal or metal nitride, the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum, and the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

5. The method for forming a semiconductor structure according to claim 4, It is characterized in that The material of the passivation material layer includes nitrogen-rich titanium nitride.

6. The method for forming a semiconductor structure according to claim 1, It is characterized in that Before a natural oxide layer is formed on the surface of the initial bottom electrode material layer, the method further includes: flattening the initial bottom electrode material layer to form a transition bottom electrode material layer, wherein the natural oxide layer is located on the surface of the transition bottom electrode material layer.

7. The method for forming a semiconductor structure according to claim 6, It is characterized in that The process for planarizing the initial bottom electrode material layer includes a chemical mechanical polishing process; the parameters of the chemical mechanical polishing process include: the polishing liquid is an acidic solution, and the pH value of the acidic solution ranges from 5 to 9; the grinding rate is 3 angstroms per second to 5 angstroms per second; and the grinding time is 6 seconds to 10 seconds.

8. The method for forming a semiconductor structure according to claim 1, It is characterized in that The thickness of the bottom electrode material layer ranges from 350 angstroms to 450 angstroms.

9. The method for forming a semiconductor structure according to claim 1, It is characterized in that The thickness of the passivation material layer is in the range of 2 angstroms to 3 angstroms.

10. The method for forming a semiconductor structure according to claim 1, It is characterized in that After forming the capacitor structure, the method further includes: forming a dielectric layer on the substrate, wherein the capacitor structure and the conductive structure are located in the dielectric layer.

11. The method for forming a semiconductor structure according to claim 1, It is characterized in that The method for forming the capacitor structure includes: forming a first mask structure on a top electrode material layer, wherein the first mask structure exposes a portion of the surface of the top electrode material layer; etching the top electrode material layer and the dielectric structure material layer using the first mask structure as a mask until the surface of the passivation material layer is exposed, thereby forming a dielectric structure and a top electrode layer located on the dielectric structure; forming a second mask structure on the passivation material layer, the dielectric structure and the top electrode layer, wherein the second mask structure exposes a portion of the surface of the passivation material layer on the bottom electrode material layer; etching the passivation material layer and the bottom electrode material layer using the second mask structure as a mask until the surface of the substrate is exposed, thereby forming the bottom electrode layer and the passivation layer located on the bottom electrode layer.

12. The method for forming a semiconductor structure according to claim 10, It is characterized in that The method for forming the conductive structure comprises: forming an opening in the dielectric layer, wherein the opening exposes the surface of the passivation layer on the bottom electrode layer; and forming a conductive structure in the opening, wherein the conductive structure is located on the passivation layer and is electrically connected to the bottom electrode layer.

13. The method for forming a semiconductor structure according to claim 12, It is characterized in that The conductive structure includes a barrier layer located on the sidewall surface and the bottom surface of the opening and a conductive layer located on the barrier layer.

14. The method for forming a semiconductor structure according to claim 13, It is characterized in that The material of the barrier layer includes metal nitride, and the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride; The material of the conductive layer includes metal, and the metal includes: one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum.

15. The method for forming a semiconductor structure according to claim 1, It is characterized in that The dielectric structure includes a plurality of dielectric layers; the plurality of dielectric layers include a single layer, a double layer or a triple layer.

16. The method for forming a semiconductor structure according to claim 15, It is characterized in that The dielectric structure includes three layers; the dielectric structure includes: a first dielectric layer, a second dielectric layer located on the first dielectric layer, and a third dielectric layer located on the second dielectric layer.

17. The method for forming a semiconductor structure according to claim 1, It is characterized in that The material of the top electrode material layer includes metal or metal nitride, the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum, and the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

18. The method for forming a semiconductor structure according to claim 1, It is characterized in that The substrate comprises: a base; a device layer located on the base, wherein the device layer comprises an isolation structure and a device structure located within the isolation structure, and the device structure comprises a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure.

19. A semiconductor structure formed by the method according to any one of claims 1 to 18, It is characterized in that include: substrate; A capacitor structure located on the substrate, the capacitor structure comprising a bottom electrode layer, a passivation layer located on the bottom electrode layer, a dielectric structure located on the passivation layer, and a top electrode layer located on the dielectric structure, wherein the dielectric structure and the top electrode layer expose a portion of the surface of the passivation layer; A conductive structure is located on the bottom electrode layer, the conductive structure is located on the passivation layer, the conductive structure is electrically connected to the bottom electrode layer, and the passivation layer has conductivity.

20. The semiconductor structure of claim 19, It is characterized in that Also includes: A dielectric layer is located on the substrate, and the capacitor structure and the conductive structure are located in the dielectric layer.

21. The semiconductor structure of claim 19, It is characterized in that The conductive structure is in contact with the passivation layer.

22. The semiconductor structure of claim 19, It is characterized in that The material of the passivation layer includes a nitrogen-containing bottom electrode layer material, and the nitrogen-containing bottom electrode layer material is a material obtained by nitrogen-containing plasma treatment.

23. The semiconductor structure of claim 22, It is characterized in that The material of the bottom electrode layer includes metal or metal nitride, the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum, and the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

24. The semiconductor structure of claim 23, It is characterized in that The material of the passivation layer includes nitrogen-rich titanium nitride.

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