Capacitor, semiconductor device, electronic device, and method for manufacturing the same

Abstract

The application relates to a capacitor structure, comprising: a semiconductor substrate; a plurality of storage node contacts on the semiconductor substrate; each of the storage node contacts is provided with a lower electrode of a half-enclosing structure, and each two opposite lower electrodes of the half-enclosing structure form a lower electrode pair surrounding an upper electrode; the two opposite lower electrodes of the lower electrode pair and the upper electrode are separated from each other by a dielectric layer. The capacitor and the semiconductor device obtained by the manufacturing method can effectively reduce the difficulty of the manufacturing process under the premise of ensuring the device performance such as the storage capacity of the capacitor storage unit, and on the basis of simplifying the process, the limitation of the traditional 6F2 trench process mode is broken, so that the gap between the capacitors is reduced, a smaller size than the existing capacitor is prepared, and the integration of the semiconductor device is improved.

Description

Technical Field

[0001] This application relates to capacitors and methods of manufacturing the same, as well as to semiconductor devices, electronic devices and methods of manufacturing the same including the capacitor. Background Technology

[0002] In recent years, semiconductor manufacturers have increasingly focused on researching highly integrated, high-speed semiconductor devices due to the demands of semiconductor users for low power consumption, high storage capacity, and high speed. Dynamic Random Access Memory (DRAM), in particular, is widely used as a semiconductor memory cell because of its free data input / output capabilities and large storage capacity.

[0003] However, to rapidly improve the integration and scalability of memory, the integration density of semiconductor devices is constantly increasing, and the design size of semiconductor devices is correspondingly decreasing. For example, DRAM is typically a collection of cells, and each cell has a MOS (Metal Oxide Semiconductor) transistor and a storage capacitor. As integration density increases, the size of the semiconductor chip decreases, and the size of the capacitor must also decrease. The reduction in capacitor size leads to a gradual decrease in the spacing between electrodes, which in turn reduces the capacitance of the capacitor, thereby reducing the storage capacity. However, even considering the increased integration density of semiconductor memory, the capacitors must still have sufficient capacitance to ensure the smooth operation and performance of the semiconductor memory device.

[0004] There are two main types of DRAM currently in use: one with an 8F2 cell area and the other with a 6F2 cell area. DRAM with 8F2 cells is widely used due to its improved signal-to-noise ratio, but it consumes more cell area compared to DRAM with 6F2 cells because it has more unused space. While DRAM with 6F2 cells offers some improvements in reducing cell area, manufacturing with this technology still presents challenges, such as the process difficulties associated with smaller cells.

[0005] Therefore, how to propose a simpler manufacturing method for capacitor storage cells to achieve a smaller storage cell area and higher charge storage capacity has become an important technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0006] The objective of this application is achieved through the following technical solution:

[0007] According to one or more embodiments, this application discloses a capacitor structure, including:

[0008] Semiconductor substrate;

[0009] Multiple memory node contacts located on a semiconductor substrate;

[0010] Each of the storage node contacts is provided with a lower electrode of a semi-enclosed structure, and every two opposing lower electrodes of the semi-enclosed structure form a pair of lower electrodes surrounding the upper electrode;

[0011] The two opposing lower electrodes of the lower electrode pair and the upper electrode are separated from each other by a dielectric layer.

[0012] According to one or more embodiments, this application also discloses a method for manufacturing a capacitor structure, which includes the following process steps:

[0013] A semiconductor substrate is provided, wherein a memory node contact portion is provided on the semiconductor substrate;

[0014] A sacrificial mode layer is formed on a semiconductor substrate;

[0015] The sacrificial mold layer is etched to form a plurality of lower electrode recesses, in which the surfaces of two adjacent memory node contacts are exposed;

[0016] A lower electrode layer is deposited to fill the lower electrode groove, followed by chemical mechanical planarization or etch-back to expose the sacrificial mold layer;

[0017] The lower electrode layer and the sacrificial mold layer are etched to form an upper electrode groove, which divides the lower electrode layer into a pair of opposing semi-enclosed lower electrodes;

[0018] A dielectric layer and an upper electrode are formed within the groove of the upper electrode.

[0019] According to one or more embodiments, this application also discloses semiconductor devices, electronic devices, etc., that include the capacitor structure described above or that include the capacitor structure prepared by the manufacturing method described above.

[0020] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description, or some features and advantages may be inferred from the description or determined without question, or may be learned by practicing embodiments of this application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0021] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0022] Figures 1a-1h This is a schematic diagram of the fabrication process of the capacitor structure according to an embodiment of this application.

[0023] Figure 2 This is a top cross-sectional view of the capacitor structure according to an embodiment of this application.

[0024] Figure 3 This is the pattern used when forming the lower electrode groove in the embodiments of this application.

[0025] Figures 4a-4c This is the pattern used when forming the upper electrode groove in the embodiments of this application.

[0026] Figure 5 This is a diagram showing the corresponding positions of the upper electrode groove and the lower electrode groove. Detailed Implementation

[0027] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are shown. However, the present application is not limited to the embodiments set forth herein. Rather, these embodiments are provided to thoroughly and completely illustrate and fully convey the scope of the present application to those skilled in the art. In the drawings, the thickness of layers and regions may be exaggerated for clarity. The same numerals throughout the text identify the same elements. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0028] The terminology used herein is for the purpose of detailed description of embodiments only and is not intended to limit the application. As used herein, unless explicitly stated otherwise, the singular forms “a,” “the,” and “the” also include the plural forms. It should also be understood that the term “comprising” as used in the specification indicates the presence of the stated feature, integral, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0029] It should be understood that when an element, such as a layer, region, or substrate, is referred to as "on another element" or "extends to another element," it can be directly on the other element, directly extended to the other element, or there may be intermediate elements. Conversely, when an element is referred to as "directly on another element" or "directly extended to another element," there are no intermediate elements. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0030] It should be understood that although the terms first, second, etc., may be used herein to describe different elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts are not limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the spirit of this application, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0031] Furthermore, relative terms, such as “below” or “bottom” and “above” or “top”, are used here to describe the relationship between one element and another as shown in the accompanying drawings. It should be understood that relative terms include not only the orientations described in the drawings but also different orientations of the device. For example, if a device in the drawing is flipped, an element described as being below another element becomes above another element. Therefore, the exemplary term “below” includes both the “below” and “above” orientations depending on the specific orientation of the drawing. Similarly, if a device in the drawing is flipped, an element described as “below other elements” or “under other elements” is oriented above other elements. Therefore, the exemplary term “below” or “under…” includes both the above and below orientations.

[0032] Embodiments of this application are described herein with reference to illustrative cross-sectional views (and / or plan views) illustrating idealized embodiments. Similarly, deviations from the schematic shapes are expected due to factors such as manufacturing processes and / or tolerances. Therefore, the embodiments of this application are not to be construed as limitations on the specific shapes of the areas illustrated herein, but rather to include shape deviations caused, for example, by manufacturing processes. For instance, etched areas illustrated as or described as rectangular typically have circular or curved features. Thus, the areas illustrated are schematic in nature, and their shapes do not represent the precise shapes of the device areas nor limit the scope of this application.

[0033] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms, such as those defined in common dictionaries, should be interpreted as consistent with their meaning in relevant art literature and, unless expressly defined herein, not as idealized or overly formal. Those skilled in the art will understand that references to structural or functional components configured adjacent to another component may have overlapping or subordinate parts.

[0034] This application discloses a capacitor structure and its manufacturing method. Each storage node of the capacitor has a lower electrode with a semi-circular, semi-enclosed structure, for example, a semi-cylindrical shape. Two opposing semi-enclosed lower electrodes form a lower electrode pair surrounding the upper electrode, as well as any suitable shape obtainable in the art. The following embodiments use a capacitor with a semi-cylindrical, semi-enclosed lower electrode as an example, but this application is not limited to this. The specific capacitor structure and manufacturing process are as follows:

[0035] like Figure 1h and Figure 2As shown, this application embodiment exemplifies a semiconductor device including a capacitor structure. This semiconductor device can be used in, for example, some electronic device, such as a smartphone, computer, tablet computer, wearable smart device, artificial intelligence device, power bank, etc. The semiconductor device includes a semiconductor substrate, such as the semiconductor substrate of a MOS (Metal-Oxide-Semiconductor) transistor circuit element. Functional components (not shown), such as gate, source / drain, and bit lines, are formed on the semiconductor substrate. An interlayer insulating layer 201 is formed on the semiconductor substrate; a storage node contact 202 is formed on the interlayer insulating layer 201. A lower electrode 209 can be formed on the upper part of the contact portion 202 of each storage node. In this embodiment, the lower electrode 208 has, for example, a semi-cylindrical C-shaped opening semi-enclosed structure. The C-shaped openings of the two lower electrodes 209A and 209B located on two adjacent storage nodes are mirror-facing each other, forming a lower electrode pair. This lower electrode pair surrounds the periphery of the upper electrode 210. A dielectric layer 210 is formed between the lower electrodes 209A, 209B, and the upper electrode 219, separating the three from each other. In this way, the lower electrode 209A and the upper electrode 211, as well as the lower electrode 209B and the upper electrode 211, form two independent capacitor storage cells. Overall, on a cross-section parallel to the semiconductor substrate, all lower electrodes can be arranged linearly in parallel along a first direction, and these linearly arranged lower electrodes are staggered on adjacent lines; simultaneously, all upper electrodes can also be arranged linearly in parallel along a second direction perpendicular to the first direction, and these linearly arranged upper electrodes are also staggered on adjacent lines. In other embodiments, on a cross-section parallel to the semiconductor substrate, upper electrodes on the same line can be connected in pairs to form a whole, or all upper electrodes on the same line can be connected to each other to form a whole.

[0036] Next, refer to Figures 1a-1h As shown, the manufacturing process and materials used in the above-described semiconductor device, according to an embodiment of this application, will be described in further detail below:

[0037] The manufacturing process of this application can first provide a semiconductor substrate on which circuit elements such as BCAT (Buried Channel Array Transistor) transistors have already been formed. Functional components such as gate, source / drain, and bit lines (not shown) are formed on the semiconductor substrate.

[0038] like Figure 1aAs shown, an interlayer insulating layer 201 can be formed on the semiconductor substrate; a storage node 202 is formed on the interlayer insulating layer 201, and the storage node 202 can be made of materials such as W or Co.

[0039] Subsequently, a sacrificial mold layer 203 (mold) can be formed on the surfaces of the interlayer insulating layer 201 and the storage node 202. The sacrificial mold layer 203 commonly uses oxides, specifically an oxide sacrificial mold layer (mold oxide). Its material can contain doped oxides, such as any one or a combination of two or more of SiO2, SiOH, PSG (Phosphosilicate glass), BPSG (Borophosphosilicate glass), SiCOH, and TEOS (Tetraethylorthosilicate). The sacrificial mold layer can also adopt a multi-layered structure, such as the layered structure of TEOS. The sacrificial mold layer can be processed using suitable processes such as chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0040] Subsequently, a hard mask layer 204 (HM) can be formed on the surface of the oxide sacrificial mold layer 203. The hard mask layer can include common hard mask materials such as polysilicon (Poly-Si), doped silicon (Dope-Si), amorphous carbon (ACL), and spin-coated silicon (SOH) layers formed using CVD processes. In other embodiments, a hard mask layer can be skipped, and patterning and subsequent etching can be performed directly using a photoresist layer.

[0041] Subsequently, a photoresist layer 205 (PR) can be formed on the surface of the hard mask layer 204. The photoresist layer can be formed using processes such as spin coating. Then, the photoresist layer 205 can be patterned using a developing process to expose the surface of the hard mask layer 204. The mask pattern after removing the photoresist portion is as follows: Figure 3 As shown, the mask pattern consists of multiple rectangular lower electrode recess mask pattern units. These multiple lower electrode recess mask pattern units can be arranged linearly in parallel along a first direction on a cross section parallel to the semiconductor substrate, and are staggered on adjacent lines. The projection of each lower electrode recess mask pattern unit on the cross section parallel to the semiconductor substrate is based on the standard of substantially covering two adjacent memory nodes (see reference). Figure 2 (as shown in the structure).

[0042] like Figure 1bAs shown, conventional etching methods can then be used, according to... Figure 3 The photoresist layer 205 is patterned according to the mask pattern shown. The hard mask layer 204 and the sacrificial mask layer 203 are etched to obtain the lower electrode recess 206. The top view cross-sectional structure of the lower electrode recess 206 can be combined with... Figure 2 and 3 As shown, the rectangular frame of the lower electrode recess mask pattern unit basically corresponds to the position of the lower electrode recess. That is, the etching of the lower electrode recess 206 can be based on the standard that the bottom of the recess basically exposes the entire surface of two adjacent memory nodes 202. The etching can be carried out using conventional dry etching processes, such as dry etching processes using fluorine-containing gases such as CH2F2 / O2 / Ar / CHF3; or conventional wet etching processes can be carried out, such as mixed buffer solutions including HF and NH4F, for example, LAL solutions in which HF:NH4F are mixed in a ratio of about 1:6 to 1:10.

[0043] Subsequently, the hard mask layer 204 and the photoresist layer 205 can be removed, for example, by using conventional ashing processes or other removal methods.

[0044] like Figure 1c As shown, subsequently, a lower electrode material can be deposited in the lower electrode recess 206 to fill the lower electrode recess 206 and cover it with the sacrificial mold layer 203, forming the lower electrode layer 207 (Bottom Electrode). Since current technologies typically use dielectric materials with high dielectric constants, such as Ta2O5, Al2O3, and / or HfO2, as the dielectric layer of capacitors, the interface quality between the dielectric material and the polycrystalline silicon electrode may be reduced. In particular, the interface quality between the dielectric material and the polycrystalline silicon electrode may decrease as the dielectric constant increases; therefore, a metal with high work function, such as TiN, can be used. x TaN x WN x Electrodes can be made from any one or more of refractory metals to replace traditional polycrystalline silicon electrodes. Common deposition processes such as CVD, PECVD, and ALD (atomic layer vapor deposition) can be used.

[0045] like Figure 1dAs shown, the surface of the lower electrode layer can then be chemically and mechanically planarized (CMP) until the top surface of the sacrificial mold layer 203 is exposed, thereby isolating the lower electrode layers from each other. Alternatively, other processes can be used to etch back the surface of the lower electrode layers to expose the top surface of the sacrificial mold layer 203 and isolate the lower electrode layers from each other. Examples of etch back processes include reactive ion etching (RIE).

[0046] like Figure 1e As shown, a hard mask layer 204' (HM) can then be formed on the surfaces of the lower electrode layer 207 and the sacrificial mold layer 203. The hard mask layer can include common hard mask materials such as polysilicon (Poly-Si), doped silicon (Dope-Si), amorphous carbon (ACL), and spin-coated silicon (SOH) layers formed using CVD processes. In other embodiments, a photoresist layer can be used directly for patterning and subsequent etching without forming a hard mask layer.

[0047] like Figure 1f As shown, a photoresist layer 205' (PR) can then be formed on the surface of the hard mask layer 204'. The photoresist layer can be formed using, for example, a spin coating process. Subsequently, the photoresist layer 205' can be patterned using a development process to expose the surface of the hard mask layer 204'. The patterning can be performed using, for example, a double patterning technique or a multi-patterning technique. The mask pattern after removing the photoresist portion is as follows: Figure 4a As shown, the mask pattern consists of multiple upper electrode groove mask pattern units arranged in a "+" cross shape. These multiple upper electrode groove mask pattern units can be arranged linearly in parallel along a second direction perpendicular to the first direction on a cross section parallel to the semiconductor substrate, and are staggered on adjacent lines; as shown Figure 5As shown, the upper electrode recess mask pattern unit can correspond one-to-one with the lower electrode recess mask pattern unit. The intersection point of the "+" cross of the projection of each upper electrode recess mask pattern unit on a section parallel to the semiconductor substrate is aligned with the center of the projection of the corresponding lower electrode recess mask pattern unit on the same section parallel to the semiconductor substrate. Thus, the projection of the pattern extending along the first direction within the "+" cross falls entirely within the projection of the lower electrode recess mask pattern unit, primarily for forming the dielectric layer and the deposition recess of the upper electrode within the lower electrode layer. The projection of the pattern extending along the second direction extends to the outside of the projection of the lower electrode recess mask pattern unit, for "splitting" each lower electrode layer unit into two independent lower electrodes to form a lower electrode pair surrounding the upper electrode. In this embodiment, similar to the rectangular shape of the lower electrode recess mask pattern unit, the upper electrode recess mask pattern unit extends along the first direction... The extended pattern and the pattern extending along the second direction of the upper electrode groove mask pattern unit are both rectangular. To achieve their respective functions, the width of the lower electrode groove mask pattern unit is greater than the width of the pattern extending along the first direction of the upper electrode groove mask pattern unit (thus ensuring that the entire pattern extending along the first direction of the upper electrode groove mask pattern unit falls inside the lower electrode groove mask pattern). The width of the pattern extending along the first direction of the upper electrode groove mask pattern unit is greater than the width of the pattern extending along the second direction of the upper electrode groove mask pattern unit (the pattern extending along the second direction of the upper electrode groove mask pattern unit only needs to achieve a "separating" effect). Simultaneously, the length of the pattern extending along the second direction of the upper electrode groove mask pattern unit is at least slightly greater than the width of the lower electrode groove mask pattern unit (thus ensuring that the pattern extending along the second direction of the upper electrode groove mask pattern unit extends outside the lower electrode groove mask pattern to ensure "separation"). In other embodiments, it can also be as follows... Figure 4b As shown, connecting adjacent "+" crosses on the same line in pairs simplifies the patterning process, reducing manufacturing difficulty without affecting device performance; furthermore, in other embodiments, it can also be done as follows: Figure 4c As shown, all the "+" crosses on the same line are connected to each other to further simplify the pattern and process.

[0048] Subsequently, conventional etching techniques can be used to etch the hard mask layer 204' and the lower electrode layer 207 according to the patterned photoresist layer 205' to obtain the upper electrode recess 208. The top cross-sectional view of the upper electrode recess 208 can be compared with... Figure 4a , 4bCorresponding to 4c, the bottom of the upper electrode recess 208 is etched to expose the surfaces of two adjacent memory nodes 202. After etching, each lower electrode layer 207 is divided into two semi-cylindrical, C-shaped, semi-enclosed lower electrodes 209A and 209B. The etching can be performed using conventional dry etching processes, such as dry etching using fluorine-containing gases (CH2F2 / O2 / Ar / CHF3); or conventional wet etching processes can be performed, such as using a mixed buffer solution including HF and NH4F, for example, a LAL solution containing HF:NH4F mixed in a ratio of approximately 1:6 to 1:10.

[0049] Subsequently, the hard mask layer 204' and the photoresist layer 205' can be removed, for example, by using conventional ashing processes or other removal methods.

[0050] like Figure 1g As shown, a high-dielectric material can then be deposited on the inner wall of the upper electrode recess 208, the lower electrodes (including all lower electrodes of 209A and 209B), and the surface of the sacrificial mold layer 203 to form a dielectric layer 210; the high-dielectric material can be AlO. x HfO x ZrO x TaO x Any one or more combinations of the following; the deposition process is, for example, the ALD process.

[0051] like Figure 1h As shown, an upper electrode material can then be deposited on the surface of dielectric layer 210 to cover dielectric layer 210 and fill upper electrode groove 208 to form upper electrode 211; the upper electrode material can be metal W or doped silicon, etc. The deposition process can be CVD, PECVD, etc. Thus, as shown in the cross-sectional top view... Figure 2As shown, a lower electrode 209 is formed on the upper part of each storage node 202. The lower electrode 209 has a semi-cylindrical C-shaped semi-enclosed structure, and the semi-cylindrical C-shaped openings are mirror-facing each other, so that the two lower electrodes 209A and lower electrodes 209B located on two adjacent storage nodes form a lower electrode pair. The lower electrode pair surrounds the periphery of the upper electrode 211. A dielectric layer 210 is formed between the lower electrodes 209A, lower electrodes 209B and upper electrodes 211 to separate the three from each other. The lower electrodes 209A and upper electrodes 211, as well as the lower electrodes 209B and upper electrodes 211, form two independent capacitor storage cells. Of course, based on different patterning, it is also possible to obtain a capacitor in which adjacent upper electrodes along the same line of the second direction are connected in pairs to form a whole in the entire direction perpendicular to the semiconductor substrate, that is, the four lower electrodes (two pairs of lower electrodes) correspond to the upper electrode that forms a whole in the entire direction perpendicular to the semiconductor substrate; it is also possible to make all upper electrodes along the same line of the second direction connected to each other to form a whole in the entire direction perpendicular to the semiconductor substrate, that is, the lower electrode pairs in the same column correspond to the upper electrode that forms a whole in the entire direction perpendicular to the semiconductor substrate.

[0052] The manufacturing method described in this application can effectively reduce the difficulty of the manufacturing process while ensuring the storage capacity and other device performance of the capacitor. Furthermore, it breaks through the limitations of the traditional 6F2 trench process by simplifying the process, thereby reducing the gap between capacitors and producing a smaller size than existing capacitors, thus improving the integration of semiconductor devices.

[0053] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0054] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A capacitor structure, comprising: Semiconductor substrate; Multiple memory node contacts located on a semiconductor substrate; Each of the storage node contacts is provided with a lower electrode of a semi-enclosed structure, and every two opposing lower electrodes of the semi-enclosed structure form a pair of lower electrodes surrounding the upper electrode; The two opposing lower electrodes of the lower electrode pair and the upper electrode are separated from each other by a dielectric layer.

2. The capacitor structure according to claim 1, characterized in that: In a cross-section parallel to the semiconductor substrate, the lower electrodes are arranged in a parallel linear arrangement along a first direction, and the upper electrodes are arranged in a parallel linear arrangement along a second direction perpendicular to the first direction.

3. The capacitor structure according to claim 2, characterized in that: The linearly arranged lower electrodes are staggered on two adjacent lines; or, the linearly arranged lower electrodes are staggered on two adjacent lines and the linearly arranged upper electrodes are staggered on two adjacent lines.

4. The capacitor structure according to claim 2, characterized in that: The upper electrodes on the same line are connected in pairs to form a whole; or, all the upper electrodes on the same line are connected to each other to form a whole.

5. The capacitor structure according to any one of claims 1-4, characterized in that: In a cross section parallel to the semiconductor substrate, the lower electrodes of each pair of opposing semi-enclosed structures are in a C-shape.

6. A method for manufacturing a capacitor structure, comprising the following process steps: A semiconductor substrate is provided, wherein a memory node contact portion is provided on the semiconductor substrate; A sacrificial mode layer is formed on a semiconductor substrate; The sacrificial mold layer is etched to form a plurality of lower electrode recesses, in which the surfaces of two adjacent memory node contacts are exposed; A lower electrode layer is deposited to fill the lower electrode groove, followed by chemical mechanical planarization or etch-back to expose the sacrificial mold layer; The lower electrode layer and the sacrificial mold layer are etched to form an upper electrode groove, which divides the lower electrode layer into a pair of opposing semi-enclosed lower electrodes; A dielectric layer and an upper electrode are formed within the groove of the upper electrode.

7. The manufacturing method according to claim 6, characterized in that: When etching the sacrificial mold layer to form multiple lower electrode grooves, the multiple lower electrode groove mask pattern units are arranged linearly in parallel along a first direction on a cross section parallel to the semiconductor substrate, and the lower electrode groove mask pattern units are staggered on adjacent lines.

8. The manufacturing method according to claim 7, characterized in that: When etching the lower electrode layer and the sacrificial mold layer to form the upper electrode groove, the multiple upper electrode groove mask pattern units corresponding one-to-one with the lower electrode groove mask pattern units are arranged linearly in parallel along a second direction perpendicular to the first direction on a cross section parallel to the semiconductor substrate. Each upper electrode groove mask pattern unit is approximately arranged in a "+" cross shape. The intersection point of the "+" cross of the projection of each upper electrode groove mask pattern unit on the cross section parallel to the semiconductor substrate is aligned with the center of the projection of the corresponding lower electrode groove mask pattern unit on the cross section parallel to the semiconductor substrate. The projection of the pattern extending along the first direction of the "+" cross falls entirely inside the projection of the lower electrode groove mask pattern unit, and the projection of the pattern extending along the second direction extends to the outside of the projection of the lower electrode groove mask pattern unit.

9. The manufacturing method according to claim 8, characterized in that: In the second direction, adjacent pattern units forming a "+" cross on the same line are connected in pairs; or, all pattern units forming a "+" cross on the same line in the second direction are connected to each other.

10. The manufacturing method according to claim 8, characterized in that: The patterns of the lower electrode groove mask pattern unit, the upper electrode groove mask pattern unit extending along the first direction, and the upper electrode groove mask pattern unit extending along the second direction are all rectangular, and the width of the pattern of the upper electrode groove mask pattern unit extending along the first direction is greater than the width of the pattern of the upper electrode groove mask pattern unit extending along the second direction.

11. The manufacturing method according to claim 6, characterized in that: The etching is performed based on a patterned photoresist layer and a mask layer; or, the etching is performed based solely on a patterned photoresist layer.

12. The manufacturing method according to claim 11, characterized in that: The patterning employs dual patterning or multiple patterning techniques.

13. A semiconductor device comprising the capacitor structure as described in any one of claims 1-5, or comprising the capacitor structure prepared by the manufacturing method as described in any one of claims 6-12.

14. An electronic device comprising the semiconductor device as claimed in claim 13.

15. The electronic device according to claim 14, wherein the electronic device includes a smartphone, a computer, a tablet computer, a wearable smart device, an artificial intelligence device, and a power bank.

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