semiconductor structure

Abstract

The present invention discloses a semiconductor structure. The semiconductor structure includes a channel element. The channel element includes a substrate portion and a vertical channel portion. The vertical channel portion is adjacent to the substrate portion. Both the substrate portion and the vertical channel portion include single crystal silicon.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure. Background Art

[0002] In recent years, the size of semiconductor devices has been gradually reduced. In semiconductor technology, the reduction of feature size, the improvement of speed, performance, density and cost per unit integrated circuit are all very important goals. Summary of the Invention

[0003] The present invention relates to a semiconductor structure and a manufacturing method thereof.

[0004] According to one aspect of the present invention, a semiconductor structure is provided, comprising a channel element. The channel element comprises a substrate portion and a vertical channel portion. The vertical channel portion is adjacent to the substrate portion. Both the substrate portion and the vertical channel portion comprise single crystal silicon.

[0005] According to another aspect of the present invention, a semiconductor structure is provided, comprising a channel element. The channel element comprises a substrate portion and a vertical channel portion. The vertical channel portion is adjacent to the substrate portion. The substrate portion and the vertical channel portion have a uniform and / or continuous crystal structure as a whole.

[0006] According to yet another aspect of the present invention, a method for fabricating a semiconductor structure is provided, comprising the following steps: providing a channel material matrix. The channel material matrix comprises a substrate portion and an upper channel material portion adjacent to the substrate portion. An etching step is performed to pattern the upper channel material portion to form a vertical channel portion and define an upper substrate surface of the substrate portion.

[0007] In order to better understand the above and other aspects of the present invention, the following embodiments are specifically described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A cross-sectional view of a semiconductor structure according to an embodiment is shown.

[0009] Figure 2 A cross-sectional view of a semiconductor structure in another embodiment is shown.

[0010] Figures 3 to 17 A method for manufacturing a semiconductor structure according to an embodiment is shown.

[0011] Figures 18 to 22 A method for manufacturing a semiconductor structure according to another embodiment is shown.

[0012]

Explanation of symbols

[0013] 100A, 100B: Channel elements

[0014] 110: substrate part

[0015] 111: End surface of the first upper channel

[0016] 112: Upper substrate surface

[0017] 120A, 120B: Vertical channel section

[0018] 121: Channel sidewall surface

[0019] 122: End face of the second upper channel

[0020] 150: Channel material matrix

[0021] 160: Upper Channel Materials Department

[0022] 210: First insulation layer

[0023] 220: Second insulation layer

[0024] 230: The third insulation layer

[0025] 400: Insulation element

[0026] 500: conductive layer

[0027] 600: Spacer

[0028] 700: Insulation column

[0029] 880: Hard mask

[0030] 882: Material layer

[0031] 884: Laminated structure

[0032] 886: Hole

[0033] 888: Slit

[0034] 890: Notch

[0035] D1: Second dielectric layer

[0036] D2: First dielectric layer

[0037] E1: second gate electrode layer

[0038] E2: first gate electrode layer

[0039] k1: First source / drain terminal

[0040] k2: Second source / drain terminal

[0041] T1, T2: transistors DETAILED DESCRIPTION

[0042] The following is an illustration of some embodiments. It should be noted that the present invention does not show all possible embodiments, and other embodiments not proposed in the present invention may also be applicable. Furthermore, the dimensional ratios in the drawings are not drawn in proportion to the actual product. Therefore, the description and illustrations are only used to describe the embodiments and are not used to limit the scope of protection of the present invention. In addition, the descriptions in the embodiments, such as local structures, process steps and material applications, etc., are only for illustrative purposes and are not intended to limit the scope of protection of the present invention. The details of the steps and structures of the embodiments can be changed and modified according to the needs of the actual application process without departing from the spirit and scope of the present invention. The following is an illustration of the same / similar elements represented by the same / similar symbols.

[0043] Please refer to Figure 1 , which illustrates a cross-sectional view of a semiconductor structure in one embodiment. The channel element 100A includes a substrate portion 110 and a vertical channel portion 120A. The vertical channel portion 120A is connected to the substrate portion 110.

[0044] In one embodiment, both the substrate portion 110 and the vertical channel portion 120A comprise a single crystal material, such as single crystal silicon, thereby exhibiting excellent carrier mobility. In one embodiment, no crystal interfaces (e.g., horizontal crystal interfaces or crystal interface planes) exist within the channel element 100A (i.e., the entirety of the substrate portion 110 and the vertical channel portion 120A). The substrate portion 110 and the vertical channel portion 120A have a uniform and / or continuous crystalline structure. Consequently, the channel element 100A exhibits excellent carrier mobility. In one embodiment, the substrate portion 110 and the vertical channel portion 120A may be formed of single crystal silicon.

[0045] Substrate portion 110 includes a first upper channel end surface 111 and an upper substrate surface 112. Vertical channel portion 120A has a solid cylindrical shape. Vertical channel portion 120A includes a channel sidewall surface 121 and a second upper channel end surface 122. Second upper channel end surface 122 is located above first upper channel end surface 111. Channel sidewall surface 121 is between upper substrate surface 112 and second upper channel end surface 122. Upper substrate surface 112 is between first upper channel end surface 111 and channel sidewall surface 121. Opposing end surfaces of channel element 100A are first upper channel end surface 111 and second upper channel end surface 122.

[0046] The second gate electrode layer E1 is adjacent to the upper substrate surface 112 of the substrate portion 110 and the channel sidewall surface 121 of the vertical channel portion 120A. A second dielectric layer D1 is between the second gate electrode layer E1 and the channel element 100A. A first insulating layer 210 is on the upper surface of the second gate electrode layer E1. The first gate electrode layer E2 is above the upper substrate surface 112 of the substrate portion 110 and adjacent to the channel sidewall surface 121 of the vertical channel portion 120A. The first gate electrode layer E2 is on the upper surface of the first insulating layer 210. The first dielectric layer D2 is between the first gate electrode layer E2 and the vertical channel portion 120A of the channel element 100A. A second insulating layer 220 is on the first dielectric layer D2 on the upper surface of the first gate electrode layer E2. A third insulating layer 230 is on the second insulating layer 220 and the vertical channel portion 120A. The insulating element 400 passes through the second dielectric layer D1, the second gate electrode layer E1, the first dielectric layer D2, the first gate electrode layer E2, the second insulating layer 220, and the third insulating layer 230. The conductive layer 500 passes through the insulating element 400 and is electrically connected to the first upper channel end surface 111 of the substrate portion 110. The second dielectric layer D1 extends continuously between the lower surface and the sidewall surface of the second gate electrode layer E1. The outer sidewall surface of the second dielectric layer D1 directly contacts the first insulating layer 210, and the inner sidewall surface of the second dielectric layer D1 directly contacts the vertical channel portion 120A.

[0047] Transistor T1 includes substrate portion 110 and vertical channel portion 120A of channel element 100A, second gate electrode layer E1, and second dielectric layer D1. Transistor T2 includes vertical channel portion 120A of channel element 100A, first gate electrode layer E2, and first dielectric layer D2. Second dielectric layer D1 and first dielectric layer D2 can have different material groups.

[0048] The first upper channel end surface 111 and the second upper channel end surface 122 of the channel element 100A are electrically connected to a first source / drain terminal k1 and a second source / drain terminal k2, respectively. The conductive layer 500 is electrically connected between the first upper channel end surface 111 of the substrate portion 110 and the first source / drain terminal k1. The first source / drain terminal k1 is one of the source terminal and the drain terminal. The second source / drain terminal k2 is the other of the source terminal and the drain terminal.

[0049] In one embodiment, transistor T1 is an access transistor, and its second dielectric layer D1 may include a dielectric material film suitable for use as a gate dielectric layer. The dielectric material film may include an oxide, such as silicon oxide, a nitride, such as silicon nitride, or other suitable film materials. Transistor T2 is a memory transistor, and its first dielectric layer D2 may include a dielectric material film suitable for use as a memory layer. The first dielectric layer D2 may include an oxide-nitride-oxide (ONO) structure. However, the present invention is not limited thereto, and the memory layer may include any charge trapping structure, such as an ONONO structure, an ONONONO structure, or a BE-SONOS structure. For example, the charge trapping layer may use a nitride, such as silicon nitride, or other similar high-k materials, including metal oxides, such as aluminum oxide (Al2O3) or hafnium oxide (HfO2). The first source / drain terminal k1 may be a terminal of a source line (SL) or a reference line. The second source / drain terminal k2 may be a terminal of a drain line or a bit line (BL).

[0050] In another embodiment, transistor T1 is a memory transistor, and its second dielectric layer D1 may include the aforementioned dielectric material film suitable for a memory layer. Transistor T2 is an access transistor, and its first dielectric layer D2 may include the aforementioned dielectric material film suitable for a gate dielectric layer. The first source / drain terminal k1 may be a terminal for a drain line or a bit line. The second source / drain terminal k2 may be a terminal for a source line or a reference line.

[0051] In an embodiment, the semiconductor structure can be applied to a vertical channel 3D 2T NOR memory device, wherein each unit memory cell of a memory cell array includes a transistor T1 and a transistor T2 . The access transistor can be operated as a field effect transistor.

[0052] Figure 2 A cross-sectional view of a semiconductor structure in another embodiment is shown. Figure 1The differences in the semiconductor structures shown are described as follows. Spacers 600 are located on the second upper channel end surface 122 of the vertical channel portion 120B of the channel element 100B. The vertical channel portion 120B and the spacers 600 may have a tubular shape (or a hollow column shape). In one embodiment, the vertical channel portion 120B and the spacers 600 may have a circular tubular shape, but the present invention is not limited thereto. In other embodiments, the vertical channel portion 120B and the spacers 600 may have an elliptical tubular shape, a regular (or symmetrical) or irregular (or asymmetrical) curved annular tube shape, or a polygonal annular tube shape. An insulating pillar 700 passes through the vertical channel portion 120B and the spacers 600. The insulating pillar 700 is located within the sidewall surfaces of the vertical channel portion 120B and the sidewall surfaces of the spacers 600. The bottom surface of the insulating pillar 700 is below the upper substrate surface 112 of the substrate portion 110. The third insulating layer 230 is located on the second insulating layer 220, the spacers 600, and the insulating pillar 700.

[0053] Figures 3 to 17 A method for manufacturing a semiconductor structure according to an embodiment is shown.

[0054] Please refer to Figure 3 , providing a channel material matrix 150. The channel material matrix 150 includes a substrate portion 110 (or a lower channel material portion) and an upper channel material portion 160 adjacent to (or continuously connected to) the substrate portion 110. In one embodiment, both the substrate portion 110 and the upper channel material portion 160 may comprise single crystal silicon material. In one embodiment, the entire channel material matrix 150 (or the entire substrate portion 110 and the upper channel material portion 160) is a semiconductor material formed continuously in a single process (or a common process). In one embodiment, the channel material matrix 150 may be a silicon wafer cut from a silicon ingot. In one embodiment, the channel material matrix 150 may be a semiconductor material film formed on the surface of the wafer in a single epitaxial process or a single deposition process. The silicon wafer or semiconductor material film may have a uniform and / or continuous crystal structure. In one embodiment, the channel material matrix 150 is composed of single crystal silicon, for example, p-type single crystal silicon.

[0055] Please refer to Figure 4 A hard mask 880 is formed on the channel material base 150. In one embodiment, the hard mask 880 may comprise an oxide, such as silicon oxide, but is not limited thereto and other suitable materials may also be used. An etching step is performed, using the hard mask 880 as an etch mask to pattern the upper channel material portion 160 to form a vertical channel portion 120A and define the upper substrate surface 112 of the substrate portion 110. The vertical channel portion 120A may have a pillar shape.

[0056] Please refer to Figure 5A second dielectric layer D1 is formed on the upper substrate surface 112 of the substrate portion 110 and the channel sidewall surface 121 of the vertical channel portion 120A. In one embodiment, the second dielectric layer D1 may include an oxide formed by an oxidation process, such as silicon oxide, but is not limited thereto. Other suitable deposition processes may also be used to form the dielectric material.

[0057] Please refer to Figure 6 A second gate electrode layer E1 can be formed on the second dielectric layer D1 and the hard mask 880. The second gate electrode layer E1 may include polysilicon material formed using a deposition process, or other suitable semiconductor materials. In one embodiment, the second gate electrode layer E1 includes N-type heavily doped polysilicon material, but the present invention is not limited thereto. The second gate electrode layer E1 may also be made of a conductive material. A chemical mechanical polishing process may be performed to planarize the semiconductor structure.

[0058] Please refer to Figure 7 , the second gate electrode layer E1 can be etched back using a selective etching process.

[0059] Please refer to Figure 8 A first insulating layer 210 is formed on the upper surface of the second gate electrode layer E1 and on the channel sidewall surfaces 121 of the vertical channel portion 120A. In one embodiment, the first insulating layer 210 may include an oxide formed using an oxidation process, such as silicon oxide. The portion of the first insulating layer 210 on the upper surface of the second gate electrode layer E1 may be thicker than the portion on the channel sidewall surfaces 121 of the vertical channel portion 120A. However, the present invention is not limited thereto. The first insulating layer 210 may also be formed of a dielectric material using other suitable deposition processes.

[0060] Please refer to Figure 9 A selective etching process may be used to remove the portions of the first insulating layer 210 and the second dielectric layer D1 on the channel sidewall surface 121 of the vertical channel portion 120A. In one embodiment, this selective etching process may also reduce the portions of the hard mask 880 and the first insulating layer 210 on the upper surface of the second gate electrode layer E1.

[0061] In another embodiment, Figure 7 A first insulating layer 210 is deposited on the semiconductor structure, and then the first insulating layer 210 is planarized by chemical mechanical polishing. Next, the first insulating layer 210 and the second dielectric layer D1 are etched by reactive ion etching (RIE), thereby obtaining the following: Figure 9 The semiconductor structure shown.

[0062] Please refer to Figure 10, forming a material layer 882 on the first insulating layer 210. In one embodiment, the material layer 882 may include a nitride such as silicon nitride formed by a deposition process, but is not limited thereto and other suitable materials may also be used. A chemical mechanical polishing process may be performed to planarize the semiconductor structure.

[0063] Please refer to Figure 11 , the material layer 882 can be etched back using a selective etching process.

[0064] Please refer to Figure 12 , forming a second insulating layer 220 on the material layer 882. In one embodiment, the second insulating layer 220 may include an oxide formed by a deposition process, such as silicon oxide. However, the present invention is not limited thereto. The second insulating layer 220 may also be made of other suitable dielectric materials. A chemical mechanical polishing process may be performed to remove the hard mask 880 and planarize the semiconductor structure.

[0065] Please refer to Figure 13 A third insulating layer 230 is formed on the second insulating layer 220 and the vertical channel portion 120A. In one embodiment, the third insulating layer 230 may include an oxide formed by a deposition process, such as silicon oxide. However, the present invention is not limited thereto. Other suitable dielectric materials may also be used for the third insulating layer 230. The stacked structure 884 may include a second dielectric layer D1, a second gate electrode layer E1, a first insulating layer 210, a material layer 882, a second insulating layer 220, and a third insulating layer 230. The stacked structure 884 is on the upper substrate surface 112 of the substrate portion 110.

[0066] Please refer to Figure 14 An etching step is performed to pattern the stacked structure 884 to form a hole 886 passing through the stacked structure 884 and exposing the first upper channel end surface 111 of the substrate portion 110. The first upper channel end surface 111 can be flush with the upper substrate surface 112 not exposed by the hole 886, or lower than the upper substrate surface 112.

[0067] Please refer to Figure 15 The material layer 882 exposed by the hole 886 can be removed by a selective etching process to form a slit 888. The slit 888 can expose the channel sidewall surface 121 of the vertical channel portion 120A, the upper surfaces of the first insulating layer 210 and the second dielectric layer D1, and the lower surface of the second insulating layer 220.

[0068] Please refer to Figure 16A first dielectric layer D2 is formed in the slit 888. The first dielectric layer D2 can be formed using a deposition process. The first dielectric layer D2 is formed on the upper substrate surface 112 of the substrate portion 110 and the channel sidewall surface 121 of the vertical channel portion 120A. A first gate electrode layer E2 is formed on the first dielectric layer D2 in the slit 888. The first gate electrode layer E2 can include, but is not limited to, a metal formed using a deposition process. Other suitable conductive materials can also be used. In one embodiment, an etch-back process can be used to remove the portions of the first dielectric layer D2 and the first gate electrode layer E2 formed on the sidewall surfaces of the stacked structure 884 exposed by the hole 886.

[0069] Please refer to Figure 17 , forming an insulating element 400 on the sidewall surface of the stacked structure 884 exposed by the hole 886, the sidewall surface of the first dielectric layer D2, and the sidewall surface of the first gate electrode layer E2. The insulating element 400 may have a straight line shape. In one embodiment, the insulating element 400 may include an oxide formed by a deposition process, such as silicon oxide. However, the present invention is not limited to this. Other suitable dielectric materials may also be used for the insulating element 400. A conductive layer 500 is formed on the first upper channel end surface 111 of the substrate portion 110 and the sidewall surface of the insulating element 400. The conductive layer 500 may include a titanium nitride (TiN) film used as a barrier layer and a tungsten (W) film formed on the titanium nitride film. However, the present invention is not limited to this. The conductive layer 500 may include other metals or conductive materials formed by a deposition process. In one embodiment, the above process may be used to form Figure 1 The semiconductor structure.

[0070] Figures 18 to 22 Another embodiment of a method for manufacturing a semiconductor structure is shown. Figure 12 The manufacturing steps are then followed by Figure 18 The manufacturing steps are shown.

[0071] Please refer to Figure 18 The vertical channel portion 120A may be etched back to form a notch 890 to expose the sidewall surface of the stacked structure 884. In one embodiment, the etch back may be performed using a reactive ion etching (RIE) method.

[0072] Please refer to Figure 19, forming spacers 600 on the second upper channel end surface 122 of the vertical channel portion 120A exposed by the recess 890 and on the sidewall surfaces of the stacked structure 884. The spacers 600 may have a tubular shape. In one embodiment, the spacers 600 may comprise an oxide, such as silicon oxide, formed by a deposition process. However, the present invention is not limited thereto. Other suitable dielectric materials may also be used for the spacers 600. The second upper channel end surface 122 of the vertical channel portion 120A is above the top surface of the material layer 882.

[0073] Please refer to Figure 20 The vertical channel portion 120A is etched using the spacer 600 as an etching mask to form a vertical channel portion 120B having a tube shape. In one embodiment, the etching step can be performed using a reactive ion etching method.

[0074] Please refer to Figure 21 , forming insulating pillars 700 within the spacers 600 and the vertical channel portion 120B. In one embodiment, the insulating pillars 700 may comprise an oxide, such as silicon oxide, formed by a deposition process. However, the present invention is not limited thereto. Other suitable dielectric materials may also be used for the insulating pillars 700. In one embodiment, the bottom surface of the insulating pillars 700 is located below the upper substrate surface 112 of the substrate portion 110.

[0075] Please refer to Figure 22 , forming a third insulating layer 230 on the second insulating layer 220 , the spacers 600 and the insulating pillars 700 .

[0076] Then, a similar reference can be made Figures 14 to 17 The manufacturing steps shown in FIG. 8 are used to remove the material layer 882 and form the first dielectric layer D2, the first gate electrode layer E2, the insulating element 400 and the conductive layer 500. In one embodiment, the following can be formed: Figure 2 The semiconductor structure shown.

[0077] According to an embodiment of the present invention, the channel elements (eg, channel element 100A, channel element 100B) are formed from a channel material matrix 150 obtained by a single continuous process (or a common process). Therefore, the channel elements do not have crystal interfaces therein and thus have high carrier mobility.

[0078] So far, the embodiments of the present invention have been described in detail with reference to the accompanying drawings.

[0079] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A semiconductor structure, wherein: include: A channel element comprising a substrate portion and a vertical channel portion, wherein the vertical channel portion is adjacent to the substrate portion, and both the substrate portion and the vertical channel portion comprise single crystal silicon. The substrate portion comprises an upper substrate surface, and the vertical channel portion comprises a channel sidewall surface. A first gate electrode layer is located on the upper substrate surface and the channel sidewall surface; a first dielectric layer is located between the sidewall surface of the first gate electrode layer and the channel sidewall surface of the vertical channel portion; a second gate electrode layer is located on the channel sidewall surface and between the upper substrate surface and the first gate electrode layer; and a second dielectric layer extends continuously between a lower surface and a sidewall surface of the second gate electrode layer. The second dielectric layer and the first dielectric layer comprise a different material group, and the upper surface of the second dielectric layer is connected to the first dielectric layer. and an insulating layer, between the first gate electrode layer and the second gate electrode layer, the second dielectric layer having an outer sidewall surface and an inner sidewall surface relative to the outer sidewall surface, the outer sidewall surface of the second dielectric layer directly contacts the insulating layer, and the inner sidewall surface of the second dielectric layer directly contacts the vertical channel portion.

2. A semiconductor structure, wherein: include: A channel element comprising a substrate portion and a vertical channel portion, wherein the vertical channel portion is adjacent to the substrate portion, the substrate portion and the vertical channel portion having a uniform and / or continuous crystal structure as a whole, the substrate portion comprising an upper substrate surface, the vertical channel portion comprising a channel sidewall surface, a first gate electrode layer located between the upper substrate surface and the channel sidewall surface, a first dielectric layer located between the sidewall surface of the first gate electrode layer and the channel sidewall surface of the vertical channel portion, a second gate electrode layer located on the channel sidewall surface and between the upper substrate surface and the first gate electrode layer, a second dielectric layer extending continuously between a lower surface and a sidewall surface of the second gate electrode layer, the second dielectric layer and the first dielectric layer having a different material group, and the upper surface of the second dielectric layer being connected to the first dielectric layer; and an insulating layer, between the first gate electrode layer and the second gate electrode layer, the second dielectric layer having an outer sidewall surface and an inner sidewall surface relative to the outer sidewall surface, the outer sidewall surface of the second dielectric layer directly contacts the insulating layer, and the inner sidewall surface of the second dielectric layer directly contacts the vertical channel portion.

3. The semiconductor structure according to claim 1 or 2, wherein: An access transistor is included, wherein the access transistor includes the channel element, the first gate electrode layer and the first dielectric layer.

4. The semiconductor structure according to claim 1 or 2, wherein: A memory transistor is included, wherein the memory transistor includes the channel element, the first gate electrode layer and the first dielectric layer.

5. The semiconductor structure according to claim 4, wherein An access transistor is included, wherein the access transistor includes the channel element, the second gate electrode layer and the second dielectric layer.

6. The semiconductor structure according to claim 1 or 2, wherein: The substrate portion and the vertical channel portion as a whole do not have a crystal interface therein.

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