Vertical storage structure

Abstract

The present disclosure relates to a vertical memory structure. A memory device is implemented in the vertical memory structure and includes a stack of alternating insulating material layers and wordline material layers, with a pillar group including alternating conductive pillars and insulating pillars disposed through the stack. A data storage structure is disposed on the inner surface of the wordline material layer at the intersection of the insulating pillar and the wordline material layer. A semiconductor channel material is disposed between the insulating pillar and the data storage structure and located at the intersection of the insulating pillar and the wordline material layer. The semiconductor channel material extends around the outer surface of the insulating pillar, contacting adjacent conductive pillars on both sides to provide source / drain terminals.

Description

Technical Field

[0001] The present disclosure relates to a three-dimensional memory, including multiple structures and multiple manufacturing methods for implementing the three-dimensional memory. The three-dimensional memory includes a three-dimensional AND structure device and a three-dimensional NOR structure device. Background Art

[0002] As the critical dimensions of devices in integrated circuits shrink to the limits of conventional memory cell technology, designers have begun to seek techniques for stacking multiple memory cell planes to achieve greater storage capacity and lower bit cost.

[0003] AND and NOR flash memories are random access memories used in high-speed applications. However, the implementation of these devices is limited by density. For NAND flash memories, high density can be achieved using three-dimensional stacked NAND flash memories. However, the lack of random access in NAND memories makes them unsuitable or undesirable for some applications.

[0004] There is a need to provide techniques for three-dimensional stacked integrated circuit memories with higher density, random access, and high operating speed.

[0005] Public content

[0006] The three-dimensional memory technology is described as being suitable for use in AND and NOR memory structures, including flash memory. This summary of the invention describes several representative aspects of the technology as an introduction to the present specification.

[0007] The present disclosure utilizes a vertical memory structure to implement multiple memory devices, including a stack having multiple pillar groups to form a memory block, the stack comprising alternating layers of insulating material and layers of wordline material, the pillar groups comprising alternating conductive pillars and insulating pillars, the pillar groups being disposed through the stack. A particular pillar group comprises at least a first conductive pillar, a first insulating pillar adjacent to the first conductive pillar, and a second conductive pillar adjacent to the first insulating pillar. Multiple data storage structures are disposed on multiple inner surfaces of the multiple wordline material layers at intersections of the first insulating pillar and the multiple wordline material layers. Semiconductor channel material is disposed between the first insulating pillar and the multiple data storage structures and at multiple intersections of the first insulating pillar and the multiple wordline material layers. The semiconductor channel material extends around the outer surface of the first insulating pillar and contacts the first and second conductive pillars to provide source / drain terminals. In various embodiments of the memory structure, the outer surface of the first insulating pillar is arcuate, in the sense of being curved or bent relative to a straight line, in a plane parallel to the multiple wordline material layers.

[0008] In some embodiments, the semiconductor channel material may be discontinuous along the outer surface of the insulating pillar. Furthermore, in some embodiments, the inner surfaces of the plurality of word line layers adjacent to the first insulating pillar are recessed relative to the inner surfaces of the plurality of insulating material layers adjacent to the first insulating pillar to form a plurality of recessed chambers between the plurality of insulating material layers; wherein the semiconductor channel material and the data storage structure are disposed in the recessed chambers.

[0009] Conductive strips covering the stack can serve as pillar select lines or bit line select lines for a plurality of vertical channel transistors, which pass through the conductive strips. The vertical channel transistors contact individual conductive pillars in the pillar group. A plurality of bit line conductors can be disposed in a layer above the vertical channel transistors and contact individual vertical channel transistors in the plurality of vertical channel transistors.

[0010] The conductive pillars from the plurality of pillar groups may be arranged in an array, the array comprising a plurality of distinct sub-arrays. Each distinct sub-array may comprise at least one pillar group from the plurality of pillar groups. The structure may further comprise a plurality of conductive strips disposed in a pillar selection layer overlying the stack, including a corresponding conductive strip corresponding to each distinct sub-array of the array, and a plurality of vertical channel structures corresponding to each distinct sub-array of the array, the vertical channel structures being used for vertical transistors and contacting individual conductive pillars in the distinct sub-arrays through corresponding conductive strips.

[0011] In some embodiments, the structure may include an insulator-filled slot disposed in a space along a plurality of pillar groups comprising alternating conductive and insulating pillars, extending through a pillar selection layer comprising a plurality of conductive strips and through the stack. The slot can be used in a process known as a gate replacement step, in which a sacrificial material is contacted through the slot prior to filling. The filled slot can extend in a direction orthogonal to the plurality of pillar groups comprising alternating conductive and insulating pillars.

[0012] The vertical storage structure may include a conductive layer below the stack, wherein conductive pillars from a plurality of pillar groups comprising alternating conductive pillars and insulating pillars are connected to the conductive layer. In some embodiments, the connection may comprise a PN junction. In some embodiments, a conductor-filled slot is disposed in the gap along the plurality of pillar groups comprising alternating conductive pillars and insulating pillars and extends through the stack to contact the conductive layer below the stack. The filled slot is elongated in a direction perpendicular to the plurality of pillar groups comprising alternating conductive pillars and insulating pillars.

[0013] In addition, the vertical storage structure includes: a stack comprising a plurality of alternating insulating material layers and a plurality of word line material layers; a plurality of different pillar groups comprising alternating conductive pillars and insulating pillars, the plurality of different pillar groups being arranged through the stack, the conductive pillars in the plurality of different pillar groups being arranged in an array and in a plurality of different sub-arrays of the array, each different sub-array comprising at least one different pillar group in the plurality of pillar groups, each different pillar group in the plurality of different pillar groups comprising at least a first conductive pillar, a first insulating pillar adjacent to the first conductive pillar, and a second conductive pillar adjacent to the first insulating pillar; a data storage structure arranged on an inner surface of the word line material layer at an intersection of the insulating pillars in the plurality of different pillar groups and the word line material layer; and a semiconductor channel material between the insulating pillars in the plurality of different pillar groups. and a data storage structure and located at the intersection of the insulating pillars and the word line material layer in the multiple different pillar groups, the semiconductor channel material extends around the outer surface of the insulating pillars in the multiple different pillar groups and contacts the adjacent conductive pillars on both sides of the multiple different pillar groups; a plurality of conductive strips are arranged in the pillar selection layer on the stack, the plurality of conductive strips include a corresponding conductive strip corresponding to each different sub-array of the array, and include a plurality of vertical channel structures corresponding to each different sub-array of the array, the plurality of vertical channel structures pass through the corresponding conductive strips and contact individual conductive pillars in the different sub-arrays; and a plurality of bit line conductors are arranged on the pillar selection layer on the stack, each bit line conductor has a contact structure connected to a vertical channel transistor among the multiple vertical channel transistors in each different sub-array.

[0014] This disclosure also describes various fabrication methods for various embodiments of three-dimensional memory structures.

[0015] The present disclosure describes integrated circuit memory devices that include the three-dimensional memory structures described herein.

[0016] The present disclosure describes various unique integrated circuit structures and fabrication methods that can be used in a variety of structures beyond the memory structures described herein.

[0017] Other aspects and advantages of the present technology can be understood from an understanding of the following drawings, detailed description, and appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 depicts a top plan view of an embodiment of a three-dimensional memory block as described herein, the three-dimensional memory block comprising a plurality of pillar groups, the pillar groups comprising alternating conductive pillars and insulating pillars;

[0019] Figure 2 depicts a cross-sectional view of a stack at a stage in a manufacturing method, the stack comprising alternating layers of insulating material and layers of sacrificial material;

[0020] Figures 3A-3BA cross-sectional view and a three-dimensional perspective view are respectively shown of a stack having a first array of holes at a stage of a manufacturing method;

[0021] Figures 4A-4B depicts a cross-sectional view and a three-dimensional perspective view, respectively, of the stack after forming a storage material and a channel liner in a first hole in the stack;

[0022] Figure 5A A cross-sectional view of the stack after the first hole is filled with an insulator is shown;

[0023] Figure 5B A cross-sectional view of a stacked layer according to an alternative embodiment is shown, in which the bottom layer below the stacked layer is a conductor, such as a p-type semiconductor;

[0024] Figures 6A-6B depicts a cross-sectional view and a three-dimensional perspective view, respectively, of a stack including an array of second holes disposed between the first holes to form a set of alternating first and second holes through the stack;

[0025] Figure 7 To follow Figure 6A A cross-sectional view drawn along the AA hatch line;

[0026] Figure 8 To follow Figure 6A A cross-sectional view drawn along section line BB;

[0027] Figure 9 To follow Figure 6A a cross-sectional view taken along section line AA of FIG, at a later stage of the manufacturing process with formation of a capping layer;

[0028] Figure 10 To follow Figure 6A a cross-sectional view taken along section line BB of , at a later stage of the manufacturing process with the formation of a cover layer;

[0029] Figures 11A-11B They are shown in similar Figure 10 a cross-sectional view and a three-dimensional perspective view of the stack after forming a hole for a vertical bit line selection transistor in the structure;

[0030] Figure 12 To follow Figure 11A a cross-sectional view of the structure depicted along section line AA of FIG, after a later stage in the manufacturing process;

[0031] Figure 13A To follow Figure 11A A cross-sectional view of the laminate as depicted along hatch line BB;

[0032] Figure 13B For an alternative embodiment along the Figure 11AA cross-sectional view of the stacked layer is depicted along the BB section line. In this embodiment, the bottom layer below the stacked layer is a conductor, such as a p-type semiconductor;

[0033] Figure 14 For the pads used in vertical transistors formed on Figure 11A After the structure of Figure 11A a cross-sectional view of the structure drawn along the AA hatching line;

[0034] Figure 15 For the pads used in vertical transistors formed on Figure 11A After the structure of Figure 11A a cross-sectional view of the structure drawn along section line BB;

[0035] Figures 16A-16B They are shown in similar Figure 15 A cross-sectional view and a three-dimensional perspective view of an embodiment of the stack after forming a slit in the structure to replace the sacrificial material;

[0036] Figure 17 for Figure 16A After the sacrificial material in the structure is replaced by the word line material, Figure 16A A cross-sectional view of the laminate as depicted along hatch line AA;

[0037] Figure 18 for Figure 16A After the sacrificial material in the structure is replaced by the word line material, Figure 16A A cross-sectional view of the laminate as depicted along hatch line BB;

[0038] Figure 19 To fill Figure 16A a top plan view of an embodiment of the stack after a slit is provided in the structure to replace the sacrificial material;

[0039] Figures 20A-20B Shown respectively in Figure 19 A cross-sectional view and a three-dimensional perspective view of an embodiment of a stack after a slit is formed through a column selection layer in a structure;

[0040] Figure 21 To fill in with alternative configuration Figure 19 a top plan view of an embodiment of a stack after forming a slit through a column selection layer in a structure;

[0041] Figure 22 To follow Figure 21 A cross-sectional view of the laminate as depicted along hatch line BB;

[0042] Figures 23A-23B Shown respectively in Figure 21 A cross-sectional view and a three-dimensional perspective view of an embodiment of the stack after forming an overlying bit line structure in the structure;

[0043] Figure 24 To follow Figure 23A A cross-sectional view of the laminate as depicted along hatch line AA;

[0044] Figure 25 To follow Figure 23A A cross-sectional view of the laminate as depicted along hatch line BB;

[0045] Figure 26 Draw as Figure 2-25 A flow chart of the manufacturing method shown;

[0046] Figure 27 A top plan view of a stack comprising a second array of holes disposed between the first holes to form a set of alternating first and second holes through the stack, similar to Figure 6A The stacked layers are provided with the second hole being filled with a conductive material;

[0047] Figure 28 To follow Figure 27 A cross-sectional view of the laminate as depicted along hatch line AA;

[0048] Figure 29 To follow Figure 27 A cross-sectional view of the laminate as depicted along hatch line BB;

[0049] Figure 30 Draw along the BB section line Figure 29 a cross-sectional view of the stack after the sacrificial material in the structure is removed;

[0050] Figure 31 The word line material is filled along the BB cross section line. Figure 30 a cross-sectional view of the stack after removing the pores left by the sacrificial material in the structure;

[0051] Figure 32 Draw along the BB section line Figure 31 a cross-sectional view of the laminate after forming a sealing gasket in the open hole in the structure;

[0052] Figure 33 Draw similar Figure 32 A top plan view of a stack comprising alternating insulating and conductive pillars passing through the stack;

[0053] Figure 34 To follow Figure 33 A cross-sectional view of the laminate as depicted along hatch line AA;

[0054] Figure 35 To follow Figure 33 A cross-sectional view of the laminate as depicted along hatch line BB;

[0055] Figure 36 The column selection layer material is formed on Figure 33 After the structure of Figure 33 A cross-sectional view of the laminate as depicted along hatch line AA;

[0056] Figure 37 The column selection layer material is formed on Figure 33 After the structure of Figure 33 A cross-sectional view of the laminate as depicted along hatch line BB;

[0057] Figure 38 depicts a top plan view of the stack after forming a vertical channel structure for a pillar select transistor on a conductive pillar;

[0058] Figure 39 To follow Figure 38 A cross-sectional view of the laminate as depicted along hatch line AA;

[0059] Figure 40 To follow Figure 38 A cross-sectional view of the laminate as depicted along hatch line BB;

[0060] Figure 41 Draw on Figure 38 a top plan view of an embodiment of a stack after forming a slit through a column selection layer in a structure;

[0061] Figure 42 Draw on Figure 41 a top plan view of an embodiment of a stack after forming an overlying bit line in a structure;

[0062] Figure 43 Draw as Figure 27-42 A flow chart of the manufacturing method shown;

[0063] Figure 44 Another manufacturing method is shown in FIG. Figure 3A a cross-sectional view of etching a sacrificial material into a structure to form a recessed chamber;

[0064] Figure 45 Draw on Figure 44 A cross-sectional view of the structure after a storage structure and a semiconductor channel material are formed in the recess;

[0065] Figure 46 Shown filled with insulating material Figure 45 The holes shown are used to form insulating columns;

[0066] Figure 47 Draw on Figure 46 Conductive columns are formed between the insulating columns;

[0067] Figure 48 Draw the form for Figure 47A material for forming a column selection layer on the structure;

[0068] Figure 49 The structure is shown along the cross-sectional line BB after forming a vertical channel structure for a column select transistor, replacing the sacrificial material, and forming an overlying bit line structure;

[0069] Figure 50 Draw as Figures 44-49 A flow chart of an alternative manufacturing method is shown;

[0070] Figures 51-52 For similar Figure 13B After forming the insulating cap layer in the structure, the cross-sectional views along the AA section line and the BB section line are drawn, according to another manufacturing method;

[0071] Figure 53 An embodiment of the present invention is shown in FIG. Figures 51-52 a top plan view of a structure after forming cutouts in the pillar selection layer in the stack of layers and filling the slits with a conductive material to replace the sacrificial material;

[0072] Figure 54A Draw on Figure 53 A top plan view after forming an overlying bit line structure in the structure;

[0073] Figure 54B Draw as Figure 51-54A A flow chart of an alternative manufacturing method is shown;

[0074] Figure 55 A schematic diagram of a three-dimensional memory array that can be manufactured by the method described above is depicted;

[0075] Figure 56 depicts a schematic diagram of a three-dimensional memory array including a lower source line conductor that can be fabricated using the method described above; and

[0076] Figure 57 A simplified block diagram of an integrated circuit memory including a virtual ground three-dimensional memory array according to various embodiments described herein is shown.

[0077] Description of Reference Numerals

[0078] 101-1~101-8,510:Insulation column

[0079] 102-1~102-9,601~604:Conductive columns

[0080] 103-1 to 103-8: Semiconductor channel materials and storage elements

[0081] 105: Three-dimensional storage block

[0082] 110: Hole Array

[0083] 205-209: Insulation material layer

[0084] 210: Hard mask layer

[0085] 208s, 209s, 314s: sidewalls

[0086] 211-215, 311-315: Sacrificial material layer

[0087] 351, 361, 2601-2604, 4401, 4402: holes

[0088] 411, 421: Multilayer dielectric charge storage structures

[0089] 412, 422, 3713, 3714, 4903: Semiconductor channel layer

[0090] 1011, 1012: Insulation layer

[0091] 1020: Sacrificial layer

[0092] 1101~1104, 3701~3704, 4905: pads

[0093] 1210, 1220, 1230, 1310, 3801-3804: Column selection transistors

[0094] 1211: Gate oxide material layer

[0095] 1212: Channel material layer

[0096] 1301, 6332, 6333: PN junction

[0097] 1410: Covering

[0098] 1601, 1602: Slit

[0099] 1701, 1702: Insulators

[0100] 1815: Pillar selection gate layer

[0101] 2010, 4010: Incision

[0102] 2111~2115,3011~3015:Word line layer

[0103] 2151: High dielectric constant lining

[0104] 2201, 2202, 2204, 2206, 4201, 4202, 4204, 4206, 4910: bit lines

[0105] 2205, 2207, 2610-2613, 4601, 4602: Insulation columns

[0106] 2213, 2215: Vertical conductor structure

[0107] 2302, 2304, 2306, 4908: Bit line contact structure

[0108] 2310: Interlayer dielectric

[0109] 2620: Porosity

[0110] 2701-2710, 4301-4312, 5001-5012, 5401-5410: Steps

[0111] 3025: Insulated sidewalls

[0112] 3201~3204,4211,4212,4214:Conductive pillars

[0113] 3520: word line material layer

[0114] 3723, 3724, 4902: Gate oxide layer

[0115] 4411, 4412: Alcove

[0116] 4510, 4512: Silicon oxide layer

[0117] 4511, 4513: Channel

[0118] 4520: Area

[0119] 4901: Vertical transistor structure

[0120] 4904: Core

[0121] 4911, 5120: Word line materials

[0122] 4920, 4921: Interlayer dielectric

[0123] 5205, 6330: Source line conductor

[0124] 5301, 5302: Conductor filling slots

[0125] 5501, 5502: Source line bias line

[0126] 5700: Integrated Circuits

[0127] 5750: Bit Line Decoder

[0128] 5752: Circuit

[0129] 5755: bit line

[0130] 5760: 3D Virtual Ground Storage Array

[0131] 5763: BLT and word line decoder

[0132] 5764: Word Line

[0133] 5765: Bus

[0134] 5766: Block

[0135] 5767: Data bus

[0136] 5768: Block

[0137] 5769: Controller

[0138] 5771: Data input line

[0139] 5772: Data output line

[0140] 5774: Other circuits

[0141] 6210~6214, 6601~6603: conductive columns

[0142] 6222, 6224: Insulation / channel column

[0143] 6250: Conductive column select transistor

[0144] 6251: Layered

[0145] AA, BB: hatching

[0146] BL1~BL5: bit lines

[0147] BLT1, BLTN: bit line selection line

[0148] WL1~WL8: word lines

[0149] X, Y, Z: direction DETAILED DESCRIPTION

[0150] Reference Figure 1-57 A detailed description of several embodiments of the present technology is provided.

[0151] The technology described in this disclosure includes multiple structures and multiple manufacturing methods that can be used to realize three-dimensional memory devices, including Figures 55-56 A three-dimensional storage device in the form of a simplified circuit diagram is shown.

[0152] Please refer to Figure 55, the three-dimensional memory array shown includes multiple different sub-arrays on different slices in the simplified diagram. In this example, each sub-array is connected to a set of bit lines BL1-BL5 through bit line select transistors, and the bit line select transistors are controlled by a common bit line select line. Thus, in this example, Figure 56 The simplified diagram in shows N different sub-arrays, which are composed of multiple vertical slices of a three-dimensional block and are selected by bit line selection lines BLT1-BLTN.

[0153] exist Figure 55 In the simplified diagram of FIG, each distinct subarray is composed of a set of conductive pillars 6210, 6211, 6212, 6213, and 6214 interleaved with insulating / channel pillars, schematically represented by vertical dashed lines (e.g., insulating / channel pillars 6222 and 6224). As described in detail herein, semiconductor channels and memory elements are disposed around the outer surfaces of the insulating / channel pillars and at the intersections of the wordline layers (e.g., wordlines WL1-WL8) and the insulating / channel pillars. The semiconductor channels contact the conductive pillars on opposite sides to form a stack of memory cell transistors, such as stack 6251. A conductive pillar select transistor 6250, controlled by a bitline select line BLTN, connects the vertical conductive pillars forming the distinct subarray to the corresponding bitline overlying the stack.

[0154] For example Figure 55 The illustrated memory array can operate in a virtual ground configuration in which bit lines BL1-BL5 alternately function as source-side conductors and drain-side conductors for memory cells in a memory cell stack. Thus, bit line BL2 and conductive pillar 6211 coupled to bit line BL2 can function as both a source-side conductor for memory cells in stack 6251 and a drain-side conductor for memory cells in the left stack, which is located between conductive pillars 6211 and 6212. The left stack, which is located between conductive pillars 6210 and 6211, can function as both a source-side conductor for memory cells in stack 6251 and a drain-side conductor for memory cells in the left stack. Figure 55 The circuit may also be implemented as described in U.S. patent application Ser. No. 16 / 394,363, filed on April 25, 2019 (U.S. Patent No. 10,910,393), entitled “3D NOR MEMORY HAVING VERTICAL SOURCE AND DRAIN STRUCTURES,” which has the same inventors as the present case and is commonly owned at the time of invention and is now, and which is incorporated herein by reference in its entirety.

[0155] Figure 56 A circuit diagram for another memory array structure is shown, similar to Figure 55The memory array structure shown (similar elements are not described here) is further illustrated with the addition of a lower source line conductor 6330. Source line conductor 6330 is connected to a conductive pillar (e.g., 6211) via a PN junction (e.g., 6332, 6333). In this manner, lower source line conductor 6330 can be used to bias the conductive pillar during some memory operations (e.g., the erase operation described herein), while being isolated from the conductive pillar during other memory operations (e.g., read and program operations).

[0156] The integrated circuit storage structure used to implement the storage array can be, for example, Figures 55-56 The schematic diagram is shown in the figure and can be manufactured in multiple steps. Figure 1-54B Let's understand some of these steps.

[0157] Figure 1 A top plan view of an embodiment of a subassembly of a three-dimensional memory block 105 at an intermediate stage of fabrication is shown, comprising a plurality of pillar groups comprising alternating conductive pillars and insulating pillars. The three-dimensional memory block 105 comprises a stack of alternating insulating material layers and wordline material layers. In the depicted three-dimensional memory block 105, four pillar groups are arranged through the stack, each comprising alternating conductive pillars (in this example, conductive pillars 102-1 through 102-9) and insulating pillars (101-1 through 101-8). The insulating pillars can have a columnar shape with vertical sidewalls within the limits of the process being used. The pillar shape can be a cylinder, an elliptical cylinder, or other shape suitable for the fabrication method and layout pattern being used. In the embodiment depicted herein, the insulating pillars in the pillar groups have an arcuate outer surface in a plane parallel to the wordline material layers. Similarly, the conductive pillars can have a columnar shape with vertical sidewalls within the limits of the process being used. The pillar shape can be a cylinder, an elliptical cylinder, or other shape suitable for the fabrication method and layout pattern being used. In the embodiment described herein, the conductive pillars are elliptical cylinders having their major axes aligned with the direction of the pillar groups, which is the row direction or X direction.

[0158] This results in a memory cell structure that spans the insulating pillar at the wordline level, with source / drain terminals on adjacent conductive pillars on each side.

[0159] like Figure 1 As shown, a specific different pillar group among the multiple different pillar groups includes N+1 conductive pillars (102-1 to 102-9 in this example) and N insulating pillars (101-1 to 101-8), where N is equal to 8 in this figure, so that the specific different pillar group includes N memory cell stacks.

[0160] Figure 2 Shown are subassemblies at an early stage in the method of manufacturing a three-dimensional memory block. Figure 2The result of forming a block is shown. The block includes a stack of alternating layers of insulating material and sacrificial material. The sacrificial material will be replaced by wordline material later in the manufacturing process. In this example, the alternating insulating material layers are represented by symbols 205 to 209, and the alternating sacrificial material layers are represented by symbols 211 to 215. The insulating material can be implemented using, for example, silicon oxide or other suitable insulators, while the sacrificial material can be implemented using silicon nitride, a silicon germanium compound, or other materials that can be etched using highly selective etching chemistry to replace the sacrificial material with the wordline material without removing the insulating material. In this example, a hard mask layer 210 is formed on top of the stack for use in later patterning stages.

[0161] Figure 3A The subassembly is shown at a later stage, after using a hard mask to define the pattern for the hole array and etching holes 351 , 361 through the stack, which holes 351 , 361 will be used to form insulating pillars. Figure 3B is a perspective view showing a (representative) layout of a hole array 110 that may be used through the laminate, including holes 351 , 361 .

[0162] Figure 4Ais a cross-sectional view along the row or X-direction, depicting the subassembly at a later stage, after a series of steps including depositing a memory structure at least at the wordline level. In this example, the memory structure is a multilayer dielectric charge storage structure 411, 421, which is formed to line the sidewalls of holes 351, 361. Exemplary multilayer dielectric charge storage structures can be implemented using so-called SONOS technology and bandgap engineered SONOS technology, where the memory structure includes a dielectric tunneling layer, a dielectric charge trapping layer, and a dielectric barrier layer. In some embodiments, the tunneling layer can be implemented using one or more silicon oxide and silicon nitride films. The dielectric charge trapping layer can be implemented using silicon nitride or other materials. The dielectric barrier layer can be implemented using one or more layers including silicon oxide or other insulators having a higher dielectric constant than silicon oxide. Abbreviated designations such as ONO, ONONO, and ONONONO are sometimes used to represent these dielectric charge trapping structures. In other embodiments, a ferroelectric memory structure may be used. The ferroelectric memory structure may include a ferroelectric material such as hafnium oxide. For example, the hafnium oxide includes silicon-doped hafnium oxide, aluminum-doped hafnium oxide, yttrium-doped hafnium oxide, gadolinium-doped hafnium oxide, lanthanum-doped hafnium oxide, zirconium-doped hafnium oxide, or other materials.

[0163] In addition, semiconductor channel layers 412 and 422 are formed on the multi-layer dielectric charge storage structures 411 and 421 .

[0164] The steps of forming the structure may include first performing a blanket deposition of a multilayer dielectric charge storage structure, followed by a blanket deposition of a semiconductor channel material on the multilayer dielectric charge storage structure. An anisotropic spacer etch is then applied to remove material from the bottom of the hole and the top of the stack, leaving a Figure 4A The sidewall structure shown is anisotropically spacer etched using, for example, reactive ion etch chemistry. Figure 4B For similar Figure 3B 3D perspective view showing that the hole is lined with a multi-layer charge storage structure and a semiconductor channel layer (eg, hole 361 is lined with a multi-layer dielectric charge storage structure 421 and a semiconductor channel layer 422).

[0165] Figure 5A The structure is shown after the steps of filling the holes 351 and 361 with an insulator and flattening the surface. The insulator is, for example, silicon oxide. The flattening step is, for example, chemical mechanical polishing. Figure 5A As shown, the insulating pillars 510 are formed in the holes 351 , 361 .

[0166] Figure 5B The structure is shown in an alternative embodiment with an underlying conductive layer. Figure 5B In the figure, the lower conductive layer is the source line conductor 5205 arranged below the stack. Figure 5B Neutralization Figure 5A The same symbols represent similar structures.This alternative embodiment will be described in more detail below.

[0167] Figure 6A A top plan view of an embodiment of a three-dimensional memory block 105 is shown at an intermediate manufacturing stage. After etching the second hole array, a conductive material is deposited in the second hole array to form conductive pillars (e.g., 601, 602, 603, 604) to form a plurality of pillar groups comprising alternating conductive pillars and insulating pillars (e.g., 510). In one embodiment, the conductive pillars can be formed by depositing N+ polysilicon in the second hole array, followed by a planarization step such as chemical mechanical polishing.

[0168] In the illustrated embodiment, there are four pillar groups comprising alternating conductive and insulating pillars, extending along the row direction. To facilitate the high-density configuration discussed below, each pillar group is offset from adjacent rows. As described above, the insulating pillars comprise a semiconductor channel layer and a memory structure layer. The conductive pillars contact the semiconductor channel layer on adjacent insulating pillars or multiple insulating pillars to form source / drain terminals for the memory cells at the intersections of the wordline layers.

[0169] Figure 6B is a perspective view of a stack showing an array of holes disposed between insulating pillars (eg, 510) to form conductive pillars (eg, 604).

[0170] Figure 7 The cross-section line AA is drawn along the row direction or the X direction. Figure 6A As shown in the figure, conductive pillars 601, 602, and 603 and insulating pillars are arranged in an alternating manner. Because this cross-section is taken along its centerline, the semiconductor channel layer extending around the outer surfaces of the insulating pillars and the storage structure layer do not intersect in the cross-sectional view of this embodiment.

[0171] Figure 8 The cross-section line BB is drawn along the row direction or the Y direction. Figure 6A . As shown, insulating pillars 510 are arranged in separate rows along the columns. The middle row along the columns includes conductive pillars 604. In the sacrificial material layers 211-215, the sacrificial material extends around the insulating and conductive pillars at the locations where word lines will be formed after the sacrificial material is replaced.

[0172] Figure 9 For similar Figure 7 10. A cross-sectional view of the stack of FIG. 10 is shown along section line AA at a later stage after insulating layer 1011, sacrificial layer 1020, and insulating layer 1012 are formed on top of the stack to form the pillar select transistor structure. The layers at this location are collectively referred to as the pillar select layer on the stack.

[0173] Figure 10 for peace Figure 9 Cross-section at the same stage, along Figure 7 The cross-section line BB in FIG. 1 shows the structure after the insulating layer 1011, the sacrificial layer 1020 and the insulating layer 1012 are formed at the column select transistor level. The sacrificial layer 1020 and the insulating layer 1011 can be made of the same material as the alternating sacrificial and insulating material layers in the stack.

[0174] Figure 11A A top plan view of an embodiment of a three-dimensional memory block 105 is shown at an intermediate manufacturing stage, after structures for implementing the pillar select transistors are formed on the conductive pillars. Figure 11A As shown in the layout of FIG, pads 1101, 1102, 1103, and 1104 are formed on top of the vertical channel structure of the column selection transistor, and the column selection transistor is disposed on top of the conductive column. Figure 11B A three-dimensional perspective view showing the pad array exposed on the top of the stack.

[0175] Figure 12 To follow Figure 11A The structure shown is a cross-sectional view taken along the line AA in the row direction at a later stage. The steps for forming the column selection transistor include etching an array of holes above the conductive column, such as Figure 11BAs shown, the holes expose the tops of the conductive pillars, such as conductive pillars 601, 602, and 603. Next, a gate oxide material layer (such as 1211) and a channel material layer (such as 1212) are disposed on the sides of the holes, for example, by performing a blanket deposition of the material and then performing an anisotropic spacer etch to remove material from the bottom of the hole and the top of the structure, so that the gate oxide material layer and the channel material layer are disposed on the sides of the hole. The gate oxide material is, for example, silicon oxide, and the channel material is, for example, polysilicon. After forming the gate oxide material layer and the channel material layer, the holes are filled with silicon oxide, other insulators, or other suitable materials. Then, an etch-back step can be performed to remove material from the top of the hole, leaving a recess in the upper surface. Next, conductive polysilicon or other conductor can be deposited and planarized to form pads 1101, 1102, and 1103. The conductive polysilicon is, for example, N+ type polysilicon. This step forms a pillar select transistor structure having source / drain terminals located on corresponding conductive pillars and pads, and having a vertical channel extending between the conductive pillars and pads. As discussed further below, the sacrificial layer 1020 is replaced with wordline material.

[0176] Figure 13A To follow Figure 11A The cross-sectional view of the structure shown is shown along the column direction along the section line BB. As shown, a conductive pillar 604 is disposed in one column of the array and between insulating pillars 510 in adjacent columns. Structures for pillar select transistors (e.g., 1210) are disposed above the conductive pillars 604. Structures for the pillar select transistors are not disposed above the insulating pillars 510.

[0177] Figure 13B The cross-section line BB is drawn along the row direction. Figure 11A The cross-sectional view of the structure shown shows an alternative embodiment in which a source line conductor 5205, such as a p-type conductor layer, is disposed below the stack. In this structure, the conductive pillar 604 can be n-type or N+ type polysilicon, and the source line conductor 5205 can be a p-type diffusion in the semiconductor substrate or other p-type semiconductor body. This results in a PN junction 1301 being formed at the intersection of the conductive pillar 604 and the source line conductor 5205, such as Figure 56 Knot 6332 shown.

[0178] Figure 14 and Figure 15 are cross-sectional views respectively drawn along the section line AA and the section line BB, respectively showing the cap layer 1410 formed on the column selection transistors 1210, 1220, and 1230. Figure 12 and Figure 13A The capping layer 1410 may be a silicon oxide layer or other material layer that can serve as a hard mask or other type of protective layer for later processing steps.

[0179] Figure 16A A top plan view of an embodiment of a three-dimensional memory block 105 is shown at an intermediate fabrication stage (cap layer 1410 is shown as transparent), after forming slots 1601, 1602 through the stack to be used to replace the sacrificial material. Figure 16B is a three-dimensional perspective view showing the array with the slots exposed through the cover layer 1410 at the top of the stack.

[0180] In this example, slits 1601 and 1602 are disposed between eight insulating pillars in the row direction and extend in the column direction for a pillar group comprising alternating conductive pillars and insulating pillars. The spacing length can be defined, for example, by a parameter M, where the spacing length, which is a measure of the number of insulating pillars, can be equal to 2M. The parameter M can be any positive integer, including one, two, three, or four. In the example described, M = 3. In this example, the length of the slits in the column direction is equal to approximately four columns. Again, the length of the slits in the column direction can be selected based on the specific embodiment.

[0181] Figure 17 and Figure 18 To follow Figure 16A The cross-sectional views indicated by the section lines AA and BB in the structure of FIG. 1 respectively show the results of replacing the sacrificial materials in the word line layer and the column selection transistor layer with the word line material.

[0182] The replacement of the sacrificial material can be achieved by performing an etching step that removes the exposed sacrificial material (i.e., sacrificial material layers 211-215) in the wordline layer and the pillar select layer through the slits 1601 and 1602, leaving the insulating material in layers 205-210 and 1011 and 1012. Next, the wordline material is deposited in the voids left by the removal of the sacrificial material. Thus, as shown in Figures 17-18, the wordline layer (2111-2115) and the pillar select gate layer (1815) are each represented by cross-hatched lines resembling vertical conductive pillars. It should be noted that the material of the wordline and pillar select gate layers (in this example, substantially tungsten) may be different from the material used for the vertical conductive pillars (N+ polysilicon, as described above).

[0183] In some embodiments, prior to depositing the wordline material, a high-k liner (2151) may be deposited in the pores. The high-k liner has, for example, a higher dielectric constant than silicon dioxide or a higher dielectric constant than the insulating material used in the alternating layers 205-209. This high-k liner 2151 may comprise aluminum oxide, hafnium oxide, zirconium oxide, or other high-k (high-k, meaning a dielectric constant greater than 7) material that can serve as a blocking layer or portion of a blocking layer for the dielectric charge trapping structure formed to line the insulating pillars. This results in a high-k dielectric between the conductive pillars in the pillar group and the wordline material in the wordline material layer. The high-k material also electrically insulates the wordline layer (e.g., 2111) from the conductive pillars (e.g., 604). Furthermore, in other embodiments, additional materials for the dielectric charge-trapping memory structure can be deposited in this manner, such as a charge-trapping layer comprising silicon nitride and a barrier layer comprising one or more insulating layers (e.g., high-k aluminum oxide, hafnium oxide, or zirconium oxide). In this case, after forming the holes for the insulating pillars, only the portion of the memory structure not deposited during the gate replacement process needs to be applied to the sidewalls of the openings. In some embodiments, the wordline material is formed by first depositing titanium nitride or another suitable adhesion / barrier liner in the holes (optionally covering the aforementioned liner), followed by depositing tungsten through the slots. After the material is deposited in the holes, the tungsten / titanium nitride material is then etched back to remove it from the slots, thereby breaking the conductive path between the wordline layer and the pillar select layer in the array region.

[0184] Figure 19 A top plan view is shown after the slots are filled with insulating material. In this embodiment, after etching back, the slots are filled with insulators 1701 and 1702.

[0185] Figure 20A A top plan view of a shallow trench stopping at the top wordline layer of the stack is shown after forming a cut 2010 through the pillar select gate layer. Figure 20B is a three-dimensional perspective view showing shallow cuts 2010 used to form different column select gates (also called bit line transistor (BLT) lines) used to select different sub-arrays of the memory array as described above. Figure 20A In the example shown, the cutouts 2010 are provided between pillar groups comprising alternating insulating and conductive pillars.

[0186] Figure 21 The subassembly is shown with an alternative location of the cutout 2010 disposed above the dummy pillar set including the dummy insulating pillar and the dummy conductive pillar. Figure 21 A stack having an array of pillars formed in this manner may reduce variations in pillar structure along the edges between cuts and may allow for a tighter array layout.

[0187] Figure 22 To follow Figure 21 The cross-sectional view shown along the section line BB in the column direction of FIG. 1 shows that the cutout 2010 forms a gap separating the pillar select gate layer 1815 into a plurality of conductive strips, with a corresponding conductive strip of the plurality of conductive strips forming each different sub-array of the corresponding array. Therefore, the conductive pillars in the different sub-arrays are contacted through the plurality of vertical channel structures corresponding to the conductive strips of the different sub-arrays.

[0188] Figure 23A A top plan view of the structure after the step of forming overlying bit lines (e.g., 2201, 2202, 2204, and 2206) is shown. This step may include depositing an interlayer dielectric 2310 over the column select transistor pads, forming bitline contact plugs through the interlayer dielectric 2310, and then forming and patterning metal in the bitline layer to form the bitlines. Multiple bitlines are assembled so that they contact at most one vertical conductor structure in each distinct subarray. Thus, bitline 2201 contacts vertical conductor structure 2203 in the subarray above cutout 2010 at the top and spans insulating pillar 2207 above cutout 2010 and insulating pillar 2205 below cutout 2010 at the bottom. Bitline 2201 extends to a vertical conductor structure (not shown) below insulating pillar 2205 and below cutout 2010 at the bottom. Furthermore, the bit line 2202 contacts the vertical conductive structure 2213 above the cutout 2010 and the vertical conductive structure 2215 below the cutout 2010 . Figure 23B The figure is a three-dimensional perspective view of the structure after the bit lines are formed. In this example, the bit lines are arranged along the column direction orthogonal to the row direction, and a column group including alternating conductive columns and insulating columns is formed along the row direction.

[0189] Figure 24 To follow Figure 23A , after the bit lines are formed. As shown, bit line contact structures 2302, 2304, 2306 are formed between pads of vertical transistor structures (e.g., column select transistors 1210, 1220, 1230) and the overlying bit lines (2202, 2204, 2206).

[0190] Figure 25 To follow Figure 23A , showing a gap or cut 2010 forming a different pillar select gate structure for each different sub-array. Although not shown, in some embodiments, the cut 2010 can be cut through the pillar select transistor structure having the pillar select transistors for the active conductive pillars in the array.

[0191] The layout of the gaps or cutouts 2010 in the column selection layer corresponds to the configuration of the different sub-arrays in the array. The cutouts 2010 can be defined between each row, in which case each different sub-array includes only one column group comprising alternating conductive columns and insulating columns. The cutouts 2010 can be defined between pairs of rows, where each different sub-array includes two column groups comprising alternating conductive columns and insulating columns. The row spacing (spacing) between the gaps can be set to any number. For example, the parameter P can be used to define that there are 2P column groups comprising alternating conductive columns and insulating columns in each different sub-array, where P can be any integer, such as, two, three, etc. When each different sub-array has a large number of column groups comprising alternating conductive columns and insulating columns, a higher bit line density than the column density may be required to produce a sufficient number of contact structures.

[0192] Figure 26 Drawing example as above Figure 2-25 A flow chart of a manufacturing method is described. As shown in the flow chart, the steps begin by forming a stack comprising alternating layers of sacrificial material and layers of insulating material on a substrate (step 2701). The substrate may include an integrated circuit substrate, which in some cases includes logic circuitry adjacent to and below the stack, the logic circuitry being used to implement peripheral circuitry for a memory device. After the stack is formed, holes are etched in a selected pattern, the holes are lined with material of a data storage structure (e.g., one or more layers of a multilayer dielectric charge storage structure), and then a semiconductor channel material is formed over the material of the data storage structure to form an array of insulating pillars through the stack (step 2702). The next step in the flow chart is to form an array of conductive pillars through the stack, the conductive pillars being arranged in a pattern to form a block of the stack comprising layers of insulating material and sacrificial material, with a plurality of pillar groups extending in a row direction within the block, the pillar groups comprising alternating insulating pillars and conductive pillars extending through the stack (step 2703).

[0193] Next in the flow chart, the method includes forming a sacrificial layer over the stack, separated by insulating layers above and below the sacrificial layer, for forming a pillar select transistor (step 2704). A plurality of holes are formed through the sacrificial layer over the stack, aligned with the conductive pillars. A gate dielectric and a semiconductor channel material are lined on the sidewalls of the holes, such that the semiconductor channel material contacts the corresponding conductive pillars (step 2705). Furthermore, pads may be formed on top of the holes, contacting the semiconductor channel material to provide a current path from the corresponding conductive pillars to the pads.

[0194] exist Figure 26In some embodiments, a plurality of slits are etched through the stack and the sacrificial layer above the stack. The slits are spaced apart along the row direction, for example, between each group of eight insulating pillars and nine conductive pillars in the pillar group, and extend across multiple pillar groups along the column direction, for example, across four or eight pillar groups. The slits expose the sacrificial material in the stack and the sacrificial material in the sacrificial layer above the stack (step 2706). After exposing the sacrificial material, the sacrificial material is removed through the slits, leaving apertures at the locations of the word lines and pillar select lines of the memory array implemented in this block (step 2707). Wordline material, such as tungsten, is then deposited in the apertures left by the removal of the sacrificial material. In some embodiments, a high-k dielectric liner is formed before depositing the wordline material, or one or more multi-layer charge storage structures are formed at the intersections of the wordlines and insulating pillars (step 2708). After depositing the wordline material, the remaining material within the slits is removed, and in this embodiment, the slits are filled with an insulator (step 2709).

[0195] Then, bit line construction and other back end of line operations may be performed to complete the device (step 2710).

[0196] Generally speaking, Figure 26 An example method for fabricating a vertical memory structure is illustrated, including forming a block comprising a stack comprising alternating insulating material layers and wordline material layers, and forming a plurality of distinct pillar groups comprising alternating conductive pillars and insulating pillars arranged in an array and extending through the stack. Furthermore, the method includes forming a data storage structure on the inner surface of the wordline material layer at the intersections of the insulating pillars and the wordline material layer. The method also includes forming a semiconductor channel material between the insulating pillars and the data storage structure at the intersections of the insulating pillars and the wordline material layer. The semiconductor channel material can be an arcuate layer that extends around the arcuate outer surface of the insulating pillars and contacts adjacent conductive pillars on both sides, such as with ohmic contacts, to establish source / drain terminals at the junctions. Furthermore, the method results in forming a plurality of conductive strips in a pillar selection layer over the stack. For each distinct subarray of the array, the plurality of conductive strips includes a corresponding conductive strip serving as a gate for the plurality of vertical channel structures of the distinct subarray. Furthermore, the method includes forming a bitline conductor on the pillar selection layer above the stack. In the embodiments described herein, each bitline conductor has a contact structure connected to a vertical channel transistor in each different sub-array of the array in the stack.

[0197] The integrated circuit storage structure used to realize the storage array can be Figures 55-56 The schematic diagram shows that it can also be manufactured in multiple steps, which can be referred to Figure 27-42 Let's understand some of these steps. Figure 27-42 The various stages of the manufacturing method of an alternative embodiment are shown, wherein no slits are used instead of sacrificial material. Figure 6A In the aforementioned stage, in this manufacturing method, a hole array is formed for forming conductive pillars disposed in a plurality of pillar groups. Figure 27 So similar to Figure 6A , the difference is Figure 27 The holes are not filled with conductive material.

[0198] Figure 27 A top plan view of an embodiment of a three-dimensional memory block is shown at an intermediate manufacturing stage, after etching a second array of holes (e.g., 2601, 2602, 2603, 2604), wherein conductive material will be deposited at a later stage to form a plurality of conductive pillars in a pillar group comprising alternating conductive pillars and insulating pillars.

[0199] Figure 28 The cross-section line AA is drawn along the row direction or the X direction. Figure 27 A cross-sectional view of the structure is shown. As shown, holes 2601, 2602, and 2603 and insulating pillars 2612 and 2613 are arranged in an alternating pattern. Because this cross-section is taken along its centerline, the semiconductor channel layer extending around the outer surfaces of the insulating pillars and the memory structure layer do not intersect in this embodiment's cross-sectional view.

[0200] Figure 29 The cross-section line BB is drawn along the row direction or the Y direction. Figure 27 A cross-sectional view of the structure is shown. As shown, insulating pillars 2610 and 2611 are arranged in separate rows along the columns. The middle row along the columns contains holes 2604. In the sacrificial material layers 311-315, the sacrificial material extends around the insulating pillars and holes for the conductive pillars at the locations where word lines will be formed after the sacrificial material is replaced.

[0201] Figure 30 Draw a pair Figure 29After the subassembly shown in the cross-sectional view undergoes the step of removing the sacrificial material, the sacrificial material is removed by removing the holes (e.g., 2604) that will be used to form the conductive pillars. For this embodiment, the sacrificial material is preferably made of, for example, silicon germanium, which allows for easier selective etching to remove the sacrificial material between the insulating pillars, compared to silicon nitride in some embodiments. As shown, the removal of the sacrificial material forms voids (e.g., 2620) between the insulating material layers, into which wordline material can be deposited. In this embodiment, additional slits disposed in the spaces along the pillars comprising alternating insulating and conductive pillars are optional and, in some embodiments, can be omitted to increase the density of the array layout. As described, material of the data storage structure, or in some embodiments, portions of the multi-layered data storage structure, extending around the outer surface of the insulating pillars (e.g., 2610) is exposed within the voids.

[0202] Figure 31 Draw on Figure 30 The subassembly follows the step of filling the pores with a wordline material, such as a titanium nitride liner with a tungsten filler, to form wordline layers 3011-3015 in the structure. As previously mentioned, in some embodiments, filling the pores may include depositing a high-k dielectric film or other dielectric film, which may be part of the data storage structure in the final product. This step involves depositing the material and then etching back the material to reopen the pores (e.g., 2604).

[0203] Figure 32 Draw something similar to Figure 31 After performing the steps of forming a cavity in the titanium nitride / tungsten fill and then forming oxide or other insulating sidewalls (e.g., 3025) in the cavity to insulate the word line structure from the conductive pillar to be formed in the hole 2604. This can be achieved by filling the hole 2604 with silicon oxide or other suitable material and then anisotropically etching back the fill. Figure 32 Thus, the semiconductor channel layers (412, 422) are exposed and may protrude above the top of the stack.

[0204] Figure 33 Shown as filled with conductive material Figure 31 The holes shown are formed with conductive pillars (eg 3201 , 3202 , 3203 , 3204 ) in the spaces of the holes, followed by a planarization step to flatten the surface, and the resulting structure is a top plan view. The conductive material is, for example, n-type polysilicon.

[0205] Figure 34 The cross-section line AA is drawn along the row direction or the X direction. Figure 33As shown in the figure, the conductive pillars (e.g., 3201, 3202, 3203) and the insulating pillars 2612, 2613 are arranged in an alternating manner. Because this cross-section is taken along its centerline, the semiconductor channel layer extending around the outer surfaces of the insulating pillars and the memory structure layer do not intersect in the cross-sectional view of this embodiment.

[0206] Figure 35 The cross-section line BB is drawn along the row direction or the Y direction. Figure 33 A cross-sectional view of the structure of FIG. As shown, insulating pillars 2610 and 2611 are arranged in separate rows along the columns. The middle row along the columns includes a conductive pillar 3204. Wordline layers 3011-3015 extend around the insulating and conductive pillars and are separated by insulating sidewalls (e.g., 3025) in the location of the wordline material. Insulating sidewalls 3025 insulate conductive pillars 3204 from wordline layers 3011-3015. However, conductive pillars 3204 are physically connected to semiconductor channel layers 412 and 422.

[0207] Figure 36 The cross-section line AA is drawn along the row direction. Figure 34 1 is a cross-sectional view of the material forming the pillar selection layer of the structure in FIG. This material will be used to form the pillar selection transistor. The material includes an insulating layer 1011, a wordline material layer 3520, and a top insulating layer 1012. The insulating layer 1011 may be, for example, silicon oxide or other suitable interlayer insulator material. The wordline material layer 3520 may be, for example, tungsten or other suitable wordline material. The insulating layer 1012 may be made of the same material as the insulating layer 1011. These layers may be deposited in a blanket manner on top of the stack. A plurality of pillar groups comprising alternating conductive pillars (e.g., 3201, 3202, 3203) and insulating pillars (e.g., 2612, 2613) are formed in the stack.

[0208] Figure 37 For similar Figure 35 The cross-sectional view is shown along the section line BB in the row direction. Figure 37Also shown are materials for the pillar selection layers of the structure, which will be used to form the pillar selection transistors. These materials include an insulating layer 1011, a wordline material layer 3520, and a top insulating layer 1012. The insulating layer 1011 may be, for example, silicon oxide or other suitable interlayer insulators, and the wordline material layer 3520 may be, for example, tungsten or other suitable wordline materials. The insulating layer 1012 may be made of the same material as the insulating layer 1011. As shown, the insulating pillars (2610, 2611) are lined with storage structures (e.g., multi-layer dielectric charge storage structures 411, 421) and semiconductor channel layers 412, 422. The storage structures (e.g., multi-layer dielectric charge storage structures 411, 421) and semiconductor channel layers 412, 422 extend around the arcuate outer surfaces of the insulating pillars that contact the wordline layers 3011-3015. Furthermore, insulating sidewalls 3025 (eg, oxide sidewalls) isolate the word line layers 3011 - 30115 from the vertical conductive pillars (eg, 3204 ).

[0209] Figure 38 is a top plan view of the stack, illustrating the top pads (e.g., 3701, 3702, 3703, 3704) of vertical column select transistors formed in the column select layer above corresponding conductive columns (e.g., 3201, 3202, 3203, 3204). In this figure, the word line material layer 3520 is shown transparent to show the alternating conductive and insulating columns.

[0210] Figure 39 The cross section line AA is drawn along the row direction. Figure 38 A cross-sectional view of a structure after a step including forming a hole extending to the top of the corresponding conductive column. After the hole is formed, the gate oxide material and the semiconductor channel material are then deposited, followed by a reactive ion etching process or other anisotropic etching process to form the sidewalls, leaving the gate oxide material and the semiconductor channel material on the sidewalls. The remaining volume of the hole is then filled with an insulator such as silicon dioxide and planarized. An etch back process is performed to form a recess at the top, which is then filled with conductive polysilicon (such as N+ type polysilicon or other suitable conductor) and planarized by chemical mechanical polishing or other methods to form a landing pad on the top of the vertical column select transistor. Figure 39 As shown, pillar select transistors 3801, 3802, and 3803 are formed for corresponding vertical conductive pillars 3201, 3202, and 3203. Each vertical pillar select transistor includes a gate oxide layer (e.g., 3723) that contacts a word line material layer (3520) that will serve as a pillar select gate. In addition, each vertical pillar select transistor includes a semiconductor channel layer (e.g., 3713) that extends around an insulator and provides a transistor channel extending between the vertical conductive pillar (e.g., 3203) and the pad (e.g., 3703).

[0211] Figure 40 The cross-section line BB is drawn along the row direction. Figure 38 As shown in this example, a vertical column select transistor 3804 having a pad 3704 is disposed on a vertical conductive column 3204. The vertical column select transistor 3804 includes a gate oxide layer 3724 and a semiconductor channel layer 3714 extending between the conductive column 3204 and the pad 3704.

[0212] Figure 41 A top plan view of the structure is shown after forming a cut 4010 through the column select gate layer, forming a shallow trench that stops before the top wordline layer of the stack. The cut 4010 is used to form different column select gates (also called bitline transistor (BLT) gates) that are used to select different sub-arrays of the memory array as described above. Figure 41 In the example shown, the cutout 4010 is provided above the dummy column group including the dummy insulating column and the dummy conductive column. Figure 21 .

[0213] Thus, a plurality of vertical channel transistors are provided, which are controlled by a different column select gate for each different sub-array.

[0214] Figure 42 For Figure 41 A top plan view of the structure after forming overlying bit lines in the structure. Formation of the structure may involve forming an interlayer dielectric over the pads of the vertical channel transistors, followed by etching an array of bitline contact holes that contact the pads of the vertical channel transistors. Metal layers are then deposited and patterned to form bitlines (e.g., 4201, 4202, 4204, and 4206) for the array.

[0215] Each bit line contacts a vertical column select transistor in each different sub-array. For example, bit line 4201 contacts the column select transistor for conductive column 4211 in the different sub-array above the cutout 4010, and contacts the column select transistor (not shown) for another conductive column in a different sub-array below the cutout. Bit line 4202 contacts the column select transistor for conductive column 4212 in the different sub-array above the cutout 4010, and contacts the column select transistor for conductive column 4214 in the different sub-array below the cutout 4010.

[0216] Figure 43 Drawing example as above Figure 27-42A flow chart of a manufacturing method is described. As shown in the flow chart, the steps begin by forming a stack comprising alternating layers of sacrificial material and layers of insulating material on a substrate (step 4301). The substrate may include an integrated circuit substrate, which in some cases includes logic circuitry adjacent to and below the stack, the logic circuitry being used to implement peripheral circuitry of a memory device. After the stack is formed, holes (first holes) are etched in a selected pattern, the holes are lined with material of a data storage structure (e.g., one or more layers of a multi-layer dielectric charge storage structure), and then a semiconductor channel material is lined on the material of the data storage structure to form an array of insulating pillars through the stack (step 4302).

[0217] In this process, after forming the insulating pillar array, a hole array is formed through the stack to form multiple groups of insulating pillars and holes (second holes). The holes will be used to form conductive pillars in a later step (step 4303). After the holes are formed, the exposed sacrificial material is removed through the holes (step 4304). This step is similar to the reference step. Figure 26 The steps described are different except that the slits used in the replacement steps are not necessary, thus allowing for a higher density array layout.

[0218] After wordline material is deposited in the voids left by the removal of the sacrificial material (step 4305), the voids are reopened, the wordline material is etched back to form recesses on the sidewalls, and insulating material is deposited. A reactive ion etching process is then performed to remove the insulating material outside the recesses. The reactive ion etching process also removes any oxide on the sides of the semiconductor channel material surrounding the insulating pillars that was exposed by the voids (step 4306). The voids are then filled with conductive material to form conductive pillars (step 4307).

[0219] The stack can then be planarized, for example using chemical mechanical polishing, and a column select layer is then formed on the stack, the column select layer comprising an insulating material, a conductive material, and an insulating material (step 4308). Thereafter, a vertical column select transistor is formed, comprising forming a hole through the column select layer and aligned with the conductive column (step 4309). Next, a gate oxide and a channel material are formed in a lined manner on the sidewalls of the hole, and the hole is then filled with an insulator. The insulator is etched back to form a pad on top of the vertical column select transistor (step 4310). Next, the column select layer is etched to define the column select gates for the different sub-arrays as described above (step 4311). Finally, the bit line structure and other back-end processes are performed to complete the device (step 4312).

[0220] Generally speaking, Figure 43Another example of a method for fabricating a vertical memory structure is illustrated, including forming a block comprising a stack comprising alternating insulating material layers and wordline material layers, and forming a plurality of distinct pillar groups comprising alternating conductive pillars and insulating pillars, the alternating conductive pillars and insulating pillars being arranged in an array and extending through the stack. Furthermore, the method includes forming a data storage structure on the inner surface of the wordline material layer at the intersections of the insulating pillars and the wordline material layer. The method also includes forming a semiconductor channel material between the insulating pillars and the data storage structure at the intersections of the insulating pillars and the wordline material layer. The semiconductor channel material can be an arcuate layer that extends around the arcuate outer surface of the insulating pillars and contacts adjacent conductive pillars on both sides to establish source / drain terminals at the contact points. Furthermore, the method results in forming a plurality of conductive strips in a pillar selection layer above the stack. For each distinct subarray of the array, the plurality of conductive strips includes a corresponding conductive strip serving as a gate for the plurality of vertical channel structures of the distinct subarray. Furthermore, the method includes forming a bitline conductor in the pillar selection layer above the stack. In the embodiments described herein, each bitline conductor has a contact structure connected to a vertical channel transistor in each different sub-array of the array in the stack.

[0221] The integrated circuit storage structure used to realize the storage array can be Figures 55-56 The schematic diagram shows that it can also be manufactured in multiple steps, which can be referred to Figures 44-50 Let's understand some of these steps. Figures 44-50 The various stages of the fabrication process of an alternative embodiment are shown, wherein the semiconductor channel material is discontinuous in the vertical direction, cutting off the current leakage paths in the array. Figure 3A The process further comprises a step of forming a hole array that will be used to form insulating pillars.

[0222] Figure 44 Draw on Figure 3A In a subsequent process stage, after forming holes 4401 and 4402 for forming insulating pillars, the sacrificial material layer (311-315) is etched back to form shallow recesses (e.g., 4411 and 4412). For embodiments with sacrificial material and silicon nitride, a suitable recipe for forming the recesses may include using an H3PO4 solution or a time-controlled selective reactive ion etch. The recesses provide a concave cavity for forming the channel material of the memory cell, wherein the sidewalls of the sacrificial material layer (e.g., 314s) are recessed relative to the sidewalls of the adjacent insulating material layer (e.g., 209s and 208s).

[0223] Figure 45The subassembly is shown at a process stage after depositing a silicon oxide layer and a semiconductor channel material layer (e.g., polysilicon), followed by an anisotropic etch to remove the semiconductor channel material between the recesses. This step leaves confined semiconductor channels (e.g., 4511, 4513) separated by silicon oxide layers (e.g., 4510, 4512) and sacrificial material layers in each level. The confined semiconductor channels extend in an arcuate shape around the outer surface of the hole within the recess. As a result, the semiconductor channel material is discontinuous in regions crossing the insulating material layer (e.g., 4520), severing potential leakage paths between memory cells on different levels of the structure.

[0224] The silicon oxide layer (e.g., 4510, 4512) can be part of a data storage structure, such as a tunneling layer of a multi-layer dielectric charge trapping structure. Furthermore, in some embodiments, additional layers of the multi-layer dielectric charge trapping structure can be deposited earlier than the silicon oxide layer. As described above, the remaining portion of the multi-layer dielectric charge trapping structure can be deposited during the step of replacing the sacrificial material to form the data storage structure in the confined, arcuate region at the intersection of the wordline layer and the insulating pillar in the structure.

[0225] Figure 46 It is a cross-sectional view along the row direction, after the holes are filled with an insulating material and a planarization process (such as chemical mechanical polishing) is performed to form insulating pillars 4601 and 4602.

[0226] Figure 47 The cross section line BB along the column direction (as mentioned above) Figure 6A The cross-sectional view shown in FIG. 1 is taken along line BB of the plan view after forming an array of holes for forming conductive pillars and filling the holes with a conductor (e.g., N+ polysilicon). A planarization step, such as chemical mechanical polishing, is performed after filling the holes.

[0227] Figure 48 For similar Figure 10 A cross-sectional view taken along section line BB is shown at a later stage after the insulating layer 1011, sacrificial layer 1020, and insulating layer 1012, which will form the column select transistor structure, are formed on top of the stack. The combined layer at this location is considered the column select layer of the stack. The sacrificial layer 1020 and insulating layer 1011 can be made of the same material as the alternating sacrificial and insulating material layers in the stack.

[0228] Figure 49 Draw a cross-section of the bit line orthogonal to the sub-component, and Figures 10 to 23BThe manufacturing stage after the steps described is shown for connecting the vertical conductive pillars 604 to the overlying bit lines 4910. The steps include replacing a layer of sacrificial material, such as tungsten in the word line layer of the stack and in the pillar select layer as described above, with word line material 4911, 5120 using the slits as described above located in the space and along the pillar group comprising alternating conductive pillars and insulating pillars. In this embodiment, replacing the sacrificial material with word line material 4911, 5120 includes depositing the remaining portion of the data storage structure, such as for the dielectric charge storage structure, the charge trapping layer (e.g., a charge trapping layer comprising silicon nitride), and the barrier layer comprising aluminum oxide or other high dielectric constant dielectric. As described above, a tunneling layer (e.g., a dielectric layer comprising aluminum oxide or other high dielectric constant dielectric) may be deposited prior to forming the semiconductor channel material as described above around the insulating pillars. Figure 45 In other embodiments, the silicon oxide layer 4510 may be Figure 45 In the subsequent stage, a tunneling layer (e.g., silicon oxide layer 4510) and a charge trapping layer are deposited, leaving only the barrier layer to be deposited in the stage that replaces the sacrificial material. Thus, a vertical pillar selection transistor structure, such as vertical transistor structure 4901, is formed. The vertical pillar selection transistor structure includes a gate oxide layer 4902 and a semiconductor channel layer 4903 surrounding an insulating core 4904. Furthermore, a pad 4905 is formed to establish a current path from the pad 4905 to the conductive pillar 604 below.

[0229] Additionally, interlayer dielectrics 4920 and 4921 are formed on the pillar select layer structure, and a plurality of bit lines (e.g., bit line 4910) are formed above the interlayer dielectric. As shown, a bit line contact structure 4908 is formed between pad 4905 of the vertical transistor structure (4901) and the overlying bit line 4910. In this embodiment, the structure may also include insulator-filled slots (not shown) disposed in the spaces along the pillar set comprising alternating insulating and conductive pillars, as previously described, wherein the slots are used to provide access to the sacrificial material during the step of replacing the sacrificial material with word line material. Of course, other techniques for providing access to the sacrificial material may also be used, including the aforementioned technique of using holes formed by the conductive pillars to provide access to the sacrificial material in the stack.

[0230] In this embodiment, since the semiconductor channel is formed in a restricted ring around the outer surface of the insulating pillar, a structure can be formed in which the word line controls all semiconductor channel material regions on the sidewalls of the insulating pillar.

[0231] Figure 50 Drawing example as above Figure 2-25 The manufacturing method described in Figures 44-49As shown in the flowchart, the steps begin by forming a stack of layers comprising alternating layers of sacrificial material and layers of insulating material on a substrate (step 5001). The substrate may include an integrated circuit substrate, which in some cases includes logic circuits adjacent to and below the stack, and the logic circuits may be used to implement peripheral circuits of a memory device. In addition, the stack may be formed on a conductive metal layer, such as a layer comprising a source side conductor in some embodiments, such as Figure 56 As shown. After forming the stack, holes are etched in a selected pattern to form an array of holes for insulating pillars through the stack (step 5002). The method then includes etching a recess in the sidewall of the sacrificial material layer, and forming at least a portion of the data storage structure (such as silicon oxide as described above) and channel material lining the recess (step 5003). Next, an anisotropic etching process is used to etch the interior of the hole to remove the channel material outside the recess, so that the channel material is discontinuous between the sacrificial material layers, and then filling the hole with insulating material (step 5004). The next step in the flow chart is to form an array of conductive pillars through the stack, the conductive pillar array being arranged in a pattern to form a block of the stack including the insulating material layer and the sacrificial material layer, and a plurality of pillar groups extending along the row direction in the block, the pillar groups including alternating insulating pillars and conductive pillars extending through the stack (step 5005).

[0232] Next in the flow chart, the method includes forming a sacrificial layer on the stack, separated by insulating layers above and below the sacrificial layer, for forming a pillar select transistor (step 5006). A plurality of holes are formed through the sacrificial layer above the stack, with the holes aligned with corresponding conductive pillars. A gate dielectric and a semiconductor channel material are formed to line the sidewalls of the holes, such that the semiconductor channel material contacts the corresponding conductive pillars (step 5007). Furthermore, a pad may be formed on top of the vertical transistor, the pad contacting the semiconductor channel material to provide a current path from the corresponding conductive pillar to the pad.

[0233] exist Figure 50In some embodiments, a plurality of slits are etched through the stack and the sacrificial layer above the stack. The slits are spaced apart along the row direction, for example, between each group of eight insulating pillars and nine conductive pillars in the pillar group, and extend across multiple pillar groups along the column direction, for example, across four or eight pillar groups. The slits expose the sacrificial material in the stack and the sacrificial material in the sacrificial layer above the stack (step 5008). After exposing the sacrificial material, the sacrificial material is removed through the slits, leaving apertures at the locations of the word lines and pillar select lines of the memory array implemented in this block (step 5009). Wordline material, such as tungsten, is then deposited in the apertures left by the removal of the sacrificial material. In some embodiments, a high-k dielectric liner is formed before depositing the wordline material, or one or more multi-layer charge storage structures are formed at the intersections of the wordlines and insulating pillars (step 5010). After depositing the wordline material, the remaining material within the slits is removed, and in this embodiment, the slits are filled with an insulator (step 5011).

[0234] Then, bitline construction and other back-end operations may be performed to complete the device (step 5012).

[0235] Figure 50 The method is based on the technique of removing sacrificial material by using slits spaced along a plurality of pillar groups including a plurality of conductive pillars and a plurality of insulating pillars. In other embodiments, holes for the conductive pillars can be used to remove the sacrificial material, such as with Figure 43 The technology described.

[0236] Generally speaking, Figure 50 Another example of a method for fabricating a vertical memory structure is illustrated, including forming a block comprising a stack comprising alternating insulating material layers and wordline material layers, and forming a plurality of distinct pillar groups comprising alternating conductive pillars and insulating pillars, the alternating conductive pillars and insulating pillars being arranged in an array and extending through the stack. Furthermore, the method includes forming a data storage structure on the inner surface of the wordline material layer at the intersections of the insulating pillars and the wordline material layer. The method also includes forming a semiconductor channel material between the insulating pillars and the data storage structure at the intersections of the insulating pillars and the wordline material layer. The semiconductor channel material can be an arcuate layer that extends around the arcuate outer surface of the insulating pillars and contacts adjacent conductive pillars on both sides to establish source / drain terminals at the junctions. Furthermore, the method results in forming a plurality of conductive strips in a pillar selection layer above the stack. For each distinct subarray of the array, the plurality of conductive strips includes a corresponding conductive strip serving as a gate for the plurality of vertical channel structures of the distinct subarray. Furthermore, the method includes forming a bitline conductor in the pillar selection layer above the stack. In the embodiments described herein, each bitline conductor has a contact structure connected to a vertical channel transistor in each different sub-array of the array in the stack.

[0237] The integrated circuit storage structure used to implement the storage array can be, for example, Figures 55-56 The schematic diagram shows that it can be manufactured in multiple steps, which can be referred to Figure 51-54A Let's understand some of these steps. Figure 51-54A The various stages of a manufacturing method according to an embodiment are shown, which can form a Figure 56 The circuit shown has a source side conductor below. This source side conductor can be used, for example, for memory operation, where a voltage is applied to the vertical conductive column through the conductor below to erase the memory cell block. Figure 5B and Figure 13B The stack is formed on top of the source line conductor 5205, which may be, for example, a lightly doped P-type conductive layer or a lightly doped P-type conductive line. In the structure, the conductive pillar 604 may be an n-type semiconductor, such as N+ polysilicon, and the source line conductor 5205 may be a p-type diffusion or other p-type semiconductor in the semiconductor substrate. This results in the formation of a PN junction 1301 at the intersection of the conductive pillar 604 and the source line conductor 5205, such as Figure 56 Knot 6332 shown.

[0238] Figure 13B The cross-section line BB is drawn along the row direction. Figure 11A , illustrates an alternative embodiment in which a source line conductor 5205, such as a p-type conductor layer, is disposed below the stack. In this structure, the conductive pillar 604 may be n-type or N+ type polysilicon, and the source line conductor 5205 may be a p-type diffusion in the semiconductor substrate, or another p-type semiconductor. This results in a PN junction 1301 being formed at the intersection of the conductive pillar 604 and the source line conductor 5205, such as Figure 56 Knot 6332 shown.

[0239] Figure 51 and Figure 52 (Similar to Figure 14 and Figure 15 ) are cross-sectional views taken along section lines AA and BB, respectively, showing the structure after a capping layer 1410 is formed on the column selection transistors 1210, 1220, 1230, and 1310. Figure 12 and Figure 13BCap layer 1410 may be a silicon oxide layer or other material layer that can serve as a hard mask or other type of protective layer for later processing steps. As previously described, a PN junction (e.g., 5110, 1301) is formed at the contact between the vertical conductive pillars (e.g., 6601, 6602, 6603, 604), which may include n-type polysilicon, and the source line conductor 5205. In other embodiments, the PN junction may be implemented in other ways or may be located at other locations along the current path from the source line conductor to the bias circuit, which is used to apply a bias voltage and float the connection of the source line conductor during memory operation.

[0240] Figure 53 A top plan view of an embodiment of a three-dimensional memory block 105 is shown at an intermediate manufacturing stage (the pillar selection layer is shown transparent), after forming the aforementioned slots through the stack for replacing the sacrificial material with wordline material. Figure 16A and Figures 16B to 21 In this embodiment, the slits are filled with a conductive material to form conductor-filled slits 5301 and 5302 connected to the source line conductor 5205 or multiple source line conductors below. Figure 52 In an embodiment, an interlayer contact structure is formed through an interlayer dielectric from the conductor-filled slots 5301, 5302 to a metal layer for forming a bit line or to other patterned conductor layers on the stack to form a connection between the conductor-filled slots 5301, 5302 and a bias circuit.

[0241] Figure 54A The bit lines (eg, 2201, 2202, 2204, 2206) are shown to be covered, similar to Figure 23A , and a top plan view of the structure after the step of forming overlying source line bias lines 5501 and 5502 connected to conductor-filled slots 5301 and 5302. This step may include depositing an interlayer dielectric over the column select transistor pad, forming a bitline contact plug through the interlayer dielectric and a contact structure connected to the conductor-filled slot, and then forming and patterning metal on an overlying patterned conductor layer or layers to form bitline and source line conductors. Multiple bitlines are assembled so that they contact at most one vertical conductor structure in each distinct subarray. Thus, bitline 2202 contacts vertical conductor structure 2213 in the subarray above notch 2010 at the top and contacts vertical conductor structure 2215 below notch 2010 at the bottom.

[0242] Figure 54B Drawing example as above Figure 2-25 The manufacturing method described in Figure 51-54AFlowchart showing an adjustment to the method of FIG. As shown in the flowchart, the steps begin by forming a stack comprising alternating layers of sacrificial material and insulating material on a P-type semiconductor layer or a plurality of P-type semiconductor lines on a substrate (step 5401). The substrate may include an integrated circuit substrate, which in some cases includes logic circuitry adjacent to and below the stack, which may be used to implement peripheral circuitry for a memory device. After forming the stack, holes are etched in a selected pattern to form an array of insulating pillars through the stack, lining the holes with material of a data storage structure (e.g., one or more multilayer dielectric charge storage structures), and then lining the material of the data storage structure with semiconductor channel material (step 5402). The next step in the flowchart is to form an array of conductive pillars through the stack, the conductive pillar array being arranged in a pattern to form a block of the stack comprising layers of insulating material and sacrificial material, with a plurality of pillar groups extending in a row direction within the block, the pillar groups comprising alternating insulating pillars and conductive pillars extending through the stack (step 5403). In this embodiment, the conductive pillars contact the source line conductor or multiple source line conductors below the corresponding PN junction.

[0243] Next in the flow chart, the method includes forming a sacrificial layer on the stack, separated by insulating layers above and below the sacrificial layer, for forming a pillar select transistor (step 5404). A plurality of holes are formed through the sacrificial layer above the stack, with the plurality of holes aligned with the conductive pillars. A gate dielectric and a semiconductor channel material are formed to line the sidewalls of the holes, such that the semiconductor channel material contacts the corresponding conductive pillars (step 5405). Furthermore, a pad may be formed on top of the hole, contacting the semiconductor channel material to provide a current path from the corresponding conductive pillar to the pad.

[0244] exist Figure 54BIn some embodiments, a plurality of slits are etched through the stack and the sacrificial layer above the stack. The slits are spaced apart along the row direction, for example, between each group of eight insulating pillars and nine conductive pillars in the pillar group, and extend across multiple pillar groups along the column direction, for example, across four or eight pillar groups. The slits expose sacrificial material in the stack and sacrificial material in the sacrificial layer above the stack (step 5406). After exposing the sacrificial material, the sacrificial material is removed through the slits, leaving apertures at the locations of word lines and pillar select lines for the memory array implemented in this block (step 5407). Word line material, such as tungsten, is then deposited in the apertures left by the removal of the sacrificial material. In some embodiments, a high-k dielectric liner is formed before depositing the word line material, or one or more multi-layer charge storage structures are formed at the intersections of the word lines and insulating pillars (step 5408). After depositing the word line material, the remaining material within the slits is removed, and the sidewalls of the word line material are oxidized or formed in the form of an insulator liner on the sidewalls of the word line material. The slots are then filled with a conductor, such as tungsten or polysilicon (in this embodiment) (step 5409).

[0245] Then, a bit line structure contacting the pad of the vertical column select transistor and a source line bias line structure contacting the conductor filling slot are formed, and the bit line structure and other back-end operations may be performed to complete the device (step 5410).

[0246] Generally speaking, Figure 54B An example method for fabricating a vertical memory structure is illustrated, including forming a block comprising a stack above a source line bias conductor, the stack comprising alternating insulating material layers and word line material layers, and forming a plurality of distinct pillar groups comprising alternating conductive pillars and insulating pillars, the alternating conductive pillars and insulating pillars being arranged in an array and extending through the stack. Furthermore, the method includes forming a data storage structure on the inner surface of the word line material layer at the intersections of the insulating pillars and the word line material layer. The method also includes forming a semiconductor channel material between the insulating pillars and the data storage structure at the intersections of the insulating pillars and the word line material layer. The semiconductor channel material can be an arcuate layer that extends around the arcuate outer surface of the insulating pillars and contacts adjacent conductive pillars on both sides to establish source / drain terminals at the junctions. Furthermore, the method results in forming a plurality of conductive strips in a pillar select layer above the stack. For each distinct subarray of the array, the plurality of conductive strips includes a corresponding conductive strip serving as a gate for the plurality of vertical channel structures of the distinct subarray. Furthermore, the method includes forming a bit line conductor in the pillar select layer above the stack. In the embodiments described herein, each bitline conductor has a contact structure connected to a vertical channel transistor in each different sub-array of the array in the stack.

[0247] Figure 54BThe method is based on the technique of removing sacrificial material by using slits spaced along a plurality of pillar groups including a plurality of conductive pillars and a plurality of insulating pillars. In other embodiments, holes for the conductive pillars can be used to remove the sacrificial material, such as with Figure 43 Furthermore, in other embodiments, the method may include the step of limiting the semiconductor channel material on the outer surface of the insulating pillar, as previously described with reference to FIG. Figure 50 As stated.

[0248] As mentioned above, Figures 55-56 A simplified circuit diagram of a three-dimensional virtual ground memory for a memory device in an AND flash or NOR flash structure, which can be implemented as described herein.

[0249] Figure 57 57 is a simplified block diagram of an integrated circuit, which in various embodiments may be implemented in a single chip or multi-chip packages. Integrated circuit 5700 includes a three-dimensional virtual ground memory array 5760 as described herein.

[0250] The memory device may include a bit line decoder 5750 (and in some embodiments, a source line conductor decoder for block erase operations). In addition, the memory device includes circuitry 5752 connected to the bit lines 5755 for biasing the bit lines for memory operations. In addition, in some embodiments, circuitry 5752 may include circuitry for biasing the source line conductors (e.g., with a Figure 54A Circuitry 5752 can be configured to select memory cells and memory cell blocks in the memory array for memory operations such as reading, erasing, and programming. Circuitry outside the memory array structure is referred to as peripheral circuitry. Peripheral circuitry can be configured for a virtual ground memory structure and can include circuitry that causes at least some of the plurality of bit lines to alternately function as source-side conductors and drain-side conductors during memory operations. As previously described, the three-dimensional virtual ground memory array 5760 can be implemented on some or all of the peripheral circuitry.

[0251] Bit line transistors BLT (also referred to herein as column select transistors) and word line decoders 5763 are coupled to a plurality of word lines 5764 for performing read, erase, and program operations on memory cells in different sub-arrays as described above. Addresses are provided on bus 5765 for supply to the BLT and word line decoders 5763 and to bit line decoder 5750. In this example, sense amplifiers and data input structures in block 5766 are coupled to bit line decoder 5750 via data bus 5767. Data is provided to the data input structures in block 5766 via data input lines 5771 from input / output ports on integrated circuit 5700, or from other data sources internal or external to integrated circuit 5700.

[0252] In the embodiment shown, other circuits 5774 are included in the integrated circuit, such as a general-purpose processor or special-purpose application circuits, or a combination of modules providing system-on-a-chip functionality supported by the programmable resistor memory cell array. Data is provided from the sense amplifiers in block 5766 via data output lines 5772 to input / output ports on the integrated circuit 5700, or to other data destinations internal or external to the integrated circuit 5700.

[0253] A controller 5769 (which may be implemented, for example, as a bias configuration state machine) configured for memory operations such as read, erase, and program controls the application of bias configuration supply voltages, such as program, erase, and read voltages. The bias configuration supply voltages are generated or provided by a voltage supply or multiple voltage supplies in block 5768.

[0254] The controller may be implemented as special-purpose logic circuitry as is known in the art. In alternative embodiments, the controller includes a general-purpose processor, which may be implemented on the same integrated circuit, and which executes a computer program to control the operation of the device. In other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be used to implement the controller.

[0255] The controller may contain logic to control read, program, and erase operations, including applying the bias voltages shown in the following table. Table 1 contains the logic used for Figure 55 The bias voltages for the three-dimensional virtual ground arrays shown in FIG. 1 have discontinuous or continuous channel materials in the vertical direction. Table 2 contains the bias voltages for the three-dimensional virtual ground arrays shown in FIG. Figure 56 The biasing of a three-dimensional virtual ground array is shown, with vertically continuous via material in the pillars.

[0256] Table 1

[0257]

[0258]

[0259] Table 2

[0260]

[0261] Described herein are some flowcharts illustrating various embodiments of manufacturing methods. As with all flowcharts herein, the reader will appreciate that many steps can be combined, performed simultaneously, or performed in a different order without affecting the functionality achieved. In some cases, as the reader will appreciate, rearrangement of multiple steps will achieve the same functionality only if certain other changes are made. In other cases, as the reader will appreciate, rearrangement of multiple steps will achieve the same functionality only if certain conditions are met. Furthermore, the reader will appreciate that the flowcharts herein illustrate only some of the steps relevant to understanding the present technology, and will appreciate that multiple additional steps to achieve other functionality may be performed before, after, or between the steps shown.

[0262] The manufacturing methods described herein include examples of methods for manufacturing vertical storage structures, comprising:

[0263] forming a block comprising a stack comprising alternating layers of insulating material and wordline layers;

[0264] forming a plurality of different pillar groups comprising a plurality of conductive pillars and a plurality of insulating pillars alternatingly arranged in a stack, wherein the conductive pillars in the plurality of different pillar groups are arranged in an array and in a plurality of different sub-arrays of the array, each different sub-array comprising at least one different pillar group from the plurality of pillar groups;

[0265] forming a data storage structure on an inner surface of the word line material layer disposed at intersections of the insulating pillars and the word line material layer in the plurality of distinct pillar groups;

[0266] forming semiconductor channel materials between the insulating pillars in the plurality of different pillar groups and the data storage structure and at intersections of the insulating pillars in the plurality of different pillar groups and the word line material layer, wherein the semiconductor channel materials extend around outer surfaces of the insulating pillars in the plurality of different pillar groups and contact adjacent conductive pillars on both sides of the plurality of different pillar groups;

[0267] forming a plurality of conductive strips in the pillar selection layer on the stack, including a corresponding conductive strip corresponding to each different sub-array of the array, and including a plurality of vertical channel structures corresponding to each different sub-array of the array, the vertical channel structures passing through the corresponding conductive strips and contacting individual conductive pillars in the different sub-arrays; and

[0268] A plurality of bit line conductors are formed on a pillar selection layer on the stack, each bit line conductor having a contact structure connected to a vertical channel transistor of the plurality of vertical channel transistors in each different sub-array.

[0269] This disclosure describes several examples of fabrication methods in which the semiconductor channel material is an arcuate layer along the outer surface of a first insulating pillar.

[0270] The present disclosure describes various examples of fabrication methods in which forming a block includes forming a stack comprising alternating layers of sacrificial material and layers of insulating material, and replacing the sacrificial material with a wordline material.

[0271] The present disclosure describes multiple examples of manufacturing methods, wherein forming a block includes: forming a stack comprising alternating layers of sacrificial material and layers of insulating material, etching a plurality of first holes through the stack, lining the plurality of first holes with a material of a data storage structure, lining the material of the data storage structure with a semiconductor channel material, and filling the plurality of first holes with an insulating material to form insulating pillars; etching a plurality of second holes through the stack, and filling the plurality of second holes with a conductive material to form conductive pillars; forming a sacrificial layer on the stack, separating the sacrificial layer from the stack with an insulating material, and covering the sacrificial layer with the insulating material; forming a plurality of third holes through the sacrificial layer on the stack, the plurality of third holes The holes are aligned with the conductive pillars, and a layer of gate dielectric and semiconductor channel structures are formed in the plurality of third holes, current-contacting the corresponding conductive pillars. A slot is etched through the stack and the sacrificial layer on the stack, the slot being disposed between a plurality of groups of conductive pillars, the plurality of groups of conductive pillars having X conductive pillars along a row direction, and the slot extending across Y of the plurality of rows along a second direction, the slot exposing sacrificial material in the stack. The sacrificial material exposed by the slot is removed to form an aperture at a location of the sacrificial material layer in the stack and a location of the sacrificial layer on the stack. A wordline material is deposited in the aperture to form a wordline material layer in the stack and a conductive material layer on the stack (using the slot for gate replacement).

[0272] The present disclosure describes several examples of fabrication methods, wherein forming a block includes: forming a stack comprising alternating layers of sacrificial material and layers of insulating material; etching a plurality of first holes through the stack, lining the plurality of first holes with a material of a data storage structure, lining the material of the data storage structure with a semiconductor channel material, and filling the plurality of first holes with an insulating material to form insulating pillars; etching a plurality of second holes through the stack; removing the sacrificial material exposed through the second holes to form pores in the stack at locations of the sacrificial material layers; depositing a word line material in the pores to form a word line material layer in the stack, and depositing a word line material in the pores exposed through the second holes. The invention relates to a method for forming an insulator on the sidewall of the word line material layer; etching back the insulating material in the second hole to expose the semiconductor channel material lining the insulating pillar in the adjacent first hole; filling the reopened second hole with a conductive material to form a conductive pillar; forming a conductive layer on the stack, separating the conductive layer and the stack conductive layer with an insulating material, and covering the conductive layer with the insulating material; forming a plurality of third holes through the conductive layer on the stack, the third holes being aligned with the conductive pillars, and forming a layer of gate dielectric and semiconductor channel structure in the plurality of third holes that are in current contact with the corresponding conductive pillars; and etching the conductive material layer on the stack to define a plurality of conductive strips.

[0273] The present disclosure describes multiple examples of manufacturing methods, in which forming a block includes: forming a stack comprising alternating multiple sacrificial material layers and multiple insulating material layers; etching a plurality of first holes through the stack; etching to recess the sidewalls of the exposed sacrificial material layers relative to the sidewalls of the exposed insulating material layers; and lining the recessed sidewalls in the recess with material of a data storage structure, lining the material of the data storage structure with material of a semiconductor channel, and filling the holes with insulating material to form insulating pillars.

[0274] This disclosure describes several examples of fabrication methods including etching semiconductor channel material in the hole so that it is discontinuous between layers of sacrificial material before filling the hole. The present disclosure describes several examples of a manufacturing method, including: etching a plurality of second holes through a stack and filling the holes with a conductive material to form conductive pillars; forming a sacrificial layer on the stack, separating the sacrificial layer from the stack with an insulating material, and covering the sacrificial layer with the insulating material; forming a plurality of third holes through the sacrificial layer above the stack, the third holes aligned with the conductive pillars, and forming a gate dielectric and semiconductor channel structure in the plurality of third holes, the gate dielectric and semiconductor channel structures being in current contact with corresponding conductive pillars; etching a slot through the stack and the sacrificial layer above the stack, the slot being disposed between a plurality of groups of conductive pillars, the plurality of groups of conductive pillars having X conductive pillars along a row direction, the slot extending across Y of the plurality of rows along a second direction, the slot exposing the sacrificial material in the stack; removing the sacrificial material exposed by the slot to form an aperture at a location of the sacrificial material layer in the stack and a location of the sacrificial layer above the stack; depositing a wordline material in the aperture to form a wordline material layer in the stack and a conductive material layer above the stack; and etching the conductive material layer above the stack to define a plurality of conductive strips.

[0275] The present disclosure describes several examples of manufacturing methods, including forming a conductive layer below a stack, wherein conductive pillars in a plurality of distinct pillar groups including conductive pillars and insulating pillars are connected to the conductive layer via PN junctions.

[0276] The present disclosure describes multiple examples of manufacturing methods, including: forming conductor-filled slots, the conductor-filled slots being arranged in intervals along a plurality of pillar groups comprising alternating conductive pillars and insulating pillars, and the conductor-filled slots extending through a stack to contact a conductive layer below the stack, the conductor-filled slots being elongated along a direction orthogonal to the plurality of pillar groups comprising alternating conductive pillars and insulating pillars.

[0277] The present disclosure describes multiple examples of fabrication methods, including: conductive pillars comprising an n-type semiconductor, and a conductive layer beneath a stack comprising a p-type semiconductor. The present disclosure describes multiple examples of fabrication methods, wherein the conductive pillars in a block are arranged in multiple rows extending along a row direction and multiple columns extending along a column direction, insulating pillars are arranged between adjacent conductive pillars in a row, and conductive strips are separated from adjacent conductive strips by etching cuts in a conductive material layer overlying the stack, with the cuts located between the multiple rows of conductive pillars to define the conductive strips. The present disclosure describes multiple examples of fabrication methods, wherein the block includes rows of dummy conductive pillars between different subarrays, and conductive strips are separated from adjacent conductive strips by etching cuts in a conductive material layer overlying the stack and over the rows of dummy conductive pillars to define the conductive strips. The present disclosure describes multiple examples of fabrication methods, wherein a wordline material layer has a side surface adjacent to the insulating pillar that is recessed relative to a side surface of an adjacent insulating material layer to form a recess between the insulating material layers, and wherein the semiconductor channel material and the data storage structure are arranged in the recess.

[0278] The present disclosure describes various examples of fabrication methods in which multiple word line material layers, multiple conductive strips, and multiple bit lines are configured in a virtual ground memory structure.

[0279] This disclosure describes various examples of fabrication methods in which data storage structures include multi-layer charge trapping structures.

[0280] This disclosure describes various examples of fabrication methods including forming a second insulating material liner on a wordline material layer in a stack, the second insulating material having a higher dielectric constant than insulating materials of a plurality of insulating material layers in the stack.

[0281] The present disclosure provides a three-dimensional memory structure suitable for high-density and high-capacity storage. Several features of embodiments of the structure include aligning the longitudinal axes of vertical conductive pillars for source / drain contact structures along rows of pillars. Several embodiments also include cutouts between bitline select lines, aligned with rows of dummy insulating pillars and dummy conductive pillars.

[0282] In various embodiments, a high-k dielectric material (with a dielectric constant K greater than 7) isolates the vertical conductive pillars for the source / drain contact structures from the wordline material.

[0283] In various embodiments, the channel is discontinuous along the vertical or Z-axis.

[0284] In various embodiments, the width of the vertical conductive pillars for the source / drain contact structures is smaller than the width of the insulating pillars in a direction orthogonal to the direction of the pillar groups.

[0285] While the present invention has been disclosed using the preferred embodiments and examples described above, it should be understood that these examples are for illustrative purposes only and are not intended to limit the present invention. Persons skilled in the art will readily appreciate that various modifications and combinations of the present invention can be made without departing from the spirit and scope of the present invention. The scope of protection of the present invention is defined by the appended claims.

Claims

1. A vertical storage structure, characterized in that: Include: a stack comprising a plurality of alternating insulating material layers and a plurality of wordline material layers; a pillar group disposed through the stack and comprising a plurality of alternating conductive pillars and a plurality of insulating pillars, the pillar group comprising at least a first conductive pillar, a first insulating pillar adjacent to the first conductive pillar, and a second conductive pillar adjacent to the first insulating pillar, wherein an outer surface of the first insulating pillar is arcuate in a plane parallel to the wordline material layers; A plurality of data storage structures are disposed on a plurality of inner surfaces of the word line material layers at a plurality of intersections between the first insulating pillar and the word line material layers; as well as A semiconductor channel material is disposed between the first insulating pillar and the data storage structures and at the intersections of the first insulating pillar and the word line material layers, the semiconductor channel material extending around the outer surface of the first insulating pillar and contacting the first conductive pillar and the second conductive pillar, wherein the inner surfaces of the word line material layers adjacent to the first insulating pillar are recessed relative to the inner surfaces of the insulating material layers adjacent to the first insulating pillar to form a plurality of recesses between the insulating material layers, and wherein the semiconductor channel material and the data storage structures are disposed in the recesses.

2. The vertical storage structure according to claim 1, characterized in that: The semiconductor channel material disposed in the recesses is discontinuous in a vertical direction and spans the insulating material layers.

3. The vertical storage structure according to claim 1, characterized in that: This column set also contains: a second insulating pillar adjacent to the second conductive pillar and a third conductive pillar adjacent to the second insulating pillar, The vertical storage structure also includes: a plurality of data storage structures disposed on a plurality of inner surfaces of the word line material layers at a plurality of intersections between the second insulating pillar and the word line material layers; and A semiconductor channel material is disposed between the second insulating pillar and the data storage structures and at the intersections of the second insulating pillar and the word line material layers. The semiconductor channel material extends around an outer surface of the second insulating pillar to contact the second conductive pillar and the third conductive pillar.

4. The vertical storage structure according to claim 1, characterized in that: Also includes: a conductive strip covering the stack; A plurality of vertical channel transistors pass through the conductive strip and respectively contact the conductive pillars in the pillar group; A plurality of bit line conductors are disposed in a layer above the plurality of vertical channel transistors and respectively contact the plurality of vertical channel transistors.

5. The vertical storage structure according to claim 1, characterized in that: The plurality of column groups are arranged through the stack and include alternating plurality of conductive columns and plurality of insulating columns. The plurality of conductive columns in the plurality of column groups are arranged in an array. The plurality of column groups include the column group including a first conductive column.

6. The vertical storage structure according to claim 5, characterized in that: The plurality of pillar groups in the array are arranged into a plurality of different sub-arrays, each of the plurality of different sub-arrays includes at least one pillar group from the plurality of pillar groups, and the vertical storage structure further includes: a plurality of conductive strips disposed in a pillar selection layer above the stack, including a corresponding conductive strip corresponding to each of the plurality of different sub-arrays of the array, and including a plurality of vertical channel structures corresponding to each of the plurality of different sub-arrays of the array, the plurality of vertical channel structures passing through the corresponding conductive strip and respectively contacting the conductive pillars in the plurality of different sub-arrays; as well as A plurality of bit line conductors are disposed on the pillar selection layer on the stack, each of the plurality of bit line conductors having a plurality of contact structures connected to a vertical channel transistor of a plurality of vertical channel transistors in each of the plurality of different sub-arrays.

7. The vertical storage structure according to claim 6, characterized in that: Also includes: a conductive layer located below the stack, wherein the conductive pillars in the plurality of pillar groups are connected to the conductive layer via a PN junction; and A plurality of conductor-filled slots are disposed in a plurality of intervals along the plurality of pillar groups and extend through the stack to contact the conductive layer below the stack. The conductor-filled slots are elongated along a direction perpendicular to the plurality of pillar groups.

8. The vertical storage structure according to claim 7, characterized in that: The conductive pillars in the plurality of pillar groups include n-type semiconductors, and the conductive layer below the stack includes p-type semiconductors.

9. The vertical storage structure according to claim 1, characterized in that: Include: a plurality of pillar groups, the plurality of pillar groups being disposed through the stack and comprising alternating plurality of the conductive pillars and plurality of the insulating pillars, the conductive pillars in the plurality of pillar groups being arranged in an array, the plurality of pillar groups including the pillar group comprising a first conductive pillar, wherein the plurality of pillar groups in the array are arranged into a plurality of distinct sub-arrays, each of the plurality of distinct sub-arrays comprising at least one pillar group in the plurality of pillar groups, and the vertical memory structure further comprising: a plurality of conductive strips separated by a plurality of gaps in a pillar selection layer above the stack, the plurality of conductive strips including a corresponding conductive strip corresponding to each of the plurality of different sub-arrays of the array, and including a plurality of vertical channel structures corresponding to each of the plurality of different sub-arrays of the array, the plurality of vertical channel structures passing through the corresponding conductive strip and respectively contacting the conductive pillars in the plurality of different sub-arrays; a plurality of alternating dummy conductive pillars and dummy insulating pillars disposed through the stack in a row and aligned with the gaps separating the plurality of conductive strips; A plurality of bit line conductors are disposed on the pillar selection layer on the stack, each of the plurality of bit line conductors having a plurality of contact structures connected to a vertical channel transistor of a plurality of vertical channel transistors in each of the plurality of different sub-arrays.

10. The vertical storage structure according to claim 9, characterized in that: The plurality of alternating dummy conductive pillars and dummy insulating pillars and the plurality of pillar groups are arranged into a regular array.

11. The vertical storage structure according to claim 6, characterized in that: The word line material layers, the plurality of conductive strips and the plurality of bit line conductors are arranged in a virtual ground memory structure.

12. The vertical storage structure according to claim 1, characterized in that: The semiconductor channel material between the insulating pillars and the data storage structures is discontinuous between the word line material layers in the stack.

13. A vertical storage structure, characterized in that: Include: a stack comprising a plurality of alternating insulating material layers and a plurality of wordline material layers; a plurality of distinct pillar groups comprising alternating cylindrical conductive pillars and cylindrical insulating pillars, the plurality of distinct pillar groups being disposed through the stack, the conductive pillars in the plurality of distinct pillar groups being arranged in an array and in a plurality of distinct sub-arrays of the array, each of the plurality of distinct sub-arrays comprising at least one distinct pillar group in the plurality of distinct pillar groups, each of the plurality of distinct pillar groups comprising at least a first conductive pillar, a first insulating pillar adjacent to the first conductive pillar, and a second conductive pillar adjacent to the first insulating pillar; a plurality of data storage structures disposed on the inner surfaces of the word line material layers at the intersections of the insulating pillars and the word line material layers in the plurality of different pillar groups; a semiconductor channel material between the insulating pillars in the plurality of different pillar groups and the data storage structures and located at the intersections of the insulating pillars in the plurality of different pillar groups and the word line material layers, the semiconductor channel material extending around the outer surfaces of the insulating pillars in the plurality of different pillar groups and contacting the adjacent conductive pillars on both sides of the plurality of different pillar groups; a plurality of conductive strips disposed in a pillar selection layer on the stack, the plurality of conductive strips including a corresponding conductive strip corresponding to each of the plurality of different sub-arrays of the array, and including a plurality of vertical channel structures corresponding to each of the plurality of different sub-arrays of the array, the plurality of vertical channel structures passing through the corresponding conductive strip and respectively contacting the conductive pillars in a corresponding different sub-array; as well as A plurality of bit line conductors are disposed on the pillar selection layer on the stack, each of the plurality of bit line conductors having a plurality of contact structures connected to a vertical channel transistor of the plurality of vertical channel transistors in each of the plurality of different sub-arrays.

14. The vertical storage structure according to claim 13, characterized in that: The outer surfaces of the insulating pillars are arched in a plane parallel to the word line material layers.

15. The vertical storage structure according to claim 13, characterized in that: The inner surfaces of the word line material layers adjacent to the insulating pillars are recessed relative to the inner surfaces of the insulating material layers adjacent to the insulating pillars to form a plurality of recesses between the insulating material layers, wherein the semiconductor channel material and the data storage structures are disposed in the recesses.

16. The vertical storage structure according to claim 15, characterized in that: The semiconductor channel material disposed in the recesses is discontinuous in a vertical direction across the insulating material layers.

17. The vertical storage structure according to claim 13, characterized in that: Also includes: a conductive layer disposed below the stack, wherein the conductive pillars in the plurality of different pillar groups are connected to the conductive layer via a PN junction; and A plurality of conductor-filled slots are disposed at a plurality of intervals along the plurality of distinct pillar groups and extend through the stack to contact the conductive layer below the stack, the conductor-filled slots being elongated in a direction orthogonal to the plurality of distinct pillar groups.

18. The vertical storage structure according to claim 17, characterized in that: The conductive pillars include n-type semiconductors, and the conductive layer below the stack includes p-type semiconductors.

19. The vertical storage structure according to claim 13, characterized in that: The plurality of conductive strips are separated by a plurality of gaps in the pillar selection layer on the stack, and the vertical storage structure comprises: A plurality of alternating dummy conductive pillars and dummy insulating pillars are disposed through the stack in a row and aligned with the gaps separating the plurality of conductive strips.

20. The vertical storage structure according to claim 13, characterized in that: The word line material layers, the conductive strips, and the bit line conductors are arranged in a virtual ground memory structure, and the vertical memory structure includes peripheral circuits to enable at least some of the bit line conductors to alternately function as a source side conductor and a drain side conductor during memory operations.

21. The vertical storage structure according to claim 13, characterized in that: The semiconductor channel material between the insulating pillars and the data storage structures is discontinuous between the word line material layers in the stack.

22. The vertical storage structure according to claim 13, characterized in that: A specific different pillar group among the plurality of different pillar groups includes N+1 conductive pillars and N insulating pillars, and the specific different pillar group includes N memory cell stacks.

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