A logic circuit for generating a dead zone of a driving signal

Abstract

The present invention belongs to the technical field of integrated circuits, and specifically relates to a logic circuit for generating a dead zone of a driving signal. This circuit generates driving signals for respectively driving the upper and lower power MOS transistors. The upper and lower parts have the same structure, which is composed of four transmission gates, four NOR gates and inverters. The input signals are a fixed PWM wave and the dead time generated by the previous stage, where the dead time is represented by a narrow pulse with a certain width, and the PWM waveform with dead time is triggered by the edge of the pulse at the output. The present invention generates a driving signal with dead time in the form of logic gates, preventing the driving circuit from generating shoot-through loss and improving the safety and stability of the circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a logic circuit for generating a dead zone of a driving signal. Background Art

[0002] In a high-voltage gate drive chip, there are two different channels, a high side and a low side. When the delay paths of the two channels do not match due to some reasons, the power transistors on the high and low sides may be turned on simultaneously, resulting in shoot-through, which can easily cause the bridge arm to burn out. Therefore, a dead zone module is added to the high-voltage gate drive chip to prevent shoot-through and bridge arm burnout. And in different application scenarios, the dead zone time is different. By extracting the dead zone time of the gate drive circuit in different application scenarios, the dead zone time can be represented by a narrow pulse of a corresponding width. A circuit structure is needed to superimpose the narrow pulse representing the dead zone time on the PWM wave signal of the system. Summary of the Invention

[0003] In view of the above problems, the present invention provides a hardware dead zone circuit that generates a dead zone time based on the edge-triggering function of a signal, thereby preventing shoot-through of the upper and lower transistors and improving the reliability and safety of the drive circuit.

[0004] The technical solution of the present invention is as follows:

[0005] A logic circuit for generating a dead zone of a driving signal, including a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, a first NOR gate, a second NOR gate, a third NOR gate, a fourth NOR gate, and an inverter; the input of the first transmission gate is connected to an input PWM signal, the upper control terminal of the first transmission gate is connected to an input dead zone time signal, the lower control terminal of the first transmission gate is connected to the inverse of the input dead zone time signal, and the output of the first transmission gate is connected to the second input terminal of the first NOR gate and the output terminal of the second transmission gate; the output terminal of the first NOR gate is connected to the input of the third transmission gate and the second input of the second NOR gate, and the output terminal of the second NOR gate is connected to the input of the second transmission gate; the upper control terminal of the second transmission gate is connected to the inverse of the input dead zone signal, and the lower control terminal is connected to the input dead zone signal; the upper control terminal of the third transmission gate is connected to the inverse of the input dead zone signal, and the lower control terminal is connected to the input dead zone signal. The output of the third transmission gate is connected to the second input of the third NOR gate and the output of the fourth transmission gate; the output of the third NOR gate is connected to the second input of the fourth NOR gate and the output of the PWM wave with dead zone; the output of the fourth NOR gate is connected to the input of the fourth transmission gate; the upper control terminal of the fourth transmission gate is connected to the input dead zone signal, and the lower control terminal is connected to the inverse of the input dead zone signal; the first input terminal of the first NOR gate and the first input terminal of the fourth NOR gate are connected to an external set input; the first input terminal of the second NOR gate and the first input terminal of the third NOR gate are connected to the inverse of the input PWM signal.

[0006] The beneficial effects of the present invention are as follows: by generating dead time through edge triggering, it has higher precision and better stability, and the generated dead time matches the input highly. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a system block diagram of a logic circuit for generating dead time of a drive signal proposed by the present invention.

[0008] Figure 2 It is an implementation structure diagram of a logic circuit for generating dead time of a drive signal proposed by the present invention.

[0009] Figure 3 It is the overall simulation result obtained by HSpice simulation of a logic circuit for generating dead time of a drive signal proposed by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0010] The present invention will be described in detail below with reference to the accompanying drawings.

[0011] The present invention proposes an overall circuit structure block diagram for adaptive dead time control as Figure 1 shown. It is divided into high and low sides. A certain dead time is generated through a sampling circuit, and then the dead time is introduced into the PWM wave through a logic circuit to generate a PWM wave with dead time.

[0012] Figure 2Circuit structure diagram of a logic circuit for generating a dead zone of a driving signal, characterized in that it includes a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4, a first NOR gate NOR1, a second NOR gate NOR2, a third NOR gate NOR3, a fourth NOR gate NOR4, and an inverter; the input of the first transmission gate TG1 is connected to the input PWM signal RD, the upper control terminal of the first transmission gate TG1 is connected to the input dead time signal, the lower control terminal of the first transmission gate TG1 is connected to the inverted input dead time signal, and the output of the first transmission gate TG1 is connected to the second input terminal of the first NOR gate NOR1 and the output terminal of the second transmission gate TG2; the output terminal of the first NOR gate NOR1 is connected to the input of the third transmission gate TG3 and the second input of the second NOR gate NOR2, and the output terminal of the second NOR gate NOR2 is connected to the input of the second transmission gate TG2; the upper control terminal of the second transmission gate TG2 is connected to the inverted input dead signal CP, and the lower control terminal is connected to the input dead signal CP; the upper control terminal of the third transmission gate TG3 is connected to the inverted input dead signal CP, and the lower control terminal is connected to the input dead signal CP. The output of the third transmission gate TG3 is connected to the second input of the third NOR gate NOR3 and the output of the fourth transmission gate TG4; the output of the third NOR gate NOR3 is connected to the second input of the fourth NOR gate NOR4 and the output terminal Q of the PWM wave with dead zone; the output of the fourth NOR gate NOR4 is connected to the input of the fourth transmission gate TG4; the upper control terminal of the fourth transmission gate TG4 is connected to the input dead signal CP, and the lower control terminal is connected to the inverted input dead signal CP; the first input terminals of the first NOR gate NOR1 and the fourth NOR gate NOR4 are connected to the external set input SD; the first input terminals of the second NOR gate NOR2 and the third NOR gate NOR3 are connected to the inverted input PWM signal RDRD.

[0013] When the SD port inputs 0, the circuit works in the startup state; when the SD port is set to 1, the output terminal Q of the PWM wave with dead zone is set to 0. The RD port is the PWM input port. When the input of the RD port is 1, the circuit works. When the input of the RD port is 0, the output is set to 0. When the SD port input is 0 and the RD port input is 1, when the input dead signal CP jumps from 0 to 1, the first transmission gate TG1 and the fourth transmission gate TG4 are turned on, the second transmission gate TG2 and the third transmission gate TG3 are turned off, and the output of the first NOR gate NOR1 is equal to the input PWM signal RD, and the output terminal Q of the PWM wave with dead zone remains unchanged; after a narrow pulse of the dead time, when the input dead signal CP jumps from 1 to 0, the first transmission gate TG1 and the fourth transmission gate TG4 are turned off, the second transmission gate TG2 and the third transmission gate TG3 are turned on, the output of the first NOR gate NOR1 remains unchanged, and the output terminal Q of the PWM wave with dead zone is equal to the output of the first NOR gate, and the output terminal Q of the PWM wave with dead zone becomes 1.

[0014] Based on the above method, a PWM wave output with an input dead time is generated, and the output simulation results are as Figure 3 shown.

Claims

1. A logic circuit for generating a dead zone of a driving signal, characterized in that It includes a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, a first NOR gate, a second NOR gate, a third NOR gate, a fourth NOR gate, and an inverter; the input of the first transmission gate is connected to an input PWM signal, the upper control terminal of the first transmission gate is connected to an input dead-time signal, the lower control terminal of the first transmission gate is connected to the inverted input dead-time signal, and the output of the first transmission gate is connected to the second input terminal of the first NOR gate and the output terminal of the second transmission gate; the output terminal of the first NOR gate is connected to the input of the third transmission gate and the second input of the second NOR gate, and the output terminal of the second NOR gate is connected to the input of the second transmission gate; the upper control terminal of the second transmission gate is connected to the inverted input dead-time signal, and the lower control terminal is connected to the input dead-time signal; the upper control terminal of the third transmission gate is connected to the inverted input dead-time signal, and the lower control terminal is connected to the input dead-time signal, and the output of the third transmission gate is connected to the second input of the third NOR gate and the output of the fourth transmission gate; the output of the third NOR gate is connected to the second input of the fourth NOR gate and the output of the PWM wave with dead time; the output of the fourth NOR gate is connected to the input of the fourth transmission gate; the upper control terminal of the fourth transmission gate is connected to the input dead-time signal, and the lower control terminal is connected to the inverted input dead-time signal; the first input terminals of the first NOR gate and the fourth NOR gate are connected to an external set input; the first input terminals of the second NOR gate and the third NOR gate are connected to the inverted input PWM signal.

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