Chip testing method, apparatus, device, and medium

Abstract

The application provides a chip testing method, device, equipment and medium, and relates to the technical field of chips. The method comprises the following steps: obtaining an estimated offset of an output characteristic of a to-be-tested chip under a target testing process, wherein the target testing process is a chip testing process that has an influence on the output characteristic of the to-be-tested chip; and adjusting the output characteristic of the to-be-tested chip by using a target chip fusing scheme corresponding to the estimated offset, so that an actual output value of the output characteristic of the to-be-tested chip after characteristic adjustment is offset by a compensation offset corresponding to the estimated offset compared with a standard value of the output characteristic, and the compensation offset is opposite to the offset direction of the estimated offset, wherein the compensation offset is used to compensate an actual output characteristic offset of the to-be-tested chip after characteristic adjustment in the target testing process. According to the embodiment of the application, the output characteristic of the chip can be accurately optimized.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, and particularly to a chip testing method, device, equipment and medium. BACKGROUND

[0002] In the preparation process of a chip, the chip often needs to be tested in the last link to ensure the quality of the prepared chip.

[0003] In the testing process, in order to ensure the integrity of the chip function, the output performance of the final test (FT) chip can be optimized, therefore, how to accurately optimize the output characteristics of the chip has become a problem to be solved.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present application, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0005] The present application provides a chip testing method, device, equipment and medium, which at least partly overcomes the problem of being unable to accurately optimize the output performance of the chip.

[0006] Other characteristics and advantages of the present application will become apparent from the following detailed description, or will be learned by practice of the present application.

[0007] According to one aspect of the present application, a chip testing method is provided, comprising:

[0008] Obtaining an estimated offset of an output characteristic of a to-be-tested chip by a target testing process, wherein the target testing process is a chip testing process that affects the output characteristic of the to-be-tested chip;

[0009] Adjusting the output characteristic of the to-be-tested chip by using a target chip fusing scheme corresponding to the estimated offset, so that the actual output value of the output characteristic of the to-be-tested chip after the characteristic adjustment exists an offset compensation amount corresponding to the estimated offset compared with the standard value of the output characteristic, and the offset compensation amount is opposite to the offset direction of the estimated offset,

[0010] Wherein, the offset compensation amount is used to compensate the actual output characteristic offset generated by the to-be-tested chip after the characteristic adjustment in the target testing process.

[0011] In one embodiment, obtaining the estimated offset of the output characteristic of the to-be-tested chip by the target testing process comprises:

[0012] acquiring a plurality of historical output characteristic offset data, wherein each historical output characteristic offset data is used to reflect a variation of an output characteristic of a reference chip before and after a target test process is performed;

[0013] determining an estimated offset according to the plurality of historical output characteristic data.

[0014] In one embodiment, the clock signal of the reference chip comprises a first clock sub-signal and a second clock sub-signal, and each historical output characteristic offset data comprises a duty cycle offset of the first clock sub-signal and a duty cycle offset of the second clock sub-signal of the corresponding reference chip;

[0015] determining an estimated offset according to the plurality of historical output characteristic data, comprising:

[0016] determining a duty cycle offset mean value of the first clock sub-signal according to the duty cycle offset of the first clock sub-signal in the plurality of historical output characteristic offset data;

[0017] determining a duty cycle offset mean value of the second clock sub-signal according to the duty cycle offset of the second clock sub-signal in the plurality of historical output characteristic offset data;

[0018] calculating a difference between the duty cycle offset mean value of the first clock sub-signal and the duty cycle offset mean value of the second clock sub-signal to obtain the estimated offset.

[0019] In one embodiment, the duty cycle offset mean value of the first clock sub-signal is calculated according to the duty cycle offset of the first clock sub-signal in the plurality of historical output characteristic offset data, comprising:

[0020] performing normal distribution statistics on the duty cycle offset of the first clock sub-signal in the plurality of historical output characteristic offset data to obtain the duty cycle offset mean value of the first clock sub-signal;

[0021] and / or,

[0022] The duty cycle offset mean value of the second clock sub-signal is calculated according to the duty cycle offset of the second clock sub-signal in the plurality of historical output characteristic offset data, comprising:

[0023] performing normal distribution statistics on the duty cycle offset of the second clock sub-signal in the plurality of historical output characteristic offset data to obtain the duty cycle offset mean value of the second clock sub-signal.

[0024] In one embodiment, the clock signal of the reference chip comprises a first clock sub-signal and a second clock sub-signal, each of the historical output characteristic offset data comprises an offset difference between an actual offset of the corresponding reference chip after performing the target test process and an actual offset of the corresponding reference chip before performing the target test process, wherein the actual offset is a duty cycle offset of the first clock sub-signal relative to the second clock sub-signal.

[0025] According to the plurality of historical output characteristic data, an estimated offset is calculated, comprising:

[0026] The offset difference in the plurality of historical output characteristic offset data is calculated to obtain the estimated offset.

[0027] In one embodiment, before adjusting the output characteristic of the to-be-tested chip by using the target chip fusing scheme corresponding to the estimated offset, the method further comprises:

[0028] Obtaining an initial measurement value of the output characteristic of the to-be-tested chip;

[0029] According to the initial measurement value and the estimated offset, a target chip fusing scheme is selected from the plurality of chip fusing schemes.

[0030] In one embodiment, each of the chip fusing schemes is used to fuse at least one electrically programmable fuse in the to-be-tested chip,

[0031] According to the initial measurement value and the estimated offset, a target chip fusing scheme is selected from the plurality of chip fusing schemes, comprising:

[0032] For each of the chip fusing schemes, an output characteristic adjustment amount corresponding to each of the chip fusing schemes is obtained, and a sum of the initial measurement value and the output characteristic adjustment amount of each of the chip fusing schemes is calculated to obtain an adjusted output amount of the output characteristic of the to-be-tested chip under adjustment of each of the chip fusing schemes;

[0033] According to the adjusted output amount corresponding to each of the plurality of chip fusing schemes and the estimated offset, a target chip fusing scheme is selected from the plurality of chip fusing schemes.

[0034] In one embodiment, the clock signal of the to-be-tested chip comprises a first clock sub-signal and a second clock sub-signal of the to-be-tested chip,

[0035] The adjusted output amount corresponding to each of the chip fusing schemes comprises a duty cycle output value of the first clock sub-signal and a duty cycle output value of the second clock sub-signal;

[0036] According to the adjusted output amount corresponding to each of the plurality of chip fusing schemes and the estimated offset, a target chip fusing scheme is selected from the plurality of chip fusing schemes, comprising:

[0037] For each chip fusing scheme, the following steps are performed:

[0038] An absolute difference value between the duty cycle output value of the second clock sub-signal under each chip fusing scheme and the estimated offset is calculated to obtain a first absolute difference value;

[0039] A difference between the first absolute difference value and an absolute value of the duty cycle output value of the first clock sub-signal under each chip fusing scheme is calculated to obtain a second difference value corresponding to each chip fusing scheme;

[0040] The chip fusing scheme corresponding to the minimum second difference value in the second difference values corresponding to the plurality of chip fusing schemes is determined as the target chip fusing scheme.

[0041] In an embodiment, each chip fusing scheme is used to fuse at least one electrically programmable fuse in the to-be-tested chip,

[0042] According to the initial measurement value and the estimated offset, a target chip fusing scheme is selected from the plurality of chip fusing schemes, including:

[0043] According to the estimated offset, a target output value of the output characteristic of the to-be-tested chip is calculated;

[0044] According to the target output value and the initial measurement value, a target characteristic adjustment value is obtained;

[0045] For each chip fusing scheme, an output characteristic adjustment amount corresponding to each chip fusing scheme is obtained, and in a case where each chip fusing scheme and the target characteristic adjustment value satisfy a preset scheme selection condition, each chip fusing scheme is taken as a target characteristic adjustment scheme.

[0046] In an embodiment, the output characteristic of the to-be-tested chip is adjusted by using the target chip fusing scheme corresponding to the estimated offset, including:

[0047] Among the plurality of electrically programmable fuses of the to-be-tested chip, an electrically programmable fuse corresponding to the target chip fusing scheme is determined;

[0048] The electrically programmable fuse corresponding to the target chip fusing scheme is fused.

[0049] In an embodiment, after the output characteristic of the to-be-tested chip is adjusted by using the chip fusing scheme corresponding to the target output value, the method further includes:

[0050] A target test process is performed on the to-be-tested chip after the characteristic adjustment to obtain a to-be-tested chip meeting a characteristic parameter requirement.

[0051] In one embodiment, after adjusting the output characteristics of the DUT chip by using the target chip fuse scheme corresponding to the estimated offset, and before performing the target test process on the characteristic-adjusted DUT chip, the method further comprises:

[0052] obtaining actual fuse states of the plurality of electrically programmable fuses of the characteristic-adjusted DUT chip;

[0053] determining whether the actual fuse states are consistent with the fuse states corresponding to the target chip fuse scheme;

[0054] performing the target test process on the characteristic-adjusted DUT chip, including:

[0055] performing the target test process on the characteristic-adjusted DUT chip in the case where the actual fuse states are consistent with the fuse states corresponding to the target chip fuse scheme.

[0056] In one embodiment, the target test process is a stress-related test process, and the target test process includes a reflow soldering process and / or an aging test.

[0057] According to another aspect of the present application, a chip testing device is provided, including:

[0058] an offset obtaining module configured to obtain an estimated offset of a target test process on output characteristics of a DUT chip, wherein the target test process is a chip testing process that has an impact on the output characteristics of the DUT chip;

[0059] a characteristic adjusting module configured to adjust the output characteristics of the DUT chip by using a target chip fuse scheme corresponding to the estimated offset, so that an actual output value of the output characteristics of the characteristic-adjusted DUT chip has an offset compensation amount corresponding to the estimated offset relative to a standard value of the output characteristics, and the offset compensation amount is opposite in offset direction to the estimated offset,

[0060] wherein the offset compensation amount is used to compensate for an actual output characteristic offset of the characteristic-adjusted DUT chip during the target test process.

[0061] According to still another aspect of the present application, an electronic device is provided, including: a processor; and a memory configured to store executable instructions of the processor; wherein the processor is configured to perform the above-described chip testing method by executing the executable instructions.

[0062] According to yet another aspect of the present application, a computer readable storage medium is provided, having stored thereon a computer program, which, when executed by a processor, implements the above-described chip testing method.

[0063] According to still another aspect of the present application, a computer program product is provided, comprising a computer program, characterized in that the computer program, when executed by a processor, implements the chip testing method as described above.

[0064] The chip testing method, device, equipment and medium provided by the embodiments of the present application can first acquire the estimated offset of the output characteristic of the to-be-tested chip under the target test process, and adjust the output characteristic of the to-be-tested chip through the target chip fusing scheme, so that the actual output value of the output characteristic of the to-be-tested chip after the characteristic adjustment can have an offset compensation amount compared with the standard value of the output characteristic. Since the offset compensation amount and the estimated offset are in opposite directions, the offset compensation amount can be used to compensate for the actual output characteristic offset generated in the actual execution process of the target test process after the fusing process, so that the output characteristic of the to-be-tested chip after the compensation is equal to or close to the standard value of the output characteristic, thereby realizing accurate optimization of the chip output characteristic.

[0065] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and are not limiting to the present application. BRIEF DESCRIPTION OF DRAWINGS

[0066] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application. It is apparent that the accompanying drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0067] Figure 1 A timing sequence diagram of a clock signal of a chip provided by an embodiment of the present application is shown;

[0068] Figure 2 A simulation diagram of a distribution curve of an exemplary chip output characteristic provided by an embodiment of the present application is shown;

[0069] Figure 3 A simulation diagram of distribution curves of a chip output characteristic before and after fusing in the related art is shown;

[0070] Figure 4 A flowchart of a chip testing method in an embodiment of the present application is shown;

[0071] Figure 5 A simulation diagram of a distribution curve of an exemplary duty cycle offset of a first clock sub-signal provided by an embodiment of the present application is shown;

[0072] Figure 6A simulation schematic diagram of a distribution curve of a duty cycle offset of an exemplary second clock sub-signal is shown.

[0073] Figure 7 A simulation schematic diagram of distribution curves of output characteristics of a chip before and after a reflow soldering process in the related art is shown.

[0074] Figure 8 A simulation schematic diagram of distribution curves of output characteristics of a chip before and after a reflow soldering process in an embodiment of the present application is shown.

[0075] Figure 9 A flowchart of another chip testing method provided by an embodiment of the present application is shown.

[0076] Figure 10 An adjustment schematic diagram of an exemplary chip fusing scheme provided by an embodiment of the present application is shown.

[0077] Figure 11 A flowchart of yet another chip testing method provided by an embodiment of the present application is shown.

[0078] Figure 12 A timing sequence change schematic diagram of a clock signal in an exemplary chip testing process provided by an embodiment of the present application is shown.

[0079] Figure 13 A schematic diagram of a chip testing apparatus in an embodiment of the present application is shown.

[0080] Figure 14 A structural block diagram of an electronic device in an embodiment of the present application is shown.

[0081] Figure 15 A schematic diagram of a computer readable storage medium in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0082] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations may, however, be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example implementations to those skilled in the art. The features, structures, or characteristics described in connection with the examples can be combined in any suitable manner in one or more implementations.

[0083] In addition, the accompanying drawings are included to provide a thorough understanding of embodiments of the application and are not intended to be exhaustive or to limit the application to the precise outline described herein. The same or similar reference numerals in different drawings represent the same or similar elements.

[0084] It should be understood that each of the steps recited in the method embodiments of the present application can be performed in different orders and / or in parallel. In addition, the method embodiments can include additional steps and / or omit performing the steps shown. The scope of the present application is not limited in this respect.

[0085] It should be noted that the terms "first", "second", and the like in the present application are only used to distinguish different devices, modules or units, and are not intended to limit the order or interdependence of the functions performed by these devices, modules or units.

[0086] It should be noted that the adjectives "one", "multiple" mentioned in the present application are illustrative and not limiting, and those skilled in the art should understand that "one or more" should be understood unless the context clearly indicates otherwise.

[0087] In the production process of semiconductor chips, in order to ensure the quality of semiconductor chips, the chips are often tested at the last link before delivery.

[0088] In the production process of chips, if there are process deviations, circuit mismatches, and chip production batches, etc., which may cause the output performance of the chips such as MOS (Metal Oxide Semiconductor, Metal-Oxide Semiconductor Field Effect Transistor) electrical performance to deviate, the transmission quality of the chip digital signal may be affected. Since there is often high-speed signal transmission inside the chip and between chips, if the quality of the clock signal output by the chip is poor, the corresponding device of the chip may be unstable, the function may be executed incorrectly or even fail. For example, if the output characteristics of the chip are poor, the memory module such as Dual In-line Memory Module (DIMM) may fail when working.

[0089] Therefore, how to accurately optimize the output characteristics of the chip has become one of the problems to be solved.

[0090] In order to facilitate understanding of the technical solutions provided by the embodiments of the present application, the technical terms related to the embodiments of the present application are first explained.

[0091] (1) Final Test (FT), referred to as FT test, is a performance test for a packaged chip, which is used to detect the process level of packaging. In the FT test, a chip under test can be subjected to a fuse process, a reflow soldering process, an aging test process, etc.

[0092] (2) Output characteristic, which can refer to the performance of an output content of a semiconductor chip, such as an output signal.

[0093] In some embodiments of the present application, the output characteristic can include the output performance of a clock signal of a chip.

[0094] Next, the output characteristic of a chip will be described in combination with a clock signal of the chip.

[0095] In one example, Figure 1 A timing diagram of a clock signal of a chip provided by an embodiment of the present application is shown.

[0096] As Figure 1 shown, the clock signal can include a first clock sub-signal (i.e., the duty cycle is related to the "ODD" timing segment width in the 180-degree mode) as shown by the dashed line 11, and a second clock sub-signal (i.e., the duty cycle is related to the "EVEN" timing segment width in the 180-degree mode) as shown by the solid line 12. Figure 1 Figure 1 Accordingly, the output characteristic of the chip can include the duty cycle of the first clock sub-signal and / or the duty cycle of the second clock sub-signal.

[0097] Accordingly, the output characteristic of the chip can include the duty cycle of the first clock sub-signal and / or the duty cycle of the second clock sub-signal.

[0098] (3) The offset of the output characteristic, which can be used to represent the deviation of the actual value of the output characteristic from the standard value of the output characteristic. Next, taking the output characteristic including the duty cycle of the first clock sub-signal and the duty cycle of the second clock sub-signal of the clock signal as an example, the offset of the output characteristic will be described in multiple examples.

[0099] In one example, the offset of the output characteristic can be the difference between the duty cycle of the first clock sub-signal and the duty cycle of the second clock sub-signal.

[0100] Next, the distribution curve of the output characteristic of the chip will be described in combination with Figure 2 . Figure 2 A simulation diagram of an exemplary distribution curve of the output characteristic of a chip provided by an embodiment of the present application is shown.

[0101] As Figure 2 shown, the distribution curve of the duty cycle of the first clock sub-signal is shown by the solid line 21, and the duty cycle of the second clock sub-signal is shown by the dashed line 22. The center value D ODD ​Duty cycle of the first clock sub-signal, the center value D of the distribution curve corresponding to the dashed line 22 EVEN Duty cycle of the second clock sub-signal.

[0102] The distance x in the horizontal axis direction between the distribution curve corresponding to the solid line 21 and the distribution curve corresponding to the dashed line 22 represents the offset of the output characteristic of the chip under test. For example, if the duty cycle of the first clock sub-signal is 40% and the duty cycle of the second clock sub-signal is 60%, the offset of the output characteristic of the chip under test can be the difference between 40% and 60%, that is, equal to -20%. For another example, if the duty cycle of the first clock sub-signal is 60% and the duty cycle of the second clock sub-signal is 40%, the offset of the output characteristic of the chip under test can be +20%.

[0103] It should be noted that the offset of the output characteristic of the chip under test can also be equal to the difference between the duty cycle of the second clock sub-signal and the duty cycle of the first clock sub-signal, which will not be described in detail.

[0104] In another example, the offset of the output characteristic can be the difference between the actual duty cycle of the first clock sub-signal and the standard duty cycle of the first clock sub-signal. For example, the standard duty cycle of the first clock sub-signal can be 50%. For example, if the duty cycle of the first clock sub-signal is 40%, the offset of the output characteristic of the chip under test can be -10%.

[0105] In yet another example, the offset of the output characteristic can be the difference between the actual duty cycle of the second clock sub-signal and the standard duty cycle of the second clock sub-signal. For example, the standard duty cycle of the second clock sub-signal can be 50%. For example, if the duty cycle of the second clock sub-signal is 60%, the offset of the output characteristic of the chip under test can be +10%.

[0106] It should be noted that, for the convenience of illustration, the following parts of the embodiments of the present application will be illustrated in units of duty cycles, but it should be understood that the various offsets or offset compensation amounts in the embodiments of the present application can also be in units of time, such as in units of ps (picoseconds), which will not be specifically limited.

[0107] After introducing the technical terms related to the embodiments of the present application, the technical solutions related to the embodiments of the present application will be described in the following.

[0108] In a related technology, in order to optimize the output characteristic of the chip, the output performance of the chip can be improved by fusing the electrically programmable fuse (E_fuse) of the chip in the FT test, so that the output characteristic of the chip after the fusing process meets the characteristic parameter requirements.

[0109] Specifically, as Figure 1As shown, before the fusing, the duty cycle of the first clock sub-signal and the duty cycle of the second clock sub-signal are too different. Through the fusing process, the duty cycle of the first clock sub-signal and the duty cycle of the second clock sub-signal can be adjusted to the same value or approximately the same value.

[0110] Exemplarily, Figure 3 A simulation diagram of the distribution curves of the output characteristics of the chip in the related art before and after the fusing is shown. Among them, Figure 3 As Figure 1 A simulation diagram of the distribution curves of the duty cycles of the first clock sub-signal and the second clock sub-signal in the clock signal is shown.

[0111] As Figure 3 shown, before the chip performs the fusing process, the distribution curve of the duty cycle of the first clock sub-signal is shown as a solid line 21A, and the distribution curve of the duty cycle of the second clock sub-signal is shown as a dashed line 22A. Since the center value of each distribution curve represents the duty cycle of the clock sub-signal corresponding to the distribution curve, by comparing the solid line 21A and the dashed line 22A, it can be known that the center values of the two are a certain distance apart, and accordingly, the duty cycle of the first clock sub-signal and the duty cycle of the second clock sub-signal have a certain deviation before the fusing process.

[0112] And, after the fusing process, the distribution curve of the duty cycle of the first clock sub-signal is shown as a solid line 21B, and the distribution curve of the duty cycle of the second clock sub-signal is shown as a dashed line 22B. By comparing the solid line 21B and the dashed line 22B, it can be known that the center values of the two are basically the same, that is, after the fusing process, the duty cycle of the first clock sub-signal and the duty cycle of the second clock sub-signal can be adjusted to almost overlap.

[0113] Accordingly, it can be known that the related art can adjust the output characteristics of the chip to a better state after the fusing process. Figure 3

[0114] However, the inventors found through research that the high temperature and high pressure test conditions after the fusing process can cause changes in the output characteristics of the chip, such as duty cycle shift, and that processes such as reflow soldering after the fusing process can cause the output characteristics of the chip to shift, thereby affecting the preparation quality of the chip.

[0115] The above related art does not consider the influence of the test process after the fusing process on the output characteristics of the chip, and cannot accurately optimize the output characteristics of the chip.

[0116] ​Based on this, the embodiment of the present application provides a chip testing scheme, which can be applied to a chip testing scene, such as a chip FT testing scene. In the embodiment of the present application, the actual output value of the output characteristic of the to-be-tested chip can be offset by a compensation amount compared with the standard value of the output characteristic through the fusing processing, and then in the target testing process after the fusing processing, the actual output characteristic offset amount generated in the actual execution process of the target testing process can be compensated by using the compensation amount, so that the output characteristic of the to-be-tested chip after compensation is equal to or close to the standard value of the output characteristic, thereby realizing accurate optimization of the chip output characteristic.

[0117] The present example embodiment will be described in detail below in combination with the accompanying drawings and examples.

[0118] First, the embodiment of the present application provides a chip testing method, which can be executed by software or hardware equipment. Exemplarily, the method can be executed by an automatic testing equipment of a chip.

[0119] Figure 4 A flow chart of a chip testing method in the embodiment of the present application is shown, as shown in the figure, the chip testing method provided in the embodiment of the present application includes the following steps S410 and S420. Figure 4

[0120] S410, obtaining an estimated offset amount of a target testing process to the output characteristic of a to-be-tested chip.

[0121] In order to facilitate S410, the following part first explains the terms involved in S410.

[0122] For the to-be-tested chip, it can be a chip that is prepared to perform fusing processing on it.

[0123] For the target testing process, it can be a chip testing process performed after the fusing processing and affecting the output characteristic of the to-be-tested chip.

[0124] In some embodiments, the target testing process is a pressure-related testing process. Exemplarily, the target testing process includes at least one of the following: reflow soldering process, aging test. Among them, for the reflow soldering process, it can refer to a process of fixing a packaged chip on a memory module such as DIMM. Exemplarily, the reflow soldering process can be infrared reflow soldering (IR Reflow). It should be noted that the reflow soldering process can also be other reflow soldering processes, which are not specifically limited.

[0125] ​In this embodiment, since pressure-related testing processes can affect the chip's output characteristics, by using pressure-related testing processes as the target testing processes, the offset compensation amount generated during the melting process can fully compensate for the actual output characteristic offset generated by the pressure-related testing processes, thereby improving the accuracy of output characteristic adjustment.

[0126] It should be noted that the target testing process can also be other processes that can affect the chip's output characteristics. For example, if high temperature will affect the chip's output characteristics, the target testing process can also include testing processes under high-temperature environments.

[0127] After introducing the target testing process, the estimated offset will be explained next.

[0128] The estimated offset can be the result of predicting the offset of the output characteristics of the chip under test caused by the target test process.

[0129] In some embodiments, the estimated offset can be the estimated difference between the duty cycle offset of the first clock sub-signal and the duty cycle offset of the second clock sub-signal. The duty cycle offset of any sub-signal among the first and second clock sub-signals can refer to the difference between the duty cycle of that arbitrary sub-signal after the target test process is executed and the duty cycle of that arbitrary sub-signal before the target test process is executed.

[0130] In other embodiments, the estimated offset can be the estimated difference between the duty cycle offset of the chip after performing the target test process and the duty cycle offset before performing the target test process. Here, the duty cycle offset is the duty cycle offset of the first clock sub-signal relative to the second clock sub-signal. For example, if the duty cycle of the first clock sub-signal is 40% and the duty cycle of the second clock sub-signal is 60%, then the duty cycle deviation between the two is -20%, i.e., the actual offset is -20%. It should be noted that the duty cycle offset of the second clock sub-signal relative to the first clock sub-signal can also be selected as the actual offset according to the actual situation; there is no specific limitation on this.

[0131] After introducing the estimated offset, the S410 will be explained in detail below in conjunction with the estimated offset.

[0132] In some embodiments, the estimated offset may be calculated based on historical data.

[0133] Accordingly, S410 may include the following steps A1 and A2.

[0134] Step A1: Obtain multiple historical output characteristic offset data.

[0135] For the historical output characteristic offset data, it is used to reflect the actual change amount of the output characteristic of a reference chip before and after the target test process is performed. The reference chip can be a chip that has actually performed the target test process. For example, for a reference chip, an output characteristic parameter can be obtained before the target test process is performed on the reference chip, and an output characteristic parameter can be obtained after the target test process is performed on the reference chip, and the historical output characteristic offset data of the reference chip can be obtained by using the two obtained output characteristic parameters.

[0136] In one example, the historical output characteristic offset data can include that each historical output characteristic offset data includes the duty cycle offset amount of the first clock sub-signal of the corresponding reference chip and the duty cycle offset amount of the second clock sub-signal.

[0137] In another example, the historical output characteristic offset data includes the actual duty cycle offset amount of the corresponding reference chip after the target test process is performed and the duty cycle offset amount before the target test process is performed.

[0138] In yet another example, the historical output characteristic offset data includes the difference between the actual duty cycle offset amount of the corresponding reference chip after the target test process is performed and the duty cycle offset amount before the target test process is performed.

[0139] It should be noted that the historical output characteristic offset data can also be other data that can directly reflect or can be obtained by data processing to reflect the actual change amount of the output characteristic of the reference chip before and after the target test process is performed, and the embodiments of the present application do not make specific limitations.

[0140] For the number of historical output characteristic offset data, it can be changed according to actual conditions and specific requirements. For example, the historical output characteristic offset data of 400 reference chips can be obtained, and the specific number of historical output characteristic offset data in step A1 is not limited.

[0141] Step A2, determining the estimated offset amount according to the plurality of historical output characteristic data.

[0142] In step A2, the plurality of historical output characteristic data can be processed to obtain the estimated offset amount. The data processing can include data operation and / or statistical analysis, and the like, and no specific details are described.

[0143] In one example, step A2 can include steps A21 to A23.

[0144] Step A21, determining the duty cycle offset amount mean of the first clock sub-signal according to the duty cycle offset amount of the first clock sub-signal in the plurality of historical output characteristic offset data.

[0145] The duty cycle offset of the first clock signal can refer to the difference between the duty cycle of the first clock signal after the target test process is performed and the duty cycle of the first clock signal before the target test process is performed. For example, if the duty cycle of the first clock signal is 55% before the reflow soldering is performed and is changed to 45% after the reflow soldering is performed, it can be determined that the duty cycle offset of the first clock signal is -10%.

[0146] The mean value of the duty cycle offset of the first clock signal can be used to reflect the central tendency of the duty cycle offsets of the plurality of first clock signals.

[0147] Exemplarily, the step A21 can include the following step A211.

[0148] In the step A211, the duty cycle offset of the first clock signal in the plurality of historical output characteristic offset data is subjected to normal distribution statistics, and a mean value of the duty cycle offset of the first clock signal is obtained through the statistics.

[0149] In the step A211, the duty cycle offset of the first clock signal in the plurality of historical output characteristic offset data can be input into a distribution statistical tool, and a statistical result including the mean value of the duty cycle offset of the first clock signal is output.

[0150] For example, Figure 5 An exemplary simulation diagram of a distribution curve of the duty cycle offset of the first clock signal is shown. According to the simulation diagram, the mean value of the duty cycle offset of the first clock signal can be calculated. Figure 5 The mean value of the duty cycle offset of the first clock signal can be calculated as -17.01587 (unit: %).

[0151] Through the step A211, the mean value of the duty cycle offset of the first clock signal can be accurately calculated according to the distribution characteristics of the duty cycle offsets of the first clock signals of the plurality of reference chips through the normal distribution statistics, and the calculation accuracy of the duty cycle offset of the first clock signal is improved.

[0152] It should be noted that, in addition to the normal distribution statistics, other data processing methods such as formula calculation can also be used to calculate the mean value of the duty cycle offset in the step A21, and the calculation method is not limited.

[0153] In the step A22, a mean value of the duty cycle offset of the second clock signal is determined according to the duty cycle offsets of the second clock signals in the plurality of historical output characteristic offset data.

[0154] Exemplarily, the step A22 can include the following step A221.

[0155] Step A221, statistically normal distribution of the duty cycle offset of the second clock sub-signal in the plurality of historical output characteristic offset data, and the statistical duty cycle offset of the second clock sub-signal is obtained.

[0156] For example, Figure 6 An exemplary simulation diagram of the distribution curve of the duty cycle offset of the second clock sub-signal is shown. According to the simulation diagram, the duty cycle offset of the second clock sub-signal is calculated. Figure 6 The duty cycle offset of the second clock sub-signal is calculated.

[0157] It should be noted that in addition to the normal distribution statistics, the duty cycle offset mean value can also be calculated by other statistical methods in step A22, which is not limited.

[0158] Through step A221, the duty cycle offset mean value of the second clock sub-signal can be accurately calculated according to the distribution characteristics of the duty cycle offset of the second clock sub-signal of the plurality of reference chips by means of normal distribution statistics, and the calculation accuracy of the duty cycle offset of the second clock sub-signal is improved.

[0159] It should be noted that the specific content of step A22 and step A221 is similar to step A21 and step A211, which can be referred to the above related description, and will not be repeated here.

[0160] Step A23, calculating the difference between the duty cycle offset mean value of the first clock sub-signal and the duty cycle offset mean value of the second clock sub-signal to obtain the estimated offset.

[0161] Continuing the above example, the duty cycle offset mean value of the second clock sub-signal is 21.15873 (about equal to 21.2), and the duty cycle offset mean value of the first clock sub-signal is-17.01587 (about equal to-17.0), then the estimated offset is-38.2 (unit: %).

[0162] Through the above steps A21 to A23, the duty cycle offset mean value of the first clock sub-signal and the duty cycle offset mean value of the second clock sub-signal can be calculated respectively, and since the duty cycle offset mean value of the first clock sub-signal can accurately estimate the offset of the first clock sub-signal of the to-be-tested chip before and after the target test process, and the duty cycle offset mean value of the second clock sub-signal can accurately estimate the offset of the second clock sub-signal of the to-be-tested chip before and after the target test process, the estimated offset can be accurately estimated according to the difference between the two, and the calculation accuracy of the estimated offset is improved.

[0163] In other embodiments, step A2 can include the following step A24.

[0164] In step A24, the difference between the actual shift of the reference chip after performing the target test process and the actual shift of the reference chip before performing the target test process is calculated from the plurality of historical output characteristic shift data to obtain the estimated shift. The actual shift is the duty cycle shift of the first clock sub-signal relative to the second clock sub-signal.

[0165] It should be noted that in step A24, the estimated shift can be calculated from the plurality of difference values by means such as normal distribution statistics, data operation, etc. The specific data processing method is not limited. For example, it can be mean calculation or other indicators that can reflect the central tendency of the plurality of historical output characteristic shift data, which is not limited.

[0166] Through the above step A24, since the difference between the actual shift of the reference chip after performing the target test process and the actual shift of the reference chip before performing the target test process can represent the actual output characteristic deviation of the corresponding reference chip before and after performing the target test process, the estimated shift can be accurately estimated according to the plurality of difference values.

[0167] Through the above steps A1 and A2, by using historical output characteristic data, the future estimated shift can be predicted from the past real measurement data according to historical and real output characteristic change data, the characteristic parameter shift of the to-be-tested chip under the influence of the target test process is accurately estimated, the accuracy of the estimation is improved, and the quality of the output characteristic is improved.

[0168] In some other embodiments, the estimated shift can also be an empirical value set according to actual conditions and specific requirements. It should be noted that in the embodiments of the present application, the estimated shift can also be determined by other means, such as using a neural network model, etc., which is not limited.

[0169] In some other embodiments, since the sum of the duty cycles of the first clock sub-signal and the second clock sub-signal can be 100%, when the duty cycle of the first clock sub-signal increases, the duty cycle of the second clock sub-signal can correspondingly decrease. Accordingly, in order to facilitate calculation, for any sub-signal of the first clock sub-signal and the second clock sub-signal, the difference between the actual duty cycle of the sub-signal after performing the target test process and the actual duty cycle of the sub-signal before performing the target test process can be taken as a historical output characteristic data. Accordingly, the estimated shift can include the estimated difference between the duty cycle of the first clock sub-signal after performing the target test process and the duty cycle of the first clock sub-signal before performing the target test process.

[0170] It should be noted that the estimated offset in this case can be calculated by means such as normal distribution statistics, data operation, etc. No specific limitation is made. For example, it can be mean calculation, or other indicators that can reflect the central tendency of multiple historical output characteristic offset data, without specific limitation.

[0171] After introducing S410, S420 is described next.

[0172] S420, using the target chip fuse scheme corresponding to the estimated offset, adjusts the output characteristics of the to-be-tested chip, so that the actual output value of the output characteristics of the to-be-tested chip after characteristic adjustment exists an offset compensation corresponding to the estimated offset compared with the standard value of the output characteristics.

[0173] For the chip fuse scheme, it is used to fuse at least one electrically programmable fuse in the to-be-tested chip to change the output characteristics of the to-be-tested chip.

[0174] For the offset compensation, the offset compensation is used to compensate the actual output characteristic offset generated by the to-be-tested chip in the target test process. The offset compensation is opposite to the offset direction of the estimated offset. That is, if the estimated offset is positive, the offset compensation can be negative.

[0175] It should be noted that due to the influence of fuse process precision, etc., the absolute value of the offset compensation and the absolute value of the estimated offset can be the same or different, without specific limitation. For example, if the estimated offset is 22%, but the offset compensation that can be achieved by the chip fuse is -20%, -10%, etc., the offset compensation after compensation that is closest to the standard value of the output characteristics can be selected as the offset compensation corresponding to the estimated offset compensation, that is, the offset compensation -20% can be selected as the offset compensation corresponding to the estimated offset 22%.

[0176] In one example, if the estimated offset is 20% (i.e. the duty cycle of the first clock sub-signal is 20% more than that of the second clock sub-signal), the actual output characteristic offset generated by the to-be-tested chip in the target test process is also 20%. The duty cycle of the first clock sub-signal of the to-be-tested chip after characteristic adjustment can be 40%, and the duty cycle of the second clock sub-signal can be 60% by means of output characteristic adjustment, i.e. the offset compensation is equal to -20%. Accordingly, after performing the target test process, the offset compensation -20% can offset the actual output characteristic offset 20% generated in the target test process, so that the duty cycle of the first clock sub-signal of the to-be-tested chip after performing the target test process is 50%, and the duty cycle of the second clock sub-signal is 50%.

[0177] In some embodiments, S420 can include the following Step B1 and Step B2.

[0178] Step B1, among the plurality of electrically programmable fuses of the to-be-tested chip, determine the electrically programmable fuse corresponding to the target chip fusing scheme.

[0179] In one example, the correspondence between the target chip fusing scheme and the electrically programmable fuse can be recorded in advance. The correspondence can be a correspondence table or a correspondence relationship, which is not limited herein.

[0180] Correspondingly, in Step B1, the correspondence between the target chip fusing scheme and the electrically programmable fuse can be determined by using the correspondence.

[0181] Step B2, fuse the electrically programmable fuse corresponding to the target chip fusing scheme.

[0182] In Step B2, the electrically programmable fuse can be fused by programming.

[0183] In one example, each bit in the fuse programming bits can correspond to an electrically programmable fuse in the chip. For example, 0 represents fusing, and 1 represents not fusing.

[0184] Through Step B1 and Step B2, the output characteristics of the to-be-tested chip can be adjusted by using the target chip fusing scheme, thereby ensuring the flexibility of the adjustment.

[0185] It should be noted that, in addition to adjusting the output characteristics of the chip by using the electrically programmable fuse, other fusing schemes that can adjust the output characteristics of the packaged chip can also be used, which are not limited herein.

[0186] The chip testing method provided by the embodiments of the present application can first obtain the estimated offset of the output characteristics of the to-be-tested chip under the target testing process, and adjust the output characteristics of the to-be-tested chip by using the target chip fusing scheme, so that the actual output value of the output characteristics of the to-be-tested chip after the characteristic adjustment can have an offset compensation amount compared with the standard value of the output characteristics. Since the offset compensation amount and the estimated offset are in opposite directions, the actual output characteristic offset generated in the actual execution process of the target testing process can be compensated by using the offset compensation amount after the fusing process, so that the output characteristics of the to-be-tested chip after the compensation are equal to or close to the standard value of the output characteristics, thereby realizing accurate optimization of the output characteristics of the chip.

[0187] In order to facilitate understanding of the beneficial effects of the embodiments of the present application, the inventors will illustrate the following Figure 7 and Figure 8 Take the reflow soldering process as an example, which is described as follows.

[0188] Figure 7 A simulation diagram showing the distribution curves of the output characteristics of a chip in the prior art before and after the reflow soldering process is shown. The distribution curve of the duty cycle of the first clock sub-signal before the chip performs the fusing process is shown as a solid line 21C, and the distribution curve of the duty cycle of the second clock sub-signal is shown as a dashed line 22C. The distribution curve of the duty cycle of the first clock sub-signal after the chip performs the fusing process is shown as a solid line 21D, and the distribution curve of the duty cycle of the second clock sub-signal is shown as a dashed line 22D.

[0189] As shown in Figure 7 , if the duty cycles of the first clock sub-signal and the second clock sub-signal are adjusted to almost overlap after the fusing process (before the reflow soldering), then after the reflow soldering process, the output characteristics are affected by the reflow soldering process, and a large deviation occurs between the two, affecting the quality of the output characteristics.

[0190] Figure 8 A simulation diagram showing the distribution curves of the output characteristics of a chip in the embodiment of the present application before and after the reflow soldering process is shown. The distribution curve of the duty cycle of the first clock sub-signal before the chip performs the fusing process is shown as a solid line 21E, and the distribution curve of the duty cycle of the second clock sub-signal is shown as a dashed line 22E. The distribution curve of the duty cycle of the first clock sub-signal after the chip performs the fusing process is shown as a solid line 21F, and the distribution curve of the duty cycle of the second clock sub-signal is shown as a dashed line 22F.

[0191] As shown in Figure 8 , if the duty cycles of the first clock sub-signal and the second clock sub-signal are adjusted to have a deviation (deviation compensation) after the fusing process (before the reflow soldering), then after the reflow soldering process, the distance between the two is reduced or even close to overlap due to the influence of the reflow soldering process on the output characteristics, and the quality of the output characteristics is optimized.

[0192] By Figure 7 and Figure 8 comparison, the chip test method provided in the embodiment of the present application can optimize the output performance of the chip after the target test process, and improve the quality of chip preparation.

[0193] Figure 9 A flowchart of another chip test method provided in the embodiment of the present application is shown. The embodiment of the present application is optimized on the basis of the above-mentioned embodiments, and the embodiment of the present application can be combined with each optional scheme in one or more of the above-mentioned embodiments.

[0194] As shown in Figure 9As shown, the chip testing method provided in the embodiments of the present application includes the following steps S910 to S940.

[0195] S910, obtaining an estimated offset of an output characteristic of the chip to be tested with respect to a target testing process. The target testing process is a chip testing process that affects the output characteristic of the chip to be tested.

[0196] S910 is similar to S410, and the specific content of S410 can be referred to, and thus will not be described here again.

[0197] S920, obtaining an initial measurement value of the output characteristic of the chip to be tested.

[0198] The initial measurement value of the output characteristic of the chip to be tested is used to reflect the actual output characteristic of the chip to be tested before the fusing process is performed.

[0199] In one example, the initial measurement value can include a duty cycle measurement value of the first clock sub-signal of the chip to be tested before the fusing process, and / or a duty cycle measurement value of the second clock sub-signal of the chip to be tested before the fusing process.

[0200] In another example, the initial measurement value can include a difference between the duty cycle measurement value of the first clock sub-signal before the fusing process and the duty cycle measurement value of the second clock sub-signal before the fusing process.

[0201] It should be noted that the initial measurement value can also be other parameters that can reflect the actual output characteristic of the chip to be tested before the fusing process is performed, and no specific limitation is made.

[0202] S930, selecting a target chip fusing scheme from the plurality of chip fusing schemes according to the initial measurement value and the estimated offset.

[0203] In S930, the selected target chip fusing scheme can adjust the output characteristic of the chip to be tested based on the initial measurement value, so that the chip output characteristic after the characteristic adjustment exists with the estimated offset compared with the standard value of the output characteristic.

[0204] Each chip fusing scheme can fuse at least one of the plurality of electrically programmable fuses of the chip. Different chip fusing schemes require different electrically programmable fuses to be fused, and each chip fusing scheme corresponds to a different output characteristic adjustment amount. The output characteristic adjustment amount of each chip fusing scheme is the adjustment amount of the output characteristic of the chip using the chip fusing scheme. In some embodiments, the output characteristic adjustment amount corresponding to each chip fusing scheme can be determined according to a plurality of historical data, wherein each historical data can be the actual change amount of the chip output parameter before and after the chip is fused using the chip fusing scheme.

[0205] Exemplarily, in the case that the chip includes 4 electrically programmable fuses, the multiple chip blowing schemes are shown in Table 1. Wherein, Y represents blowing, and N represents not blowing. Exemplarily, the electrically programmable fuse E1 and the electrically programmable fuse E2 in Table 1 can be electrically programmable fuses for adjusting the rising edge of a signal in a duty cycle correction (DCC) circuit, and the electrically programmable fuse E3 and the electrically programmable fuse E4 can be electrically programmable fuses for adjusting the falling edge of a signal in the DCC circuit.

[0206] Table 1

[0207]

[0208] Next, the adjustment schematic diagram of an exemplary chip blowing scheme provided by the embodiment of the present application will be described in combination with Table 1 and Figure 10 The multiple chip blowing schemes will be described in detail. Figure 10 An adjustment schematic diagram of an exemplary chip blowing scheme provided by the embodiment of the present application is shown. Since the sum of the duty cycle of the second clock sub-signal and the duty cycle of the first clock sub-signal is a fixed value, for the convenience of description, Figure 10 Only the waveform diagram of the second clock sub-signal in one clock cycle is shown for simplification.

[0209] As shown in Table 1, when the default scheme P0 is adopted, the electrically programmable fuses in the chip under test can not be adjusted. Wherein, as shown in Figure 10 The waveform diagram of the first clock sub-signal when the default scheme P0 is adopted is shown by the solid line.

[0210] And for the scheme P1, the electrically programmable fuse 10 can be programmed, and the output characteristic of the chip under test can be reduced by 10 ps (picoseconds) on the basis of the default scheme. Continue to refer to Figure 10 The waveform of the second clock pulse is widened (the duty cycle of the second clock pulse is increased) in the scheme P1, and correspondingly, the waveform of the first clock pulse is narrowed (the duty cycle of the first clock pulse is reduced), so that the output characteristic of the chip under test (the duty cycle of the first clock pulse is compared with the duty cycle of the second clock pulse) is reduced.

[0211] And the adjustment modes of the schemes P2-P7 are similar to those of the scheme P1, which can be combined with Table 1, Figure 10 and the content of the scheme P1, which will not be described herein again.

[0212] It should be noted that the electrically programmable fuses included in the chip can not be limited to 4, and correspondingly, the chip blowing scheme can not be limited to Table 1 described above, which will not be described herein again. And it should be noted that the output characteristic adjustment amount can be a specific time (such as ps), or a duty cycle, which is not limited herein.

[0213] After the chip fusing scheme is explained, the specific implementation of S930 is explained through multiple examples next.

[0214] In some embodiments, S930 can include the following steps C1 and C2.

[0215] Step C1, for each chip fusing scheme, obtain the output characteristic adjustment amount corresponding to each chip fusing scheme, calculate the sum of the initial measurement value and the output characteristic adjustment amount of each chip fusing scheme, and obtain the adjustment output amount of the output characteristic of the chip under test under the adjustment of each chip fusing scheme.

[0216] The adjustment output amount is used to reflect the output characteristic of the chip under test after adjustment using the chip fusing scheme.

[0217] In one example, the adjustment output amount can be the duty cycle of the first clock pulse and the duty cycle of the second clock pulse.

[0218] Exemplarily, taking scheme P3 as an example, the output characteristic adjustment amount of scheme P3 is -30 ps (if the corresponding duty cycle adjustment amount is -30%), and if the initial measurement value includes: the duty cycle of the first clock pulse is 60%, and the duty cycle of the second clock pulse is 40%, then after adjustment using scheme P3, the adjustment output amount corresponding to chip fusing scheme P3 can include: the duty cycle of the first clock pulse is 45%, and the duty cycle of the second clock pulse is 55%.

[0219] And after adjustment using scheme P4, the adjustment output amount corresponding to chip fusing scheme P4 can include: the duty cycle of the first clock pulse is 40%, and the duty cycle of the second clock pulse is 60%.

[0220] It should be noted that the specific calculation method of other chip fusing schemes is similar to scheme P3, and will not be described again.

[0221] In another example, the adjustment output amount can be the deviation of the duty cycle of the first clock pulse compared to the duty cycle of the second clock pulse.

[0222] Continuing the previous example, the adjustment output amount corresponding to chip fusing scheme P3 can include: -10%. The adjustment output amount corresponding to chip fusing scheme P4 can include: -20%.

[0223] Step C2, according to the adjustment output amount corresponding to each of the multiple chip fusing schemes, and the estimated offset, select a target chip fusing scheme from the multiple chip fusing schemes.

[0224] In step C2, the output characteristic parameter after the adjustment output quantity is offset again by the estimated offset amount can be determined, and the chip fusing scheme closest to the standard value of the output characteristic after being offset again is selected as the target chip fusing scheme.

[0225] In one embodiment, when the adjustment output quantity corresponding to each chip fusing scheme includes the duty cycle output value of the first clock sub-signal and the duty cycle output value of the second clock sub-signal, step C2 can include steps C21 to C23.

[0226] In step C21, for each chip fusing scheme, the absolute difference between the duty cycle output value of the second clock sub-signal under each chip fusing scheme and the estimated offset amount is calculated to obtain a first absolute difference.

[0227] In step C22, for each chip fusing scheme, the difference between the first absolute difference and the absolute value of the duty cycle output value of the first clock sub-signal under each chip fusing scheme is calculated to obtain a second difference value corresponding to each chip fusing scheme.

[0228] For example, the second difference value Y can be represented by the following formula (1)

[0229] Y = |D EVEN1 -x|-|D ODD1 | (1)

[0230] wherein D EVEN1 represents the duty cycle output value of the second clock sub-signal, x represents the estimated offset amount, and D ODD1 represents the duty cycle output value of the first clock sub-signal.

[0231] For example, if D EVEN1 is 40% and D ODD1 is 60% under a certain chip fusing scheme, and the estimated offset amount is -20%, the calculated second absolute difference is 0.

[0232] In step C23, the chip fusing scheme corresponding to the minimum second difference value among the second difference values corresponding to the plurality of chip fusing schemes is determined as the target chip fusing scheme.

[0233] For example, if the second difference value corresponding to scheme P3 is the minimum among the second difference values corresponding to schemes P1 to P8, scheme P3 can be selected as the target chip fusing scheme.

[0234] Through steps C21 to C23, the chip fusing scheme that can make the chip output characteristic after the target test process is performed optimal can be accurately determined, and the shipment quality of the chip is improved.

[0235] In one embodiment, if the adjustment output of each chip fusing scheme is the deviation of the duty cycle of the first clock pulse compared to the duty cycle of the second clock pulse under the chip fusing scheme, step C2 can include step C24 and step C25.

[0236] Step C24, calculate the absolute value of the sum of the deviation and the estimated offset under the chip fusing scheme.

[0237] Step C25, among the absolute values of the sum of the deviations and the estimated offsets under the plurality of chip fusing schemes, select the chip fusing scheme corresponding to the minimum absolute value as the target chip fusing scheme.

[0238] Continuing the previous example, if the estimated offset is 20%, the sum of the deviation (-10%) of scheme P3 and the estimated offset (20%) is 10%. The sum of the deviation (-20%) of scheme P4 and the estimated offset (20%) is 0%. Accordingly, scheme P4 can be selected as the target chip fusing scheme.

[0239] It should be noted that other ways can be selected to select a suitable target chip fusing scheme according to actual conditions and specific needs, and no specific limitation is made.

[0240] Through the above steps C1 and C2, the adjustment output corresponding to each chip fusing scheme can be determined first, and the output characteristic parameter after the adjustment output is offset again by the estimated offset is predicted. The chip fusing scheme closest to the standard value of the output characteristic after the offset again is selected as the target chip fusing scheme, so that the most suitable chip fusing scheme can be selected by considering the influence of the target test process on the output characteristic, thereby improving the adjustment accuracy.

[0241] In other embodiments, S930 can include steps C3 to C5.

[0242] Step C3, according to the estimated offset, calculate the target output value of the output characteristic of the chip under test.

[0243] In one embodiment, the target output value of the output characteristic of the chip under test can be calculated according to the estimated offset and the standard value of the output characteristic.

[0244] Exemplarily, the offset of the target output value compared to the standard value can be equal to the opposite of the estimated offset, so that the offset between the target output value and the standard value can compensate or offset the actual output characteristic offset generated in the target test process.

[0245] For example, if the standard value of the output characteristic includes that the duty cycle of the first clock sub-signal and the duty cycle of the second clock sub-signal are both 50%, and the estimated offset is -20%, the duty cycle of the first clock sub-signal in the calculated target output value is 60%, and the duty cycle of the second clock sub-signal is 40%.

[0246] It should be noted that in the embodiments of the present application, different calculation methods can be used to calculate the target output value according to actual conditions and specific scenarios, and the specific calculation method of how to calculate the target output value is not limited.

[0247] Step C4, obtaining a target characteristic adjustment value according to the target output value and the initial measurement value.

[0248] The target characteristic adjustment value can refer to the adjustment amount of the output characteristic required to take the initial measurement value as the beginning and take the target output value as the adjustment target.

[0249] In one example, the first duty cycle difference between the first clock signal and the second clock signal in the initial measurement value can be obtained, and the second duty cycle difference between the first clock signal and the second clock signal in the target characteristic adjustment value can be obtained, and the difference between the second duty cycle difference and the first duty cycle difference is taken as the target characteristic adjustment value.

[0250] In another example, the third duty cycle difference between the first clock signal in the target characteristic adjustment value and the first clock signal in the initial measurement value, and the fourth duty cycle difference between the second clock signal in the target characteristic adjustment value and the second clock signal in the initial measurement value can be calculated, and the difference between the third duty cycle difference and the fourth duty cycle difference is taken as the target characteristic adjustment value.

[0251] It should be noted that other methods can also be used to calculate the target characteristic adjustment value according to the initial measurement value and the target output value, which are not limited.

[0252] Step C5, for each chip fusing scheme, obtaining the output characteristic adjustment amount corresponding to each chip fusing scheme, and taking each chip fusing scheme as a target characteristic adjustment scheme in the case that each chip fusing scheme and the target characteristic adjustment value meet a preset scheme selection condition.

[0253] The preset scheme selection condition can be a condition that needs to be met when the output characteristic adjustment amount of the chip fusing scheme can meet the adjustment requirement of the target characteristic adjustment value.

[0254] In one example, the preset scheme selection condition can include that the absolute difference between the target characteristic adjustment value and the output characteristic adjustment amount of the chip fusing scheme is the minimum value in the absolute differences corresponding to the plurality of chip fusing schemes.

[0255] Correspondingly, the step C5 can specifically include the following steps C51 and C52.

[0256] The step C51 obtains an output characteristic adjustment amount corresponding to each chip fusing scheme, and calculates an absolute difference value between the target characteristic adjustment value and the output characteristic adjustment amount of each chip fusing scheme.

[0257] For example, if the target characteristic adjustment value is -20%, and each 10ps corresponds to 10% duty cycle, the absolute difference values corresponding to the schemes P1-P8 are 10%, 0%, 10%, …, 60% in turn.

[0258] The step C52 determines the chip fusing scheme corresponding to the minimum absolute difference value among the absolute difference values corresponding to the multiple chip fusing schemes as the target chip fusing scheme.

[0259] Continuing the above example, since the absolute difference value corresponding to the scheme P2 is the minimum, the scheme P2 can be determined as the target chip fusing scheme.

[0260] In one example, the preset scheme selection condition can include that the output characteristic adjustment amount of the chip fusing scheme is closest to the target characteristic adjustment value among the output characteristic adjustment amounts of the multiple chip fusing schemes.

[0261] For example, if the target characteristic adjustment value is 27%, since the output characteristic adjustment amount (30%) of the scheme P7 is closest to the target characteristic adjustment value, the scheme P7 can be selected as the target chip fusing scheme.

[0262] Through the steps C3-C5, the fusing scheme that can make the output characteristic of the chip after the target test process optimal can be accurately determined, and the shipment quality of the chip is improved.

[0263] It should be noted that other ways can also be used to select a suitable target chip fusing scheme in the embodiments of the present application, and details are not described herein.

[0264] S940, adjusting the output characteristic of the to-be-tested chip by using the target chip fusing scheme corresponding to the estimated offset amount, so that the actual output value of the output characteristic of the to-be-tested chip after the characteristic adjustment exists an offset compensation amount corresponding to the estimated offset amount compared with the standard value of the output characteristic, and the offset compensation amount is opposite to the offset direction of the estimated offset amount, wherein the offset compensation amount is used to compensate the actual output characteristic offset amount generated by the to-be-tested chip in the target test process after the characteristic adjustment.

[0265] The S940 is similar to the S420, and details can be referred to the specific content of the S420, which are not described herein.

[0266] The chip testing method provided in the embodiments of the present application can first acquire the estimated offset of the output characteristic of the to-be-tested chip under the target testing process, and adjust the output characteristic of the to-be-tested chip by using the target chip fusing scheme, so that the actual output value of the output characteristic of the to-be-tested chip after the characteristic adjustment can have an offset compensation amount compared with the standard value of the output characteristic. Since the offset compensation amount is opposite to the estimated offset, the actual output characteristic offset generated in the actual execution process of the target testing process can be compensated by using the offset compensation amount after the fusing processing, so that the output characteristic of the to-be-tested chip after the compensation is equal to or close to the standard value of the output characteristic, thereby realizing accurate optimization of the chip output characteristic.

[0267] In addition, according to the embodiments of the present application, the initial measurement value of the output characteristic of the to-be-tested chip and the estimated offset can be used to flexibly select a suitable target chip fusing scheme from the preset multiple chip fusing schemes, so that the actual characteristic offset of each chip can be flexibly adjusted, thereby improving the chip quality.

[0268] Figure 11 A flowchart of another chip testing method provided in the embodiments of the present application is shown. The embodiments of the present application are optimized on the basis of the above-mentioned embodiments, and the embodiments of the present application can be combined with each optional scheme in one or more of the above-mentioned embodiments.

[0269] As shown in Figure 11 The chip testing method provided in the embodiments of the present application includes the following steps S1110 to S1130.

[0270] S1110, acquiring an estimated offset of an output characteristic of a to-be-tested chip under a target testing process, wherein the target testing process is a chip testing process that has an impact on the output characteristic of the to-be-tested chip.

[0271] S1110 is similar to S420, and the specific content of S420 can be referred to, which will not be repeated here.

[0272] S1120, adjusting the output characteristic of the to-be-tested chip by using a target chip fusing scheme corresponding to the estimated offset, so that the actual output value of the output characteristic of the to-be-tested chip after the characteristic adjustment has an offset compensation amount corresponding to the estimated offset compared with the standard value of the output characteristic, and the offset compensation amount is opposite to the offset direction of the estimated offset, wherein the offset compensation amount is used to compensate the actual output characteristic offset generated in the target testing process of the to-be-tested chip after the characteristic adjustment.

[0273] S1120 is similar to S420, and the specific content of S420 can be referred to, which will not be repeated here.

[0274] S1130, performing a target test process on the chip to be tested after the characteristic adjustment to obtain the chip to be tested meeting the characteristic parameter requirement.

[0275] For the characteristic parameter requirement, it can refer to the offset between the actual output characteristic of the chip to be tested after performing the target test process and the standard value of the output characteristic being within the preset offset tolerance.

[0276] In one example, in order to facilitate the understanding of the chip testing scheme provided by the embodiments of the present application, the following will be combined with Figure 12 The above will be described. Figure 12 An exemplary timing diagram of the clock signal in the chip testing process provided by the embodiments of the present application is shown.

[0277] As Figure 12 shown, before starting the fusing process, as shown in the waveform diagram 1201 of the clock signal in one clock cycle, the duty cycle of the second clock signal is small (less than 50%), and the duty cycle of the first clock is large (more than 50%). If the reflow soldering process increases the duty cycle deviation value of the first clock signal and the second clock signal, the duty cycle of the second clock signal can be adjusted to a value exceeding the standard duty cycle (50%) during the fusing process, and the duty cycle of the first clock signal can be adjusted to a value lower than the standard duty cycle (50%). Thus, when performing the reflow soldering process, the duty cycle of the first clock signal can be increased to a value close to 50%, and the duty cycle of the second clock signal can be reduced to a value close to 50%, so that the chip output characteristic after performing the reflow soldering process can meet the characteristic parameter requirement.

[0278] The chip testing method provided by the embodiments of the present application can first obtain the estimated offset of the target test process on the output characteristic of the chip to be tested, and adjust the output characteristic of the chip to be tested through the target chip fusing scheme, so that the actual output value of the output characteristic of the chip to be tested after the characteristic adjustment can have an offset compensation amount compared with the standard value of the output characteristic. Since the offset compensation amount and the estimated offset are opposite in direction, the offset compensation amount can be used to compensate the actual output characteristic offset generated in the actual execution process of the target test process after the fusing process, so that the output characteristic of the compensated chip to be tested is equal to or close to the standard value of the output characteristic, thereby realizing accurate optimization of the chip output characteristic.

[0279] In some embodiments of the present application, between S1120 and S1130, the method further comprises the following steps D1 and D2.

[0280] Step D1, obtaining the actual fusing state of the plurality of electrically programmable fuses of the chip to be tested after the characteristic adjustment.

[0281] Step D2, judging whether the actual fusing state is consistent with the fusing state corresponding to the target chip fusing scheme. That is, the correctness of the burning using the target chip fusing scheme can be judged.

[0282] Correspondingly, S1130 specifically includes the following step D3.

[0283] Step D3, in the case that the actual fusing state is consistent with the fusing state corresponding to the target chip fusing scheme, performing the target test process on the characteristic-adjusted test chip.

[0284] Exemplarily, if the target chip fusing scheme is scheme P7, if the electrically programmable fuses E2-E4 have all been fused, and the electrically programmable fuse E1 is in the unfused state, it is determined that the actual fusing state is consistent with the fusing state corresponding to the target chip fusing scheme.

[0285] Through the above steps D1 to D3, the accuracy of each test process can be ensured through the checking manner of the fusing state, thereby ensuring the chip quality. Alternatively, when the test chip is burned incorrectly, the electrically programmable fuses of the test chip can be reprogrammed, thereby improving the accuracy of chip preparation.

[0286] It should be noted that other ways can be used to verify the fusing accuracy in the embodiments of the present application, such as verifying the fusing accuracy by testing the actual offset change of the test chip before and after the fusing process, and whether the output characteristic adjustment amount corresponding to the target chip fusing scheme is consistent, which will not be described in detail.

[0287] Based on the same inventive concept, the embodiments of the present application also provide a chip testing device, as described in the following embodiments.

[0288] Figure 13 A schematic diagram of a chip testing device in the embodiments of the present application is shown, as shown in the figure, the chip testing device 1300 includes an offset amount acquisition module 1310 and a characteristic adjustment module 1320. Figure 13

[0289] The offset amount acquisition module 1310 is configured to acquire an estimated offset amount of a target test process on the output characteristic of the test chip, wherein the target test process is a chip test process that affects the output characteristic of the test chip.

[0290] The characteristic adjustment module 1320 is configured to adjust the output characteristic of the test chip using a target chip fusing scheme corresponding to the estimated offset amount, so that the actual output value of the output characteristic of the characteristic-adjusted test chip has an offset compensation amount corresponding to the estimated offset amount compared with the standard value of the output characteristic, and the offset compensation amount and the estimated offset amount are opposite in offset direction. ​

[0291] The offset compensation amount is used to compensate for an actual output characteristic offset of the characteristic-adjusted DUT in the target test process.

[0292] In one embodiment, the offset obtaining module 1310 includes a data obtaining unit and an offset determining unit.

[0293] The data obtaining unit is configured to obtain a plurality of historical output characteristic offset data, wherein each historical output characteristic offset data is used to reflect a variation of an output characteristic of a reference chip before and after a target test process.

[0294] The offset determining unit is configured to determine an estimated offset according to the plurality of historical output characteristic data.

[0295] In one embodiment, the clock signal of the reference chip includes a first clock sub-signal and a second clock sub-signal, and each historical output characteristic offset data includes a duty cycle offset of the first clock sub-signal and a duty cycle offset of the second clock sub-signal of the corresponding reference chip.

[0296] The data obtaining unit includes a first data processing sub-unit, a second data processing sub-unit, and a third data processing sub-unit.

[0297] The first data processing sub-unit is configured to determine a duty cycle offset mean value of the first clock sub-signal according to the duty cycle offset of the first clock sub-signal in the plurality of historical output characteristic offset data.

[0298] The second data processing sub-unit is configured to determine a duty cycle offset mean value of the second clock sub-signal according to the duty cycle offset of the second clock sub-signal in the plurality of historical output characteristic offset data.

[0299] The third data processing sub-unit is configured to calculate a difference between the duty cycle offset mean value of the first clock sub-signal and the duty cycle offset mean value of the second clock sub-signal to obtain the estimated offset.

[0300] In one embodiment, the first data processing sub-unit is specifically configured to:

[0301] perform normal distribution statistics on the duty cycle offset of the first clock sub-signal in the plurality of historical output characteristic offset data to obtain the duty cycle offset mean value of the first clock sub-signal.

[0302] and / or,

[0303] The second data processing sub-unit is specifically configured to:

[0304] The duty cycle offset of the second clock sub-signal in the plurality of historical output characteristic offset data is statistically analyzed according to a normal distribution, and a mean value of the duty cycle offset of the second clock sub-signal is obtained.

[0305] In one embodiment, the clock signal of the reference chip includes a first clock sub-signal and a second clock sub-signal, and each historical output characteristic offset data includes an offset difference between an actual offset of the corresponding reference chip after performing the target test process and an actual offset before performing the target test process, where the actual offset is a duty cycle offset of the first clock sub-signal relative to the second clock sub-signal.

[0306] The data acquisition unit includes an offset calculation sub-unit.

[0307] The offset calculation sub-unit is configured to calculate the offset difference in the plurality of historical output characteristic offset data to obtain the estimated offset.

[0308] In one embodiment, the chip testing device 1300 further includes an initial measurement value acquisition module and a scheme selection module.

[0309] The initial measurement value acquisition module is configured to acquire an initial measurement value of the output characteristic of the chip under test.

[0310] The scheme selection module is configured to select a target chip fuse blowing scheme from the plurality of chip fuse blowing schemes according to the initial measurement value and the estimated offset.

[0311] In one embodiment, each chip fuse blowing scheme is configured to blow at least one electrically programmable fuse in the chip under test.

[0312] The scheme selection module includes a first output calculation unit and a first scheme selection unit.

[0313] The first output calculation unit is configured to, for each chip fuse blowing scheme, acquire an output characteristic adjustment amount corresponding to each chip fuse blowing scheme, calculate a sum of the initial measurement value and the output characteristic adjustment amount of each chip fuse blowing scheme to obtain an adjusted output amount of the output characteristic of the chip under test under adjustment of each chip fuse blowing scheme.

[0314] The first scheme selection unit is configured to select a target chip fuse blowing scheme from the plurality of chip fuse blowing schemes according to the adjusted output amount corresponding to each chip fuse blowing scheme and the estimated offset.

[0315] In one embodiment, the clock signal of the chip under test includes a first clock sub-signal and a second clock sub-signal of the chip under test.

[0316] The adjustment output corresponding to each chip fusing scheme includes a duty cycle output value of the first clock sub-signal and a duty cycle output value of the second clock sub-signal.

[0317] The first scheme selection unit includes a data calculation sub-unit and a scheme selection sub-unit.

[0318] The data calculation sub-unit is configured to, for each chip fusing scheme, calculate an absolute difference between the duty cycle output value of the second clock sub-signal and the estimated offset under each chip fusing scheme to obtain a first absolute difference, and calculate a difference between the first absolute difference and an absolute value of the duty cycle output value of the first clock sub-signal under each chip fusing scheme to obtain a second difference corresponding to each chip fusing scheme.

[0319] The scheme selection sub-unit is configured to determine, as the target chip fusing scheme, a chip fusing scheme corresponding to a minimum second difference in the second differences corresponding to the plurality of chip fusing schemes.

[0320] In an embodiment, each chip fusing scheme is used to fuse at least one electrically programmable fuse in the to-be-tested chip,

[0321] The scheme selection module includes a second output value calculation unit, an adjustment value calculation unit, and a second scheme selection unit.

[0322] The second output value calculation unit is configured to calculate a target output value of the output characteristic of the to-be-tested chip according to the estimated offset.

[0323] The adjustment value calculation unit is configured to obtain a target characteristic adjustment value according to the target output value and the initial measurement value.

[0324] The second scheme selection unit is configured to, for each chip fusing scheme, obtain an output characteristic adjustment amount corresponding to each chip fusing scheme, and in a case where each chip fusing scheme and the target characteristic adjustment value satisfy a preset scheme selection condition, take each chip fusing scheme as a target characteristic adjustment scheme.

[0325] In an embodiment, the characteristic adjustment module 1320 includes a fuse determination unit and a fusing processing unit.

[0326] The fuse determination unit is configured to determine, from a plurality of electrically programmable fuses of the to-be-tested chip, an electrically programmable fuse corresponding to the target chip fusing scheme.

[0327] The fusing processing unit is configured to fuse the electrically programmable fuse corresponding to the target chip fusing scheme.

[0328] In an embodiment, the chip testing device 1300 further includes a target test process execution module.

[0329] The target test process execution module is configured to execute a target test process on the characteristic-adjusted DUT to obtain a DUT meeting the characteristic parameter requirement.

[0330] In one embodiment, the chip testing apparatus 1300 further comprises a state acquisition module and a judgment module.

[0331] The state acquisition module is configured to acquire actual fuse blowing states of the plurality of electrically programmable fuses of the characteristic-adjusted DUT.

[0332] The judgment module is configured to judge whether the actual fuse blowing states are consistent with fuse blowing states corresponding to the target chip blowing scheme.

[0333] Correspondingly, the target test process execution module is specifically configured to:

[0334] In the case that the actual fuse blowing states are consistent with the fuse blowing states corresponding to the target chip blowing scheme, execute the target test process on the characteristic-adjusted DUT.

[0335] In one embodiment, the target test process is a stress-related test process, and the target test process comprises a reflow soldering process and / or an aging test.

[0336] It should be noted that, Figure 13 The chip testing apparatus 1300 shown can execute Figures 4 to 12 the steps in the method embodiments shown, and achieve Figures 4 to 12 the processes and effects in the method embodiments shown, which will not be described here in detail.

[0337] Those skilled in the art can understand that each aspect of the present application can be implemented as a system, a method or a program product. Therefore, each aspect of the present application can be specifically implemented as follows: a complete hardware embodiment, a complete software embodiment (including firmware, microcode, etc.), or an embodiment combining hardware and software, which can be collectively referred to as "circuitry", "module" or "system".

[0338] The electronic device 1400 according to this embodiment of the present application will be described below with reference to Figure 14 The electronic device 1400 shown is in the form of a general computing device. The components of the electronic device 1400 can include, but are not limited to, the above-mentioned at least one processing unit 1410, the above-mentioned at least one storage unit 1420, and a bus 1430 connecting different system components, including the storage unit 1420 and the processing unit 1410. Figure 14 The electronic device 1400 shown is in the form of a general computing device. The components of the electronic device 1400 can include, but are not limited to, the above-mentioned at least one processing unit 1410, the above-mentioned at least one storage unit 1420, and a bus 1430 connecting different system components, including the storage unit 1420 and the processing unit 1410.

[0339] As Figure 14 shown, the electronic device 1400 is in the form of a general computing device. The components of the electronic device 1400 can include, but are not limited to, the above-mentioned at least one processing unit 1410, the above-mentioned at least one storage unit 1420, and a bus 1430 connecting different system components, including the storage unit 1420 and the processing unit 1410.

[0340] The storage unit stores program codes which can be executed by the processing unit 1410, so that the processing unit 1410 performs the steps described in the above "Exemplary Methods" section according to various exemplary embodiments of the present application.

[0341] The storage unit 1420 can include a readable medium in the form of volatile storage such as a random access memory (RAM) 14201 and / or cache memory 14202, and also can include a non-volatile storage such as read only memory (ROM) 14203.

[0342] The storage unit 1420 can further include program / utility 14204 having a set of programs / modules 14205, including an operating system, one or more application programs, other programs / modules, and program / data, each or some combination thereof, used by the processing unit 1410 to implement various aspects of the application.

[0343] The bus 1430 can represent one or more of several types of bus structures, including a storage bus or bus controller, peripheral bus, graphics bus, processor or local bus using any of a variety of bus architectures.

[0344] The electronic device 1400 can also communicate with one or more external devices 1440 such as a keyboard or pointing device, using one or more communication ports 1450. Communication ports 1450 can also enable the electronic device 1400 to communicate with one or more devices that enable user interaction with the electronic device 1400 (for example, remote control or proximity device), and / or one or more devices that enable communication between the electronic device 1400 and other computing devices. Such communication can be facilitated, for example, by an Input / Output (I / O) interface 1450.

[0345] The electronic device 1400 can also communicate with one or more networks, either by way of a network adapter 1460, which can be any wired or wireless communication device including a modem, and / or any other device typically used to connect a computer system to a network and / or another computer system.

[0346] As shown, the network adapter 1460 communicates with the other components of the electronic device 1400 via the bus 1430. Figure 14 It should be appreciated that, although not shown explicitly, other hardware and / or software elements can be used in connection with the electronic device 1400, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc.

[0347]

[0348] ​Those skilled in the art can clearly understand that the example embodiments described in the specification can be implemented by software, or by a combination of software and necessary hardware. Therefore, the technical solutions of the embodiments of the present application can be embodied in a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, a USB, a mobile hard disk, etc.) or a network, and includes a number of instructions to enable a computing device (such as a personal computer, a server, a terminal device, or a network device, etc.) to perform the methods according to the embodiments of the present application.

[0349] In the example embodiments of the present application, a computer readable storage medium is also provided, which can be a readable signal medium or a readable storage medium. Figure 15 A schematic diagram of a computer readable storage medium in the embodiments of the present application is shown in FIG. 15, and as shown in the figure, the computer readable storage medium 1500 stores a program product capable of implementing the method described above. Figure 15 The computer readable storage medium 1500 stores a program product capable of implementing the method described above.

[0350] In some possible embodiments, various aspects of the present application can also be implemented in the form of a program product, which includes program codes for causing a terminal device to perform the steps according to various example embodiments of the present application described in the “example method” section of the specification above when the program product is run on the terminal device.

[0351] More specific examples of the computer readable storage medium in the present application can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0352] In the present application, the computer readable storage medium can include a data signal propagating in a baseband or as a carrier wave in a propagated data signal, in which readable program codes are carried. Such a propagated data signal can take various forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above.

[0353] The readable signal medium can also be any readable medium other than the readable storage medium, which can send, propagate, or transmit programs for use by or in connection with an instruction execution system, apparatus, or device.

[0354] In some examples, the program code contained on the computer-readable storage medium can be transmitted by any appropriate medium including, but not limited to, wireless, wired, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0355] In the implementation, the program code for executing the operation of the present application can be written in any combination of one or more programming languages including an object-oriented programming language, such as Java, C++, etc., and a conventional procedural programming language, such as the "C" language or a similar programming language. The program code can be executed entirely on the user computing device, partially on the user device, as an independent software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0356] In the case of a remote computing device, the remote computing device can be connected to the user computing device through any kind of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (for example, through the Internet by using an Internet service provider).

[0357] The embodiments of the present application provide a computer program product or computer program, which comprises computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions, so that the computer device executes the chip testing method provided in any of the various optional manners in the embodiments of the present application.

[0358] It should be noted that although several modules or units of the device for action execution are mentioned in the above detailed description, such division is not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided into multiple modules or units for embodiment.

[0359] In addition, although the steps of the method in the present application are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired result. In addition or alternatively, some steps can be omitted, multiple steps can be combined into one step, and / or one step can be divided into multiple steps, etc.

[0360] Through the description of the above embodiments, those skilled in the art can easily understand that the example embodiments described herein can be implemented by software, or by software in combination with necessary hardware.

[0361] Therefore, the technical solution according to the embodiments of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a U disk, a mobile hard disk, etc.) or on a network, and includes a plurality of instructions to enable a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the embodiments of the present application.

[0362] Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein.

[0363] It is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure that come within known or customary practice in the art to which the application pertains or that involve known or customary practice in the art to which the application pertains. The specification and examples are to be considered exemplary only, with the true scope and spirit of the application being indicated by the appended claims.

Claims

1. A chip testing method, characterized in that, The method includes: Obtain the estimated offset of the output characteristics of the chip under test by the target test process, wherein the target test process is a chip test process that affects the output characteristics of the chip under test. By utilizing the target chip fuse scheme corresponding to the estimated offset, the output characteristics of the chip under test are adjusted so that the actual output value of the adjusted chip under test has an offset compensation amount corresponding to the estimated offset compared to the standard value of the output characteristic. The offset compensation amount has an offset direction opposite to the estimated offset. The offset compensation amount is used to compensate for the actual output feature offset of the chip under test after the feature adjustment during the target test process. The method of obtaining the estimated offset of the output characteristics of the chip under test by the target test process includes: Acquire multiple historical output characteristic offset data, where each historical output characteristic offset data is used to reflect the amount of change in the output characteristics of a reference chip before and after the target test process is executed; The estimated offset is determined based on the aforementioned historical output characteristic data. The clock signal of the reference chip includes a first clock sub-signal and a second clock sub-signal. Each historical output characteristic offset data includes the duty cycle offset of the first clock sub-signal and the duty cycle offset of the second clock sub-signal of the corresponding reference chip. Determining the estimated offset based on the multiple historical output characteristic data includes: The average duty cycle offset of the first clock sub-signal is determined based on the duty cycle offset of the first clock sub-signal in multiple historical output characteristic offset data. The average duty cycle offset of the second clock sub-signal is determined based on the duty cycle offset of the second clock sub-signal in multiple historical output characteristic offset data. The estimated offset is obtained by calculating the difference between the average duty cycle offset of the first clock sub-signal and the average duty cycle offset of the second clock sub-signal. The step of calculating the average duty cycle offset of the first clock sub-signal based on the duty cycle offset of the first clock sub-signal in multiple historical output characteristic offset data includes: The duty cycle offset of the first clock sub-signal in the multiple historical output characteristic offset data is statistically analyzed using a normal distribution, and the mean value of the duty cycle offset of the first clock sub-signal is obtained. And / or, The step of calculating the average duty cycle offset of the second clock sub-signal based on the duty cycle offset of the second clock sub-signal in multiple historical output characteristic offset data includes: The duty cycle offset of the second clock sub-signal in the multiple historical output characteristic offset data is statistically analyzed using a normal distribution, and the mean value of the duty cycle offset of the second clock sub-signal is obtained.

2. The method according to claim 1, characterized in that, Before adjusting the output characteristics of the chip under test using the target chip fuse scheme corresponding to the estimated offset, the method further includes: Obtain initial measured values ​​of the output characteristics of the chip under test; Based on the initial measurement value and the estimated offset, the target chip fuse solution is selected from multiple chip fuse solutions.

3. The method according to claim 2, characterized in that, Each chip-to-fuse scheme is used to blow at least one electrically programmable fuse in the chip under test. The step of selecting the target chip fuse solution from multiple chip fuse solutions based on the initial measurement value and the estimated offset includes: For each chip fuse-breaking scheme, the output characteristic adjustment amount corresponding to each chip fuse-breaking scheme is obtained, and the sum of the initial measurement value and the output characteristic adjustment amount of each chip fuse-breaking scheme is calculated to obtain the adjusted output amount of the output characteristic of the chip under test under the adjustment of each chip fuse-breaking scheme. Based on the adjustment output amount corresponding to each of the multiple chip fuse-breaking schemes and the estimated offset amount, the target chip fuse-breaking scheme is selected from the multiple chip fuse-breaking schemes.

4. The method according to claim 3, characterized in that, The clock signal of the chip under test includes the first clock sub-signal and the second clock sub-signal of the chip under test; The adjustment output for each chip fuse-breaking scheme includes: the duty cycle output value of the first clock sub-signal and the duty cycle output value of the second clock sub-signal; The step of selecting the target chip fuse scheme from the multiple chip fuse schemes based on the adjusted output amount corresponding to each of the multiple chip fuse schemes and the estimated offset includes: For each chip fuse solution, perform the following steps: Calculate the absolute difference between the duty cycle output value of the second clock sub-signal and the estimated offset under each chip fuse-breaking scheme to obtain the first absolute difference; Calculate the difference between the first absolute difference and the absolute value of the duty cycle output value of the first clock sub-signal under each chip fuse-breaking scheme to obtain the second difference corresponding to each chip fuse-breaking scheme; The chip fuse solution corresponding to the smallest second difference among the multiple chip fuse solutions is determined as the target chip fuse solution.

5. The method according to claim 2, characterized in that, Each chip-to-fuse scheme is used to blow at least one electrically programmable fuse in the chip under test. The step of selecting the target chip fuse solution from multiple chip fuse solutions based on the initial measurement value and the estimated offset includes: Based on the estimated offset, calculate the target output value of the output characteristics of the chip under test; Based on the target output value and the initial measurement value, the target characteristic adjustment value is obtained; For each chip fuse-breaking scheme, the corresponding output characteristic adjustment amount is obtained. If each chip fuse-breaking scheme and the target characteristic adjustment value meet the preset scheme selection conditions, each chip fuse-breaking scheme is taken as the target characteristic adjustment scheme.

6. The method according to claim 1, characterized in that, The step of adjusting the output characteristics of the chip under test using a target chip fuse scheme corresponding to the estimated offset includes: Among the multiple electrically programmable fuses of the chip under test, determine the electrically programmable fuse that corresponds to the fuse-breaking scheme of the target chip; The electrically programmable fuse corresponding to the target chip's fuse-breaking scheme is blown.

7. The method according to claim 1, characterized in that, After adjusting the output characteristics of the chip under test using a chip fuse scheme corresponding to the estimated offset, the method further includes: The target test process is performed on the chip under test after the characteristics are adjusted to obtain a chip under test that meets the characteristic parameter requirements.

8. The method according to claim 7, characterized in that, After adjusting the output characteristics of the chip under test using the target chip fuse scheme corresponding to the estimated offset, and before performing the target test process on the chip under test with the adjusted characteristics, the method further includes: Obtain the actual melting state of multiple programmable fuses of the chip under test after the characteristic adjustment; Determine whether the actual fuse-breaking state is consistent with the fuse-breaking state corresponding to the target chip fuse-breaking scheme; The process of performing the target test on the chip under test after adjusting the aforementioned characteristics includes: If the actual fusing state is consistent with the fusing state corresponding to the target chip fusing scheme, the target test process is performed on the chip under test after the characteristic adjustment.

9. The method according to any one of claims 1-8, characterized in that, The target testing process is a pressure-related testing process. The target testing process includes reflow soldering and / or aging testing.

10. A chip testing device, characterized in that, include: The offset acquisition module is used to acquire the estimated offset of the output characteristics of the chip under test by the target test process, wherein the target test process is a chip test process that affects the output characteristics of the chip under test. The characteristic adjustment module is used to adjust the output characteristics of the chip under test (DUT) using a target chip fuse scheme corresponding to the estimated offset, so that the actual output value of the DUT after characteristic adjustment has an offset compensation amount corresponding to the estimated offset compared to the standard value of the output characteristic. The offset compensation amount is in the opposite direction to the estimated offset. The offset compensation amount is used to compensate for the actual output feature offset of the chip under test after feature adjustment during the target testing process.

11. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the chip testing method of any one of claims 1-9 by executing the executable instructions.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the chip testing method according to any one of claims 1-9.

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