Power supply noise test method and device of memory chip, storage medium and equipment

Abstract

The present disclosure relates to the technical field of integrated circuits, and discloses a power supply noise testing method and device of a memory chip, a storage medium and equipment. The power supply noise testing method comprises: transmitting test data with a to-be-tested memory through a data line, wherein a data bit corresponding to a target data line in the test data is target level data, and the target level data is used to turn on a target power supply signal of the to-be-tested memory to a ground end; acquiring a voltage signal at a connection pin of the target data line and the to-be-tested memory; and detecting power supply noise generated by the target power supply signal in the to-be-tested memory based on the voltage signal. The testing method can make the to-be-tested memory in a running process, and on the other hand, can make the target power supply signal generate a noise signal, and the noise signal is superimposed on the target data line, so that the power supply noise signal generated by the target power supply signal can be detected by detecting the voltage signal on the target data line.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more specifically, to power supply noise testing methods, apparatus, storage media, and devices for memory chips. Background Technology

[0002] SODIMM (Small Outline Dual In-line Memory Module) is a small dual in-line memory module used in personal laptops and other applications where size is a critical factor.

[0003] During operation, SDRAM chips experience dynamic current changes, which generate power supply noise on the chip. Since SDRAM chips are packaged in a package, this power supply noise is difficult to measure.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to overcome the shortcomings of the prior art and to provide a method, apparatus, storage medium and device for testing power supply noise of memory chips.

[0006] According to an exemplary embodiment of this disclosure, a method for testing power supply noise of a memory chip is provided, comprising: transmitting test data with the memory under test via a data line, wherein the data bit corresponding to the target data line in the data line is target level data, and the target level data is used to conduct the target power supply signal of the memory under test to the ground terminal; acquiring the voltage signal at the connection pin of the target data line and the memory under test; and detecting power supply noise generated by the target power supply signal in the memory under test based on the voltage signal.

[0007] In some embodiments, the pins of the memory under test connected to the corresponding data line are connected to the target voltage terminal through pull-up resistors, and the target voltage terminal is used to output the target power supply signal; the test data is the first test data, and the target level signal is a low level signal.

[0008] In some embodiments, the test data transmission with the memory under test via a data line includes: writing first test data to the memory under test via a data line.

[0009] In some embodiments, acquiring the voltage signal at the connection pin between the target data line and the memory under test includes: acquiring a first voltage signal at the connection pin between the target data line and the memory under test; correspondingly, detecting power supply noise generated by the target power supply signal in the memory under test based on the voltage signal includes: detecting power supply noise generated by the target power supply signal in the memory under test based on the voltage fluctuation of the first voltage signal.

[0010] In some embodiments, detecting power supply noise generated by the target power supply signal in the memory under test based on the voltage fluctuation of the first voltage signal includes: determining a first voltage fluctuation rate of the first voltage signal; and detecting power supply noise generated by the target power supply signal in the memory under test based on the first voltage fluctuation rate.

[0011] In some embodiments, writing the first test data to the memory under test via a data line includes: generating the first test data by performing a bitwise AND operation on a preset first data pattern and first control data; writing the first test data to the memory under test via a data line, wherein the data bits corresponding to the target data line in the first control data are low-level data, and the data bits corresponding to other data lines are high-level data.

[0012] In some embodiments, the pins of the internal device under test that can be connected to the corresponding data lines are respectively connected to the target voltage terminal through a pull-up transistor and to the ground terminal through a pull-down transistor. The target voltage terminal is used to output the target power supply signal. The test data includes second test data, and the target level signal is a high level signal.

[0013] In some embodiments, the test data transmission with the memory under test via the data cable includes: reading second test data from the memory under test via the data cable.

[0014] In some embodiments, acquiring the voltage signal at the connection pin between the target data line and the memory under test includes: acquiring a second voltage signal at the connection pin between the target data line and the memory under test; correspondingly, detecting power supply noise generated by the target power supply signal in the memory under test based on the voltage signal includes: detecting power supply noise generated by the target power supply signal in the memory under test based on the voltage fluctuation of the second voltage signal.

[0015] In some embodiments, detecting power supply noise generated by the target power supply signal in the memory under test based on the voltage fluctuation of the second voltage signal includes: determining a second voltage fluctuation rate of the second voltage signal; and detecting power supply noise generated by the target power supply signal in the memory under test based on the second voltage fluctuation rate.

[0016] In some embodiments, reading the second test data from the memory under test via a data line includes: performing a bitwise OR operation on the second control data and a second data pattern pre-written into the memory under test to generate the second test data; and reading the second test data from the memory under test via a data line; wherein the data bit of the second control data corresponding to the target data line is high-level data, and the data bit corresponding to other data lines is low-level data.

[0017] In some embodiments, the method further includes: acquiring signal integrity test data and / or power integrity test data transmitted for each signal line of the memory under test; determining the interference immunity of each data line based on the signal integrity test data and / or the power integrity test data; and identifying the data line with the best interference immunity as the target data line.

[0018] According to a second aspect of this disclosure, a power supply noise testing device for a memory chip is also provided, comprising: a control module for transmitting test data with the memory under test via a data line, wherein the data signal transmitted by the target data line in the data line is a target level signal, and the target level signal is used to conduct the target power supply signal of the memory under test to a ground terminal; a voltage acquisition module for acquiring the voltage signal at the connection pin of the target data line and the memory under test; and a noise detection module for detecting power supply noise generated by the target power supply signal in the memory under test based on the voltage signal.

[0019] According to a third aspect of this disclosure, a computer-readable storage medium is also provided, on which a computer program is stored, wherein the program, when executed by a processor, implements a power supply noise test of the memory chip described in any embodiment of this disclosure.

[0020] According to a fourth aspect of this disclosure, a test apparatus is also provided, comprising: one or more processors; and a storage device for storing one or more programs, which, when executed by the one or more processors, cause the one or more processors to perform a power supply noise test on a memory chip according to any embodiment of this disclosure.

[0021] This disclosed power supply noise testing method involves a control device transmitting data with the memory under test (MDT) via a data line. The control device controls the data signal transmitted through the target data line to a target level signal. This target level signal is used to conduct the target power supply signal to the ground terminal. This allows the MDT to operate under dynamic current changes, creating a realistic scenario. Simultaneously, it generates noise signals from the target power supply signal, which are superimposed on the target data line. Therefore, the power supply noise signal generated by the target power supply signal can be detected by detecting the voltage signal on the target data line. This disclosed testing method utilizes the existing circuit structure of the MDT to detect the power supply noise signal generated by the target power supply signal of the memory chip, does not rely on proprietary testing equipment, and has the advantages of accurate test results and simple operation.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0024] Figure 1 A flowchart of a power supply noise testing method for a memory chip according to one embodiment of the present disclosure;

[0025] Figure 2 This is a schematic diagram of a memory interface circuit according to one embodiment of the present disclosure;

[0026] Figure 3 This is a schematic diagram of a first data pattern according to one embodiment of the present disclosure;

[0027] Figure 4 This is a schematic diagram of a memory interface circuit according to another embodiment of the present disclosure;

[0028] Figure 5 This is a schematic diagram of a second data pattern according to one embodiment of the present disclosure;

[0029] Figure 6 This is a waveform diagram of the voltage signal on the target data line according to one embodiment of the present disclosure;

[0030] Figure 7 This is a structural block diagram of a power supply noise testing apparatus for a memory chip according to one embodiment of the present disclosure;

[0031] Figure 8 This is a schematic diagram of the structure of a test device according to one embodiment of the present disclosure. Detailed Implementation

[0032] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0033] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0034] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0035] During operation, SDRAM chips experience dynamic current changes, which generate power supply noise on the chip. Since SDRAM chips are packaged in a package, the power supply noise on the SDRAM chip is difficult to measure.

[0036] The power supply noise measured on the motherboard often differs significantly from that measured on the chip itself. To improve measurement accuracy, the following two methods are primarily used to measure the power supply noise on the chip:

[0037] 1. Open the memory chip and use a precision probe to measure the power supply noise on the chip. Although this measurement method can guarantee measurement accuracy, it requires a high investment cost and is difficult to use on a large scale.

[0038] 2. Design a special package structure to route the power pad on the chip to an unused pin, which can also measure the on-chip power supply noise. However, this method does not conform to the actual definition in the chip's datasheet. If the user connects the NC pin to other signals such as GND, a short circuit between power and ground will occur, burning out the chip.

[0039] To address the aforementioned problems, this disclosure provides a test method for detecting power supply noise in memory chips. This test method can be used to test the power supply noise generated by a target power network during the operation of the memory chip. The target power network can be, for example, the VDD power network that powers the I / O operations of the memory. This test method can be executed by a control device, such as a CPU or an MCU. Figure 1 This is a flowchart of a power supply noise testing method for a memory chip according to one embodiment of the present disclosure, as shown below. Figure 1 As shown, the testing method may include the following steps:

[0040] S110. Test data is transmitted to the memory under test via the data line. The data signal transmitted by the target data line in the data line is a target level signal. The target level signal is used to turn on the target power supply signal of the memory under test to the ground terminal.

[0041] S120. Obtain the voltage signal at the connection pin between the target data line and the memory under test;

[0042] S130, Detect power supply noise generated by the target power supply signal in the memory under test based on voltage signal.

[0043] This disclosed power supply noise testing method involves a control device transmitting data with the memory under test (MDT) via a data line. The control device controls the data signal transmitted through the target data line to a target level signal. This target level signal is used to conduct the target power supply signal to the ground terminal. This allows the MDT to operate under dynamic current changes, creating a realistic scenario. Simultaneously, it generates noise signals from the target power supply signal, which are superimposed on the target data line. Therefore, the power supply noise signal generated by the target power supply signal can be detected by detecting the voltage signal on the target data line. This disclosed testing method utilizes the existing circuit structure of the MDT to detect the power supply noise signal generated by the target power supply signal of the memory chip, does not rely on proprietary testing equipment, and has the advantages of accurate test results and simple operation.

[0044] The following section, with reference to the accompanying drawings, provides a detailed description of each step in the testing method disclosed herein.

[0045] In step S110, test data is transmitted to the memory under test via a data cable.

[0046] In this data line, the target data line transmits a target level signal, which is used to connect the target power supply signal of the memory under test to the ground terminal, thereby creating a path to ground and generating a power supply noise signal. The memory typically includes multiple I / O pins, each connected to a control device via a data line. Correspondingly, multiple data lines are connected to the memory. The target data line is a pre-selected data line used for power supply noise detection. This disclosure detects the corresponding power supply noise signal by superimposing the power supply noise signal onto the target data line and detecting the voltage signal on the target data line.

[0047] It is understood that the selected target data line should have high anti-interference capability, i.e., be less susceptible to other interference, so that the voltage signal on the target data line can more accurately reflect the power supply noise of the memory under test. In an exemplary embodiment, before step S110, the test method may further include the following steps:

[0048] S101. Obtain signal integrity test data and / or power integrity test data transmitted for each signal line of the memory under test;

[0049] S102. Determine the interference immunity of each data line based on signal integrity test data and / or power integrity test data;

[0050] S103. Select the data line with the best anti-interference performance as the target data line.

[0051] It is known that data lines are formed by routing on a circuit board. Different data lines may have different routing methods and structures on the circuit board, resulting in different anti-interference capabilities. This disclosure identifies the target data line from multiple data lines through steps S101 to S103. The data signal transmitted on the target data line is less affected by interference from the data signals on other data lines. Therefore, by detecting the voltage signal transmitted on the target data line, the power supply noise signal generated by the target power supply signal can be accurately reflected. In an exemplary embodiment, signal integrity test data and power integrity test data for the memory under test can be generated by simulation software. Of course, in other embodiments, the control device can also detect the anti-interference capability of each data line in other ways. For example, the control device can write preset data to the memory under test through each data line, and then read the data through each data line. The anti-interference capability of each data line can be judged by comparing the bit error rate of the read data with that of the preset data. These are all within the protection scope of this disclosure.

[0052] The target level signal can be either a high-level signal or a low-level signal, depending on the interface circuit structure of the memory under test. The following description, in conjunction with the accompanying drawings, further explains step S110 for memory modules with different interface circuits.

[0053] In an exemplary embodiment, Figure 2 This is a schematic diagram of a memory interface circuit according to one embodiment of the present disclosure. The corresponding memory 200 can be, for example, DDR4 / DDR5 SDRAM (Double-Data-Rate Fourth Generation Synchronous Dynamic Random Access Memory). Figure 2 As shown, the I / O pins of memory 200 are connected to the target voltage terminal VDD via a pull-up resistor RU. The target voltage terminal VDD is used to output the target power supply signal. Inside memory 200, the I / O pins are connected to one input terminal of a comparator, and the other input terminal of the comparator receives the reference signal Vref. Meanwhile, within control device 100, the data lines connecting the I / O pins of memory 200 are connected to the target voltage terminal VDD via a pull-up transistor TU and to the ground terminal VSS via a pull-down transistor TD. The pull-up transistor TU and the pull-down transistor TD have opposite polarities; for example, the pull-up transistor TU is a P-type transistor, and the pull-down transistor TD is an N-type transistor. When the pull-down transistor TD is off and the pull-up transistor TU is on, the pull-up transistor TU conducts, connecting the data line to the target voltage terminal VDD. This allows the I / O pins of memory 200 to obtain a high-level signal. This high-level signal is at the same potential as the high-level signal obtained by the I / O pins of memory 200 through the pull-up resistor RU, thus disconnecting the target voltage terminal VDD from ground. When the pull-up transistor TU is off and the pull-down transistor TD is on, the pull-down transistor TD conducts, connecting the data line to the ground terminal VSS. Thus, on the memory 200 side, the target voltage terminal VDD forms a path to ground through this data line connected to the ground terminal VSS. The target power supply signal output from the target voltage terminal VDD consumes power and generates a power supply noise signal, which is superimposed on the data line. Therefore, by detecting the data signal on this data line, the power supply noise signal generated by the target power supply signal can be obtained.

[0054] When the I / O pins of the memory under test have Figure 2In the interface circuit structure shown, the test data transmitted between the control device and the memory under test can be the first test data. Correspondingly, step S110 involves the control device writing this first test data to the memory under test, thereby controlling the memory under test to be in an operating state through the data writing operation, and dynamically changing the operating current of the memory under test by writing different data. The control device controls the target voltage terminal VDD to form a ground path by controlling the data transmitted on the target data line to be low-level data, thus generating a power supply noise signal. At this time, the memory under test is the data receiving end, and the control device is the data sending end.

[0055] In an exemplary embodiment, the step of the control device writing first test data to the memory under test may specifically include the step of making the data on the target data line low-level data:

[0056] S111. Generate first test data by performing a bitwise AND operation between the preset first data pattern and the first control data;

[0057] S112. Write the first test data to the memory under test via the data cable.

[0058] In the first control data, the data bits corresponding to the target data line are low-level data, and the data bits corresponding to other data lines are high-level data.

[0059] The first data pattern includes normally flipped "0" and "1" data. The data bit corresponding to the target data line in the first control data is low-level data, and the other data bits in the first control data are high-level data. Thus, by performing a bitwise AND operation between the first data pattern and the first control data, it is ensured that the data corresponding to the target data line in the obtained first test data is low-level data, and the other data bits of the first test data retain the original data pattern in the first data pattern.

[0060] For example, Figure 3 This is a schematic diagram of a first data pattern according to an embodiment of the present disclosure, such as... Figure 3As shown, the memory under test includes eight data lines DQ0 to DQ7. The control device writes first test data to the memory under test through these eight data lines DQ. The preset first data pattern Pattern1 can be, for example, “01110111”, “11010111”, “10011100”, etc. The target data line is the second data line DQ1, that is, the data signal corresponding to the data bit of the second data line DQ1 in the first test data is 0. Then the preset first control data can be, for example, “10111111”. The first test data is obtained by performing a bitwise AND operation between the preset first data pattern Pattern1 and the first control data. The data is represented as “00110111”, “10010111”, “10011100”, etc. It can be seen that the data transmitted via the target data line (second data line) DQ1 becomes “0”, and the data of other data bits in the first test data corresponds to the original data in the first data pattern Pattern1. This achieves the goal of controlling the data transmitted via the target data line DQ1 to be low-level while ensuring that the data of other bits flips normally. Therefore, the control device ensures that the target power supply signal can generate power noise and that the control device can detect the power noise signal on the target data line DQ1 by writing the first test data to the memory under test. It should be understood that the first data pattern Pattern1 used in actual testing can have different representations. Figure 3 The first data pattern Pattern1 shown is merely illustrative and should not be construed as a limitation of this disclosure.

[0061] In another exemplary embodiment, Figure 4 This is a schematic diagram of a memory interface circuit according to another embodiment of the present disclosure. The corresponding memory can be, for example, LDDR4 / LDDR5 SDRAM (Low Power Double Data Rate SDRAM), such as... Figure 4 As shown, inside memory 200, the I / O pins of memory 200 are connected to the target voltage terminal VDD via pull-up transistor TU and to the ground terminal VSS via pull-down transistor TD. The target voltage terminal VDD is used to output the target power supply signal. The I / O pins of memory 200 are connected to the corresponding pins of control device 100 via data lines. Simultaneously, within control device 100, the corresponding pins of control device 100 are connected to the ground terminal VSS via pull-down resistor RD. Figure 4As shown, when the pull-up transistor TU is turned on, the target voltage terminal VDD forms a path to ground through the data line, the pull-down resistor RD, and the connection to the ground terminal VSS. The target voltage terminal VDD consumes power to ground, generating a power supply noise signal, which is superimposed on the data line. Therefore, the power supply noise signal generated by the target power supply signal during the operation of the memory chip can be detected through this data line. When the pull-up transistor TU is turned off and the pull-down transistor TD is turned on, the target voltage terminal VDD is disconnected from ground and no power supply noise signal is generated. It can be seen that... Figure 4 In the structure shown, the target level signal is a high level signal, that is, the target voltage terminal VDD forms a path to ground through the pull-up transistor TU and the pull-down resistor RD, forming a high level signal on the data line.

[0062] When the I / O pins of the memory under test have Figure 4 In the interface circuit structure shown, the test data transmitted between the control device and the memory under test can be the second test data. Accordingly, step S110 involves the control device reading the second test data from the memory under test to control the memory under test to be in an operating state. Different read data causes dynamic changes in the operating current of the memory chip. The control device controls the target power supply signal to form a ground path by controlling the data signal transmitted via the target data line to be a high-level signal, thereby generating a power supply noise signal. At this time, the control device is the data receiver, and the memory under test is the data transmitter.

[0063] In an exemplary embodiment, the step of the control device reading second test data from the memory under test may specifically include:

[0064] S113. Perform a bitwise OR operation between the second control data and the second data pattern pre-written into the memory to be tested to generate the second test data.

[0065] S114. Read the second test data from the memory under test via the data cable.

[0066] In this second control data, the data bit corresponding to the target data line is high-level data, and the data bit corresponding to other data lines is low-level data.

[0067] Similar to the first data pattern, the second data pattern includes normally toggled "0" and "1" signals. The data bit of the second control data corresponding to the target data line is high-level data, while the other data bits are low-level data. This ensures that the data obtained in the second test data corresponds to the target data line as high-level data, and also ensures that the data of the other data bits in the second test data maintains the original data pattern in the second data pattern.

[0068] For example, Figure 5This is a schematic diagram of a second data pattern according to one embodiment of the present disclosure, such as... Figure 5 As shown, the memory under test includes eight data lines DQ0 to DQ7. The control device reads second test data from the memory under test through these eight data lines. The preset second data pattern Pattern2 can be, for example, "10110011", "01010110", "10111100", etc. The target data line is the second data line DQ1, that is, the data on the second data line DQ1 is the data "1". Then the second control data can be, for example, "10111111". By comparing the preset second data pattern Pattern2 with the second... The control data undergoes a bitwise OR operation to obtain the second test data as "11110011", "01010110", "11111100", etc. This means that only the data transmitted via the second data line DQ1 is forcibly converted to "1", while other data bits maintain their original values ​​in the second data pattern and are flipped normally. This ensures that the target power supply signal can form a path to ground by reading the second test data from the memory under test, generating a power noise signal, which the control device can detect on the target data line DQ1. It should be understood that the above-described second data pattern Pattern2 is merely an example; the second data pattern Pattern2 used in actual testing can be a complex and varied data pattern.

[0069] In step S120, the control device acquires the voltage signal at the connection pin between the target data line and the memory under test.

[0070] The control device can be connected to a signal detection device to acquire the voltage signal at the connection pin between the target data line and the memory under test, and output it to the control device. The signal detection device can be, for example, an oscilloscope. The oscilloscope's signal input is connected to the connection pin between the target data line and the memory under test, and its output is connected to the control device, thus the oscilloscope outputs the detected voltage signal to the control device. Of course, the signal detection device can also be other electronic devices capable of detecting voltage signals; this disclosure does not limit its application to these devices.

[0071] In an exemplary embodiment, when the memory under test has Figure 2 When the interface circuit structure shown is executed, step S120 involves the control device acquiring the first voltage signal at the connection pin between the target data line and the memory under test. In other words, during the process of writing data to the memory under test, the control device detects the power supply noise of the memory under test by acquiring the first voltage signal at the connection pin between the target data line and the memory under test.

[0072] In another exemplary embodiment, when the memory under test has Figure 4When the interface circuit structure shown is executed, step S120 involves the control device acquiring the second voltage signal at the connection pin between the target data line and the memory under test. In other words, during the process of reading the pre-stored test data in the memory under test, the control device detects the power supply noise of the memory under test by acquiring the second voltage signal at the connection pin between the target data line and the memory under test.

[0073] It is understandable that the voltage signal acquired by the control device is superimposed with the power supply noise signal generated by the target power supply signal in the memory under test. Therefore, this step can detect the power supply noise signal generated by the target power supply signal by analyzing the acquired voltage signal.

[0074] In step S130, the control device detects power supply noise generated by the target power supply signal in the memory under test based on the voltage signal.

[0075] As mentioned above, since the power noise signal generated by the target power signal is superimposed on the voltage signal on the target data line, the power noise signal generated by the target power supply signal of the memory under test can be detected by the acquired voltage signal.

[0076] In an exemplary embodiment, when the memory under test has Figure 2 When the interface circuit structure shown is used, step S130 involves detecting power supply noise generated by the target power supply signal in the memory under test based on the voltage fluctuation of the first voltage signal. Specifically, the control device first determines the first voltage fluctuation rate of the first voltage signal, and then further detects the power supply noise generated by the target power supply signal in the memory under test based on the first voltage fluctuation rate. The first voltage fluctuation rate can be understood as the voltage difference between the voltage signal with the maximum voltage value and the voltage signal with the minimum voltage value in the first voltage signal. If the first voltage fluctuation rate is less than a voltage threshold, it indicates that the power supply noise of the target power supply signal in the memory under test is relatively small; if the first voltage fluctuation rate is greater than the voltage threshold, it indicates that the power supply noise generated by the target power supply signal in the memory under test is relatively large.

[0077] For example, the structural circuit of the memory under test has Figure 2 In the structure shown, the data signal transmitted through the target data line is a low-level signal. Under normal circumstances, without power supply noise interference, the data signal transmitted on the target data line should be a stable low-level signal. However, as mentioned above, due to the influence of power supply noise generated by the target power supply signal, the actual data signal transmitted on the target data line is as follows: Figure 6 As shown, Figure 6The horizontal axis represents time, and the vertical axis represents the voltage signal amplitude. It can be seen that under the influence of power supply noise generated by the target power supply signal, the data signal transmitted on the target data line will fluctuate to some extent. If the voltage fluctuation rate of the first voltage signal is large, for example, exceeding the fluctuation threshold, then the current power supply noise is considered large; or if the voltage fluctuation rate of the first voltage signal is less than the threshold, then the current power supply noise is considered small. Of course, the specific magnitude of the power supply noise signal generated by the target power supply signal can also be detected.

[0078] In another exemplary embodiment, when the memory under test has Figure 4 In the interface circuit structure shown, step S130 involves detecting power supply noise generated by the target power supply signal in the memory under test based on the voltage fluctuation of the second voltage signal. For example, the control device can determine the second voltage fluctuation rate of the second voltage signal and detect the power supply noise generated by the target power supply signal in the memory under test based on the second voltage fluctuation rate. The second voltage fluctuation rate is the voltage difference between the voltage signal with the maximum voltage value and the voltage signal with the minimum voltage value in the second voltage signal. Clearly, the second voltage fluctuation rate reflects the fluctuation range of the second voltage signal, and the control device can detect the power supply noise generated by the target power supply signal in the memory under test based on the second voltage fluctuation rate. For example, the control device can compare the second voltage fluctuation rate with a preset fluctuation threshold. If the second voltage fluctuation rate is less than the fluctuation threshold, the control device can determine that the power supply noise generated by the target power supply signal in the memory under test is relatively small; or if the second voltage fluctuation rate is greater than the fluctuation threshold, the control device can determine that the power supply noise generated by the target power supply signal in the memory under test is relatively large.

[0079] For example, when the memory under test has Figure 4 When the interface circuit structure shown is used, stable high-level data is transmitted on the target data line. However, due to the influence of the power supply noise signal generated by the target power supply signal, the actual data transmitted on the target data line will be superimposed with the power supply noise signal. In other words, the second voltage signal obtained by the control device is fluctuating because of the superimposed power supply noise signal. Therefore, the power supply noise signal of the memory under test can be specifically analyzed by the second voltage fluctuation rate of the obtained second voltage signal.

[0080] This disclosure also provides a power supply noise testing device for memory chips. Figure 7 This is a structural block diagram of a power supply noise testing apparatus for a memory chip according to one embodiment of the present disclosure, as shown below. Figure 7 As shown, the testing device 700 may include a control module 710, a voltage acquisition module 720, and a noise detection module 730, wherein,

[0081] The control module 710 is used to transmit test data with the memory under test via a data line. The data signal transmitted by the target data line in the data line is a target level signal, which is used to turn on the target power supply signal of the memory under test to the ground terminal.

[0082] The voltage acquisition module 720 is used to acquire the voltage signal at the connection pin between the target data line and the memory under test.

[0083] The noise detection module 730 is used to detect power supply noise generated by the target power supply signal in the memory under test based on the voltage signal.

[0084] In an exemplary embodiment, the pin of the memory under test connected to the corresponding data line is connected to the target voltage terminal through a pull-up resistor. The target voltage terminal is used to output the target power supply signal; the test data is the first test data, and the target level signal is a low level signal.

[0085] In an exemplary embodiment, the control module 710 is further configured to write first test data to the memory under test via a data line.

[0086] In an exemplary embodiment, the control device is further configured to: generate first test data by performing a bitwise AND operation on a preset first data pattern and first control data; and write the first test data into the memory under test via a data line, wherein the data bits corresponding to the target data line in the first control data are low-level data, and the data bits corresponding to other data lines are high-level data.

[0087] In an exemplary embodiment, the voltage acquisition module 720 is further configured to acquire a first voltage signal at the connection pin between the target data line and the memory under test.

[0088] In an exemplary embodiment, the noise detection module 730 is further configured to detect power supply noise generated by the target power supply signal in the memory under test based on the voltage fluctuation of the first voltage signal.

[0089] In an exemplary embodiment, the noise detection module 730 is further configured to: determine a first voltage fluctuation rate of a first voltage signal; and detect power supply noise generated by a target power supply signal in the memory under test based on the first voltage fluctuation rate.

[0090] In an exemplary embodiment, the pins of the internal device under test that can be connected to the corresponding data lines are respectively connected to the target voltage terminal through a pull-up transistor and to the ground terminal through a pull-down transistor. The target voltage terminal is used to output the target power supply signal. The test data includes second test data, and the target level signal is a high level signal.

[0091] In an exemplary embodiment, the control module 710 is further configured to read second test data from the memory under test via a data line.

[0092] In an exemplary embodiment, the voltage acquisition module 720 is further configured to acquire a second voltage signal at the connection pin between the target data line and the memory under test;

[0093] In an exemplary embodiment, the noise detection module 730 is further configured to detect power supply noise generated by the target power supply signal in the memory under test based on voltage fluctuations of the second voltage signal.

[0094] In an exemplary embodiment, the noise detection module 730 is further configured to: determine a second voltage fluctuation rate of the second voltage signal; and detect power supply noise generated by the target power supply signal in the memory under test based on the second voltage fluctuation rate.

[0095] In an exemplary embodiment, the control module 710 is further configured to: perform a bitwise OR operation between a preset second data pattern pre-written into the memory under test and the second control data to generate second test data; and read the second test data from the memory under test via a data line; wherein the data bit of the second control data corresponding to the target data line is high-level data, and the data bit corresponding to other data lines is low-level data.

[0096] In an exemplary embodiment, the test apparatus 700 may further include an analysis module, which is configured to: acquire signal integrity test data and / or power integrity test data transmitted to each signal line of the memory under test; determine the interference immunity of each data line based on the signal integrity test data and / or power integrity test data; and determine the data line with the best interference immunity as the target data line.

[0097] Figure 8 This is a schematic diagram of the structure of a test device according to one embodiment of the present disclosure. It should be noted that... Figure 8 The test device 800 shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein. Figure 8 As shown, the test device 800 may include, but is not limited to, terminals, tablets, servers, etc.

[0098] like Figure 8 As shown, the test device 800 includes a central processing unit (CPU) 801, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 802 or a program loaded from a storage section 808 into a random access memory (RAM) 803. The RAM 803 also stores various programs and data required for system operation. The CPU 801, ROM 802, and RAM 803 are interconnected via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0099] The following components are connected to the (I / O) interface 805: an input section 806 including a keyboard, mouse, etc.; an output section 807 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 808 including a hard disk, etc.; and a communication section 809 including a network interface card such as a LAN card, modem, etc. The communication section 809 performs communication processing via a network such as the Internet. A drive 810 is also connected to the (I / O) interface 805 as needed. A removable medium 811, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 810 as needed so that computer programs read from it can be installed into the storage section 808 as needed.

[0100] Specifically, according to embodiments of this disclosure, the above reference flow Figure 1 The described process can be implemented as a computer software program. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable storage medium, the computer program containing program code for performing the methods shown in the flowchart. In such embodiments, the computer program can be downloaded and installed from a network via communication section 809, and / or installed from removable medium 811. When the computer program is executed by central processing unit (CPU) 801, it performs the various functions defined in the methods and apparatus of this disclosure.

[0101] It should be noted that the computer-readable storage medium disclosed herein may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable storage medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable storage medium can be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, etc., or any suitable combination thereof.

[0102] In another aspect, this disclosure also provides a computer-readable storage medium, which may be included in the test device 800 described in the above embodiments; or it may exist independently and not assembled into the test device 800. The computer-readable storage medium carries one or more programs that, when executed by the test device 800, cause the test device 800 to implement the methods as described in the following embodiments. For example, the test device 800 may implement... Figure 1 The various steps shown are as follows.

[0103] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the generality of this disclosure and include, but are not disclosed herein, common knowledge or customary techniques in the art. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

Claims

1. A method for testing power supply noise of a memory chip, characterized in that, include: Test data is transmitted to the memory under test via a data line. The data bit corresponding to the target data line in the data line is a target level signal. The target level signal is used to turn on the target power supply signal of the memory under test to the ground terminal. Obtain the voltage signal at the connection pin between the target data line and the memory under test; Based on the voltage signal, power supply noise generated by the target power supply signal in the memory under test is detected; The power supply noise test method for the memory chip further includes: Acquire signal integrity test data and / or power integrity test data transmitted for each signal line of the memory under test; The interference immunity of each data line is determined based on the signal integrity test data and / or the power integrity test data. The data line with the best anti-interference performance is identified as the target data line.

2. The power supply noise testing method for memory chips according to claim 1, characterized in that, The pins of the memory under test connected to the corresponding data line are connected to the target voltage terminal through pull-up resistors. The target voltage terminal is used to output the target power supply signal. The test data is the first test data, and the target level signal is a low level signal.

3. The power supply noise testing method for memory chips according to claim 2, characterized in that, The test data transmission via data cable to the memory under test includes: Write the first test data to the memory under test via the data cable.

4. The power supply noise testing method for memory chips according to claim 3, characterized in that, The step of acquiring the voltage signal at the connection pin between the target data line and the memory under test includes: Obtain the first voltage signal at the connection pin between the target data line and the memory under test; The detection of power supply noise generated by the target power supply signal in the memory under test based on the voltage signal includes: Based on the voltage fluctuation of the first voltage signal, the power supply noise generated by the target power supply signal in the memory under test is detected.

5. The power supply noise testing method for memory chips according to claim 4, characterized in that, The detection of power supply noise generated by the target power supply signal in the memory under test based on the voltage fluctuation of the first voltage signal includes: Determine the first voltage fluctuation rate of the first voltage signal; Power supply noise generated by the target power supply signal in the memory under test is detected based on the first voltage fluctuation rate.

6. The power supply noise testing method for memory chips according to claim 3, characterized in that, The step of writing the first test data to the memory under test via the data line includes: The first test data is generated by performing a bitwise AND operation between the preset first data pattern and the first control data. The first test data is written to the memory under test via a data cable; In the first control data, the data bits corresponding to the target data line are low-level data, and the data bits corresponding to other data lines are high-level data.

7. The power supply noise testing method for memory chips according to claim 1, characterized in that, The pins of the data lines connected to the memory under test are connected to the target voltage terminal via pull-up transistors and to the ground terminal via pull-down transistors, respectively. The target voltage terminal is used to output the target power supply signal. The test data includes second test data, and the target level signal is a high-level signal.

8. The power supply noise testing method for memory chips according to claim 7, characterized in that, The test data transmission via data cable to the memory under test includes: The second test data is read from the memory under test via the data cable.

9. The power supply noise testing method for a memory chip according to claim 8, characterized in that, The step of acquiring the voltage signal at the connection pin between the target data line and the memory under test includes: Obtain the second voltage signal at the connection pin between the target data line and the memory under test; The detection of power supply noise generated by the target power supply signal in the memory under test based on the voltage signal includes: Based on the voltage fluctuation of the second voltage signal, the power supply noise generated by the target power supply signal in the memory under test is detected.

10. The power supply noise testing method for a memory chip according to claim 9, characterized in that, The detection of power supply noise generated by the target power supply signal in the memory under test based on the voltage fluctuation of the second voltage signal includes: Determine the second voltage fluctuation rate of the second voltage signal; Power supply noise generated by the target power supply signal in the memory under test is detected based on the second voltage fluctuation rate.

11. The power supply noise testing method for a memory chip according to claim 8, characterized in that, The step of reading the second test data from the memory under test via the data cable includes: The second test data is generated by performing a bitwise OR operation between the second control data and the second data pattern pre-written into the memory to be tested. The second test data is read from the memory under test via a data cable; Wherein, the second control data corresponds to a high-level data bit for the target data line and a low-level data bit for the other data lines.

12. A power supply noise testing apparatus for a memory chip, using the power supply noise testing method for a memory chip as described in any one of claims 1-11, characterized in that, include: The control module is used to transmit test data with the memory under test via a data line. The data signal transmitted by the target data line in the data line is a target level signal, which is used to turn on the target power supply signal of the memory under test to the ground terminal. A voltage acquisition module is used to acquire the voltage signal at the connection pin between the target data line and the memory under test. The noise detection module is used to detect power supply noise generated by the target power supply signal in the memory under test based on the voltage signal.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the power supply noise testing method for the memory chip as described in any one of claims 1 to 11.

14. A testing device, characterized in that, include: One or more processors; A storage device for storing one or more programs, which, when executed by one or more processors, cause the one or more processors to implement the power supply noise test method for a memory chip as described in any one of claims 1 to 11.

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