A computer system and computer-implemented method and computer-readable storage medium

Abstract

The present disclosure describes a system and a computer-implemented method and a computer-readable storage medium. The method includes: extracting, by an access engine circuit implemented on a circuit board, partial structure data of a graph from one or more memory drivers of a plurality of memory drivers implemented on the circuit board; performing, by the access engine circuit, node sampling using the extracted partial structure data of the graph to select one or more sampled nodes; extracting, by the access engine circuit, partial attribute data of the graph from two or more memory drivers in parallel according to the selected one or more sampled nodes; sending, by the access engine circuit, the extracted partial attribute data of the graph to a host, the host being external to the circuit board; and performing, by one or more processors of the host, GNN processing on the graph using the extracted partial attribute data of the graph. The method can improve access performance of memory access for graph neural network (GNN) processing.

Description

Technical Field

[0001] This disclosure relates to the field of artificial intelligence technology, and in particular to a system, a computer-implemented method, and a computer-readable storage medium. Background Technology

[0002] While traditional deep learning models excel at pattern recognition and data mining by capturing hidden patterns in Euclidean data (such as images, text, and videos), graph neural networks (GNNs) have extended the capabilities of machine learning to non-Euclidean domains represented by graphs, where objects have complex relationships and interdependencies. Research shows that GNNs outperform current state-of-the-art technologies for applications ranging from molecular reasoning to community detection.

[0003] Graph neural networks (GNNs) are highly effective models for modeling and processing unstructured data. Recently, GNNs have been increasingly used in applications such as recommender systems and risk control systems. However, graph data is unstructured; therefore, accessing graph data may result in random access to memory. Summary of the Invention

[0004] In view of the above, embodiments of this disclosure provide a system, a computer-implemented method, and a computer-readable storage medium to solve the above problems.

[0005] According to one aspect, a system includes a host and a circuit board, the circuit board including: a plurality of memory drivers for storing structural data and attribute data of a graph; and access engine circuitry communicatively coupled to each of the plurality of memory drivers and the host, the access engine circuitry being configured to: extract partial structural data of the graph from one or more of the plurality of memory drivers; perform node sampling using the extracted partial structural data of the graph to select one or more sampling nodes; extract partial attribute data of the graph in parallel from two or more of the plurality of memory drivers based on the selected one or more sampling nodes; and send the extracted partial attribute data of the graph to the host; wherein the host is communicatively coupled to the circuit board for receiving partial attribute data of the graph from the circuit board, the host including: one or more processors for performing graph neural network (GNN) processing on the graph using the partial attribute data of the graph.

[0006] In some embodiments, the access engine circuitry is implemented on a field-programmable gate array (FPGA) located on a circuit board.

[0007] In some embodiments, the multiple memory drives on the circuit board in the system are solid-state drives (SSDs).

[0008] In some embodiments, multiple memory drives on a circuit board have the same storage capacity.

[0009] In some embodiments, the access engine circuitry is further configured to access the structural and attribute data of the graph from a memory location outside the circuit board.

[0010] In some embodiments, one or more processors of the host include a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a neural processing unit (NPU), or a graph neural network processing unit.

[0011] In some embodiments, the host further includes: one or more Double Data Rate Synchronous Dynamic Random-Access Memory (DDR SDRAM) communicatively coupled to one or more processors of the host and a circuit board, the one or more DDR SDRAMs being used to: store partial attribute data of a graph from the circuit board; and facilitate one or more processors of the host to perform GNN processing.

[0012] In some embodiments, the circuit board further includes a dedicated memory communicatively coupled to the access engine circuitry, the dedicated memory being one or more dual data rate synchronous dynamic random access memories (DDR SDRAM) and used to facilitate access control of the plurality of memory drives by one or more controllers.

[0013] In some embodiments, the host is communicatively coupled to multiple circuit boards, and the host communicates with multiple circuit boards in parallel.

[0014] In some embodiments, the host is also configured to: perform memory management on the multiple circuit boards using an open-channel controller of multiple access engine circuits in the multiple circuit boards.

[0015] According to another aspect, a computer-implemented method includes: extracting partial structural data of a graph from one or more memory drivers of a plurality of memory drivers implemented on a circuit board via an access engine circuit implemented on a circuit board; performing node sampling using the extracted partial structural data of the graph via the access engine circuit to select one or more sampling nodes; extracting partial attribute data of the graph in parallel from two or more memory drivers of the plurality of memory drivers based on the selected one or more sampling nodes via the access engine circuit; sending the extracted partial attribute data of the graph to a host located outside the circuit board via the access engine circuit; and performing graph neural network (GNN) processing on the graph using the extracted partial attribute data of the graph via one or more processors of the host.

[0016] According to another aspect, a non-transitory computer-readable storage medium stores instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising: extracting partial structural data of a graph from one or more memory drives of a plurality of memory drives implemented on a circuit board via access engine circuitry implemented on a circuit board; performing node sampling using the extracted partial structural data of the graph via access engine circuitry to select one or more sampling nodes; extracting partial attribute data of the graph in parallel from two or more memory drives of the plurality of memory drives based on the selected one or more sampling nodes via access engine circuitry; and sending the extracted partial attribute data of the graph to a host via access engine circuitry to enable the host to perform graph neural network (GNN) processing on the graph using the extracted partial attribute data of the graph, wherein the host is located outside the circuit board.

[0017] The system disclosed herein includes a circuit board comprising an access engine circuit. The access engine circuit accesses graph data on a memory driver on the circuit board and forwards the graph data to the host, thereby improving the host's access performance to graph data. This solution can, to some extent, address the performance bottleneck caused by random access to graph data. Attached Figure Description

[0018] These and other features of the systems, methods, and hardware devices disclosed herein, as well as the operational methods and functions of combinations of related elements and components of the structures, and the economics of manufacture, will become more apparent upon consideration of the following description and appended claims with reference to the accompanying drawings, which form part of this disclosure, and in which similar reference numerals denote corresponding portions. However, it should be understood that the drawings are for illustration and description only and are not intended to define any limitations of this disclosure.

[0019] Figure 1 This is a schematic diagram of an exemplary figure according to some embodiments of the present disclosure.

[0020] Figure 2 This is a schematic diagram of an exemplary system using a GNN accelerator architecture according to some embodiments of this disclosure.

[0021] Figure 3 This is a schematic diagram of an exemplary system for accelerating GNN performance according to some embodiments of the present disclosure.

[0022] Figure 4 This is a schematic diagram of an exemplary GNN access engine according to some embodiments of the present disclosure.

[0023] Figure 5 This is a schematic diagram of an exemplary system for accessing GNN data from one or more memories on a circuit board, according to some embodiments of this disclosure.

[0024] Figure 6 This is a schematic diagram of an exemplary circuit board for accessing GNN data from multiple memories on a circuit board, according to some embodiments of the present disclosure.

[0025] Figure 7 This is a schematic diagram of an exemplary system for accessing GNN data from multiple circuit boards, according to some embodiments of the present disclosure.

[0026] Figure 8 This is an exemplary method for accelerating GNN processing using one or more memories on a circuit board, according to some embodiments of this disclosure. Detailed Implementation

[0027] This disclosure is made in the context of a particular application and its requirements, and is intended to enable those skilled in the art to make and use embodiments. Various modifications to the embodiments of this disclosure will be apparent to those skilled in the art, and the general principles defined may be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. Therefore, this disclosure is not limited to the embodiments shown, but is accorded the broadest scope consistent with the principles and features of this disclosure.

[0028] Data can be structured or unstructured. Structured data can be organized according to a predefined data model or pattern. Unstructured data, however, cannot be organized using a predefined data model or predefined method. For example, text files (e.g., emails, reports, etc.) may contain information without a predefined structure (e.g., single letters or words). Therefore, unstructured data may contain irregularities and ambiguities, making it difficult to understand using traditional programs or data structures. Furthermore, accessing unstructured data from computer memory can involve numerous random memory accesses, making memory access cumbersome and inefficient.

[0029] One way to represent unstructured data is using graphs. A graph is a data structure that consists of two components: nodes (or vertices) and edges. For example, a graph G can be defined as a set of nodes V and a set of edges E connecting those nodes V. Nodes in a graph can have a set of features or attributes (e.g., user profiles in a graph representing a social network). If two nodes are connected by an edge, one node is defined as an adjacent node of the other. Graphs are highly flexible data structures because they do not require predefined rules to determine how many nodes they contain or how the nodes are connected by edges. Because graphs offer great flexibility, they are one of the most widely used data structures for storing or representing unstructured data, such as text files. For example, graphs can store data with relational structures, such as data on relationships between buyers or products in an online shopping platform.

[0030] Figure 1 This is a schematic diagram of an exemplary figure according to some embodiments of the present disclosure. (e.g.) Figure 1 As shown, Figure 100 includes nodes n111, n112, n113, n114, n115, and n116. Furthermore, Figure 100 includes edges e121, e122, e123, e124, e125, e126, and e127. Each node has one or more adjacent nodes. For example, node n112 shares edge e121 with node n111, and node n113 shares edge e122 with node n111; therefore, nodes n112 and n113 are adjacent to node n111.

[0031] When storing graphs in computer memory, nodes, edges, and attributes can be stored in many different data structures. One approach to storing a graph is to separate attribute data from its corresponding nodes. For example, node identifiers can be stored in an array, with each identifier providing an address or pointer to the location of the attribute data for that node. The attribute data for all nodes can be stored together and accessed by reading the address or pointer stored in the corresponding node identifier. By separating attribute data from its corresponding nodes, the data structure provides faster traversal access to the graph.

[0032] Graph Neural Networks (GNNs) are a type of neural network that can directly manipulate graphs. GNNs are better suited for graph operations than traditional neural networks (e.g., convolutional neural networks) because they can better adapt to graphs of arbitrary size or complex topology. GNNs can perform inference on data described in graph format. GNNs are capable of performing node-level, edge-level, or graph-level prediction tasks.

[0033] GNN processing involves both GNN training and GNN inference, both of which involve GNN computation. Typical GNN computation for a node (or vertex) involves aggregating features (e.g., attribute data) from its neighbors (direct neighbors or neighbors of each neighbor), and then computing the node's new activation to determine its feature representation (e.g., feature vector). Therefore, GNN processing with a small number of nodes typically requires input features from a large number of nodes. Using all neighboring nodes for message aggregation is too costly because the number of nodes required for input features can easily cover a large portion of the graph, especially in massive real-world graphs (e.g., with hundreds of millions of nodes and billions of edges).

[0034] To make GNNs more suitable for these real-world applications, node sampling is often employed to reduce the number of nodes involved in message / feature aggregation. For example, positive and negative sampling can be used to determine the optimization objective and outcome variance in GNN processing. For a given root node whose feature representation is being computed, positive sampling can sample graph nodes that are connected to the root node (directly or indirectly) via edges (e.g., connected to the root node and within a preset distance from the root node); negative sampling can sample nodes that are not connected to the root node via edges (e.g., beyond a preset distance from the root node). The nodes obtained through positive and negative sampling can be used to train feature representations of root nodes with different objectives.

[0035] To perform GNN calculations, the system can retrieve graph data from memory and send the data to one or more processors for processing. Figure 2 This is a schematic diagram of an exemplary system using a GNN accelerator architecture according to some embodiments of this disclosure. Figure 2 As shown, system 200 includes one or more processors 210, a GNN accelerator 220, memory 230, and one or more dedicated processors 240. In some embodiments, the one or more processors 210 include one or more central processing units (CPUs). In some embodiments, the one or more dedicated processors 240 may include one or more CPUs, one or more graphics processing units (GPUs), one or more tensor processing units (TPUs), one or more neural network processing units (NPUs), one or more dedicated graph neural network processing units, etc. In some embodiments, memory 230 may include synchronous dynamic random access memory (SDRAM), such as dual data rate synchronous dynamic random access memory (DDR SDRAM).

[0036] like Figure 2As shown, the GNN accelerator 220 can receive instructions and information about the GNN from one or more processors 210 and retrieve GNN-related data from memory 230. After receiving data from memory 230, the GNN accelerator 220 can preprocess the data and send the preprocessed data to one or more dedicated processors 240 for further processing.

[0037] In some embodiments, such as Figure 2 As shown, the GNN accelerator 220 includes a graph structure processor 221, a GNN sampler 222, a GNN attribute processor 223, and an address mapper 224. The graph structure processor 221 is configured to receive instructions and information about the GNN from one or more processors 210 and retrieve information about one or more root nodes and their edges from memory 230. The graph structure processor 221 then sends the retrieved information to the GNN sampler 222.

[0038] GNN sampler 222 is configured to select one or more sampling nodes for GNN processing based on edge information of one or more root nodes. In some embodiments, GNN sampler 222 selects one or more sampling nodes based on positive or negative sampling. For example, based on positive sampling, one or more sampling nodes are selected from nodes connected to one or more root nodes via edges (e.g., adjacent to one or more root nodes). Based on negative sampling, one or more sampling nodes are selected from nodes not directly connected to one or more root nodes via edges (e.g., not adjacent to or close to one or more root nodes). In some embodiments, positive sampling selects from the neighboring nodes of the root node, which are connected to the root node and within a preset distance from the root node. The connection can be a direct connection (one edge between the source node and the target node) or an indirect connection (multiple edges from the source node to the target node). The "preset distance" can be configured according to the implementation. For example, if the preset distance is 1, it means that only directly connected neighboring nodes are selected for positive sampling. If the preset distance is infinite, it means that there is no connection between the nodes (including direct and indirect connections). Negative sampling selects from nodes outside the preset distance from the root node. It is understandable that any algorithm other than positive sampling and negative sampling can be used to select sampling nodes.

[0039] After selecting sampling nodes, GNN sampler 222 sends the sampling node selection information to GNN attribute processor 223. Based on the sampling node information, GNN attribute processor 223 can be configured to retrieve the sampling node information from memory 230. In some embodiments, the sampling node information includes one or more features or attributes (also referred to as attribute data) for each sampling node. GNN attribute processor 223 can be further configured to send the retrieved sampling node information, along with information about one or more root nodes and their edges, to dedicated processor 240. Dedicated processor 240 performs GNN processing based on the information received from GNN attribute processor 223.

[0040] In some embodiments, the graph structure processor 221 and the GNN attribute processor 223 use an address mapper 224 to retrieve information from memory 230. The address mapper is configured to provide hardware address information in memory 230 based on node and edge information. For example, using identifier n111 (e.g., Figure 1 The graph structure processor 221 identifies the root node (n111) as part of the input GNN. If the graph structure processor 221 needs to extract information about node n111 (e.g., attribute data of node n111), the graph structure processor 221 provides the identifier n111 to the address mapper 224, and the address mapper 224 determines the physical address of the location in memory 230 for storing the information about node n111 (e.g., attribute data of node n111). In some embodiments, the address mapper 224 also determines the edges (e.g., edges) of node n111 in memory 230 for storing node n111. Figure 1 The location of one or more physical addresses of the edge e121 and e122).

[0041] Figure 2 The system 200 shown can be used in many different systems to accelerate memory access of GNNs to improve GNN performance. Figure 3 This is a schematic diagram of an exemplary system for accelerating GNN performance according to some embodiments of this disclosure. Figure 3 As shown, the acceleration system 300 includes a memory over fabric (MoF) 305, an access engine 310, a RISC-CV 330, a general matrix multiply (GEMM) execution engine 340, and a vector processing unit (VPU) execution engine 350. Figure 3 The access engine 310 shown is similar to Figure 2 The GNN module 220 is shown. The access engine 310 can be configured to access memory (e.g., as...). Figure 2The DDR (as shown) retrieves the data required to perform GNN calculations. For example, access engine 310 retrieves node identifiers, edge identifiers, and attribute data corresponding to the node identifiers. The data retrieved by access engine 310 is provided to the execution engine (e.g., GEMM execution engine 340 or VPU execution engine 350) or the processor for GNN-related calculations. Figure 3 As shown, both types of engines can accelerate the execution of specific GNN-related calculations.

[0042] Although System 300 includes an acceleration engine and a processor to accelerate GNN-related computations, the access engine 310 may become a bottleneck for the overall performance of System 300 because data retrieval performed by the access engine 310 may be slower than that performed by the execution engine. Figure 4 This is a schematic diagram of an exemplary GNN access engine according to some embodiments of the present disclosure. It will be understood that... Figure 4 The access engine 400 shown is similar to Figure 3 The access engine 310 is shown. (As shown) Figure 4 As shown, the access engine 400 may include the GetNeighbor module 410, the GetSample module 420, the GetAttribute module 430, and the GetEncode module 440.

[0043] In some embodiments, the GetNeighbor module 410 is configured to access or identify neighboring nodes of an input node identifier. For example, with Figure 2 Similar to the graph architecture processor 221 shown, the GetNeighbor module 410 receives instructions and information about the GNN and retrieves them from DDR (e.g., corresponding to...). Figure 2 The GetNeighbor module 410 retrieves information about one or more nodes, their edges, and their neighbors (adjacent nodes) from the memory 230. The GetNeighbor module 410 then sends the retrieved information to the GetSample module 420 (e.g., corresponding to...). Figure 2 The GNN sampler 222).

[0044] In some embodiments, the GetSample module 420 is configured to receive information from the GetNeighbor module 410 on one or more nodes and perform node sampling on those one or more nodes for GNN processing. For example, with Figure 2Similar to the GNN sampler 222 shown, the GetSample module 420 is configured to select one or more sampling nodes for GNN processing based on edge information of one or more nodes. In some embodiments, the GetSample module 420 selects one or more sampling nodes based on positive sampling and / or negative sampling. After selecting the sampling nodes, the GetSample module 420 sends the selection information of the sampling nodes to the GetAttribute module 430.

[0045] In some embodiments, the GetAttribute module 430 is configured to receive information about the selected node or sample node from the GetSample module 420, and from memory (e.g., Figure 4 The DDR or shown Figure 2 The memory 230 shown retrieves attribute information from the sampled nodes. For example, similar to the GNN attribute processor 223, the GetAttribute module 430 is configured to retrieve attribute data of the sampled nodes from the memory 230 based on received sampled node information (e.g., the identifier of the sampled node). In some embodiments, the GetAttribute module needs to retrieve attribute information of the sampled nodes from a remote location. For example, the GetAttribute module needs to retrieve attribute information from another board. Therefore, the GetAttribute module utilizes the MoF module 450 to retrieve attribute information from a remote location (e.g., another board). In some embodiments, the attribute data of the sampled nodes includes one or more features of each sampled node.

[0046] like Figure 2 , Figure 3 and Figure 4 As shown, the system retrieves graph data (e.g., structural and attribute data) from local memory (e.g., DDR or a similar memory type). It is noteworthy that these systems can be implemented on a Field Programmable Gate Array (FPGA). Therefore, for faster memory access, local DDR can be implemented on the same FPGA. However, implementing local DDR or similar memory on an FPGA or similar circuit is costly. Furthermore, DDR has limited storage capacity. For graphs with large storage capacities (e.g., greater than 50 GB), a locally implemented DDR may not be able to store a single graph without incurring significant costs. While the system can optionally retrieve graph data from a remote location via a MoF (e.g., MoF module 450), this memory access results in longer latency, further increasing the system's inefficiency. Embodiments of this disclosure provide hardware systems and methods that offer a scheme capable of balancing the storage of graph data with the access to memory.

[0047] Figure 5This is a schematic diagram of an exemplary system for accessing GNN data from one or more memories on a circuit board, according to some embodiments of this disclosure. Figure 5 As shown, system 500 includes a host 540 and a graphic access engine (GAE) board 510. The host 540 is communicatively coupled to the GAE board 510. In some embodiments, the host 540 is communicatively coupled to the GAE board 510 via a peripheral component interconnect express (PCIe) connection. In some embodiments, the host 540 is communicatively coupled to a network interface controller (NIC) 520 (e.g., via a PCIe connection). The network interface controller 520 is configured to connect the host 540 to a computer network (e.g., a local network, the Internet, etc.), thereby allowing the host 540 to upload data to or download data from the computer network.

[0048] In some embodiments, Figure 5 The illustrated GAE board 510 includes one or more memories, such as a flash drive including a solid-state drive (SSD) 511, and an access engine 512. The SSD 511 and the access engine 512 are communicatively coupled (e.g., via a PCIe connection). It is understood that the SSD 511 and the access engine 512 are physically located on the same circuit board (i.e., GAE board 510). This reduces or minimizes latency in data communication between the access engine 512 and the SSD 511. The SSD 511 is configured to store graph data, such as structural data (e.g., node identifiers, neighbor nodes, etc.) or attribute data. In some embodiments, the SSD 511 is configured to store structural data and attribute data of the graph data, respectively. It is understood that the SSD 511 may include one or more SSDs.

[0049] In some embodiments, Figure 5 The access engine 512 shown is similar to Figure 3 The access engine 310 shown or Figure 4 The access engine 400 is shown and includes one or more modules or circuits from access engine 310 or access engine 400, such as GetNeighbor module 410, GetSample module 420, GetAttribute module 430, or GetEncode module 440. For example, access engine 512 may include sampling module 513 and extraction module 514. In some embodiments, access engine 512 is programmed and implemented on an FPGA.

[0050] In some embodiments, sampling module 513 is configured to perform functions similar to those of GetNeighbor module 410 and GetSample module 420. For example, sampling module 513 acquires structural data (e.g., information about one or more nodes, their edges, and their neighbors) from solid-state drive 511, performs node sampling, and identifies the node identifiers of the sampled nodes. Sampling module 513 may be further configured to send the node identifiers of the sampled nodes to extraction module 514.

[0051] In some embodiments, the extraction module 514 is configured to perform functions similar to the GetAttribute module 430. For example, the extraction module 514 extracts attribute data of the sampled nodes from the solid-state drive 511 based on the node identifier of the sampled nodes. In some embodiments, after the extraction module 514 extracts the attribute data of the sampled nodes, the access engine 512 is configured to send the attribute data of the sampled nodes to the host 540. In some embodiments, the graph data may not be perfectly suited to the solid-state drive 511, so the extraction module 514 is configured to extract the attribute data of the sampled nodes from a remote location (e.g., an SSD located outside the GAE board 510).

[0052] In some embodiments, host 540 is configured to receive attribute data of sampled nodes from access engine 512 and perform GNN processing. For example, host 540 includes processor 541 and host DDR 542. Host 540 is configured to store attribute data of sampled nodes in host DDR 542. Processor 541 is configured to obtain attribute data of sampled nodes from host DDR 542 and perform graph neural network processing using the extracted attribute data of sampled nodes. In some embodiments, the processor is similar to Figure 2 The processor 210 or dedicated processor 240 shown is used. In some embodiments, the host DDR 542 does not have sufficient storage capacity to store the entire graph data. In fact, in some embodiments, the host DDR 542 does not even have sufficient storage capacity to store the attribute data of all neighbors. However, since the access engine 512 performs node sampling on neighbor nodes, and the data transferred from the access engine 512 to the host DDR 542 includes the attribute data of the sampled nodes, the host DDR 542 does not need to have sufficient storage capacity to store the entire graph, or even sufficient storage capacity to store the attribute data of all neighbors. Therefore, the system design on the host 540 can be simplified so that the host 540 does not need to implement an expensive host DDR with a large storage capacity. In some embodiments, the host DDR 542 includes one or more DDRs.

[0053] Figure 6This is a schematic diagram of an exemplary circuit board for accessing GNN data from multiple memories on a circuit board, according to some embodiments of this disclosure. Figure 6 As shown, the GAE board 600 includes an access engine 610 and multiple storage devices (e.g., flash drives such as SSDs). For example, as... Figure 6 As shown, the GAE board 600 includes 10 SSDs. In some embodiments, each SSD on the GAE board 600 is communicatively coupled to an access engine 610, and multiple SSDs are accessed in parallel by the access engine 610. In some embodiments, one or more SSDs are communicatively coupled to the access engine 610 via a PCIe or PCIe switch. In some embodiments, the GAE board 600 may be equipped with an M.2 connection for connecting to... Figure 5 The host 540 is located in the system. In some embodiments, the GAE board 600 is similar to the GAE board 510, the multiple SSDs are similar to solid-state drives 511, and the access engine 610 is similar to the access engine 512.

[0054] In some embodiments, the access engine 610 includes a memory controller configured to regulate and perform memory accesses to graph data on multiple SSDs. In some embodiments, each of the multiple SSDs has the same storage capacity. For example, each of the multiple SSDs has a storage capacity of 0.5 TB. In some embodiments, the multiple SSDs can be accessed in parallel. For example, the memory controller of the access engine 610 simultaneously extracts graph data from some or all of the multiple SSDs. Therefore, many SSDs can be implemented on the GAE board 600 and accessed in parallel by the access engine 610. As a result, although SSDs have longer latency for memory access compared to DDR, parallel access to multiple SSDs can compensate for the latency issue. Furthermore, accessing graph data (e.g., sampled graph data) involves random access to storage locations. Therefore, implementing multiple SSDs on the board and distributing graph data across multiple SSDs can leverage system design (e.g., Figure 6 The parallelism of multiple SSDs in the GAE 600 provides a more balanced approach to using SSDs for storing and accessing graph data, rather than using more expensive DDR in certain parts of the hardware design. This is understandable. Figure 6 The system design shown offers advantages for processing unstructured data types (but not graph data). For example, if accessing unstructured data types typically involves random access to memory locations and memory accesses can be performed in parallel, then... Figure 6 The system design shown can still provide a balance between cost and memory access efficiency for unstructured data types.

[0055] In some embodiments, the number of SSDs to be implemented on the GAE board 600 is determined at least based on the bandwidth between each SSD and the access engine. For example, if the bandwidth between an SSD and the access engine is 0.5 GB / s, and the total bandwidth requirement for accessing sampled attribute data is 4 GB / s, then the number of SSDs to be implemented on a single GAE board is 8. In some embodiments, the storage capacity of each SSD is determined at least based on an estimate of the size of the graph to be stored. For example, if the size of the graph to be stored is typically less than 4 TB, and up to 8 SSDs can be implemented on the GAE board 600, then a storage capacity of 0.5 TB or higher per SSD is sufficient. In some embodiments, SSDs with smaller storage capacities are generally less expensive to implement. Therefore, if a storage capacity of 0.5 TB or higher per SSD is sufficient to meet system requirements, an SSD with a minimum storage capacity greater than 0.5 TB (e.g., 512 GB) can be selected for implementation.

[0056] In some embodiments, the GAE board 600 includes a memory 620 configured to facilitate memory access to multiple SSDs. In some embodiments, the memory 620 is a dedicated memory for the GAE board 600. In some embodiments, the memory 620 is DRAM (e.g., DDR-SDRAM, DDR4-SDRAM, etc.). In some embodiments, the memory 620 resides on the GAE board 600, separate from the access engine 610. For example, implementing a large dedicated memory on an FPGA would be costly if the access engine 610 were implemented on the FPGA. Therefore, the memory 620 is implemented separately from the FPGA to reduce costs. Meanwhile, the memory 620 remains on the same board as the access engine 610, thus maintaining the system's data transfer efficiency. In some embodiments, the access engine 610 is implemented on an application-specific integrated circuit (ASIC).

[0057] In some embodiments, access engine 610 is configured to use memory 620 to facilitate memory access to graph data. For example, when access engine 610 performs sampling or extraction of structural or attribute data from multiple SSDs, access engine 610 may store the data in memory 620 (e.g., as a memory buffer for performing memory access). In some embodiments, memory 620 may be used as both the GAE board 600 and the host (e.g., Figure 5 A memory buffer for communication between the host 540 and the host 620. For example, before the GAE board 600 transmits the sampled attribute data to the host, the sampled attribute data can be prepared for transmission from the memory 620 to the host (e.g., ...). Figure 5Before the host DDR 542, the sampled attribute data is extracted block by block and stored in the memory 620.

[0058] The GAE board 600 can be configured to connect to a host (e.g., host 540). In some embodiments, the connection between the GAE board 600 and the host is based on a PCIe or PCIe switch. In some embodiments, the memory controller is an Open Channel controller, and the host is configured to perform memory management via the Open Channel controller on the access engine 610 (e.g., via the operating system on the host).

[0059] In some embodiments, the host is communicatively coupled to multiple GAE boards. Figure 7 This is a schematic diagram of an exemplary system for accessing GNN data from multiple circuit boards, according to some embodiments of this disclosure. Figure 7 As shown, the host 710 is connected to multiple GAE boards 720. In some embodiments, the host 710 communicates in parallel with two or more GAE boards 720. In some embodiments, graph data of a graph is stored on multiple GAE boards 720, and the graph data can be accessed by the host 710 in parallel. Figure 7 The system design shown allows for further expansion of the GAE board's functionality to accommodate diagrams requiring storage capacity beyond that of a single GAE board. In some embodiments, the host 710 is similar to... Figure 5 The host 540, and each of the multiple GAE boards 720 can be similar to Figure 6 The GAE board 600 shown is shown.

[0060] In some embodiments, each of the plurality of GAE boards 720 is similar to one another. For example, each of the plurality of GAE boards 720 has the same number of SSDs, and each SSD has the same storage capacity. When the hardware architecture on each GAE board is similar, memory access management of the system can be improved because, for example, the host 710 can better predict the available storage capacity of each GAE board and perform data storage or data retrieval accordingly. In some embodiments, the host 710 is configured to perform memory management across each of the plurality of GAE boards 720 via an open channel controller on the access engine 721 (e.g., via an operating system on the host 710).

[0061] Figure 8 This is an exemplary method for accelerating GNN processing using one or more memories on a circuit board, according to some embodiments of this disclosure. Method 800 can be... Figure 5 , Figure 6 or Figure 7 Implemented in the environment shown. Method 800 can be derived from... Figure 5-7The device, apparatus, or system shown performs the procedure. Depending on the implementation, method 800 may include additional, fewer, or alternative steps performed in various sequences or in parallel.

[0062] Step 810 includes extracting partial structural data of the graph from one or more memory drives among a plurality of memory drives implemented on the circuit board. In some embodiments, the extraction operation is performed by access engine circuitry (e.g., Figure 5 Access engine 512 Figure 6 Access engine 610 or Figure 7 The access engine 721) is executed. In some embodiments, the access engine circuitry is located on a circuit board (e.g., Figure 5 GAE board 510, Figure 6 GAE board 600 or Figure 7 The access engine circuitry is implemented on a GAE board 720. In some embodiments, the access engine circuitry is implemented on an FPGA located on the board. In some embodiments, the multiple memory drives are SSDs (e.g., Figure 5 SSD 511, Figure 6 SSD or Figure 7 (SSDs). In some embodiments, multiple SSDs have the same storage capacity.

[0063] Step 820 includes performing node sampling using the extracted partial structural data of the graph to select one or more sampled nodes. In some embodiments, node sampling is performed by access engine circuitry. In some embodiments, in conjunction with... Figure 4 GetNeighbor module 410 Figure 4 GetSample module 420 or Figure 5 The sampling module 513 performs node sampling in a similar manner.

[0064] Step 830 includes extracting partial attribute data of the graph from multiple memory drives based on one or more selected sampling nodes. In some embodiments, the partial attribute data of the graph is extracted by access engine circuitry. In some embodiments, partial attribute data of the graph is extracted in parallel from two or more memory drives of the multiple memory drives. For example, as Figure 6 As shown, each SSD on the GAE board 600 is communicatively coupled to the access engine 610, and multiple SSDs can be accessed in parallel by the access engine 610. In some embodiments, the board includes dedicated memory communicatively coupled to the access engine circuitry. In some embodiments, the dedicated memory includes one or more DDR SDRAMs and is configured to facilitate access control of the multiple memory drives by one or more controllers.

[0065] Step 840 includes sending the extracted partial attribute data of the graph to the host. In some embodiments, the extracted partial attribute data of the graph is sent by the access engine circuitry. In some embodiments, the host is similar to... Figure 5 Host 540 or Figure 7 The host 710. In some embodiments, the host is located outside the circuit board and is communicatively coupled to the circuit board via a PCIe or PCIe switch.

[0066] Step 850 includes performing GNN processing on the graph using the extracted partial attribute data. In some embodiments, the GNN processing is performed by a host. In some embodiments, the host includes one or more processors configured to perform GNN processing (e.g., Figure 5 processor 541 or Figure 7 The processor 711). In some embodiments, one or more processors include one or more central processing units (CPUs), graphics processing units (GPUs), neural network processing units (NPUs), dedicated graph neural network processing units, etc. In some embodiments, some attribute data of the graph is stored in the host's DDR SDRAM (e.g., ...). Figure 5 The host DDR 542 or Figure 7 In a host DDR 712, DDR SDRAM can facilitate GNN processing by one or more processors of the host. In some embodiments, the host is communicatively coupled to multiple circuit boards, and the host is configured to communicate in parallel with the multiple circuit boards. The multiple circuit boards can be configured to store graph data of a graph. In some embodiments, the host is configured to perform memory management on the multiple circuit boards using an open channel controller of multiple access engine circuits in the multiple circuit boards.

[0067] Each process, method, and algorithm described in the preceding sections may be embodied in a code module executed by one or more computer systems or a computer processor containing computer hardware, and may be fully or partially automated by that code module. These processes and algorithms may be implemented, in part or in whole, in dedicated circuitry.

[0068] When the functions disclosed herein are implemented as software functional units and sold or used as standalone products, they may be stored in a non-volatile computer-readable storage medium executable by a processor. Specific technical solutions (all or part) disclosed herein, or aspects contributing to the prior art, may be embodied in the form of a software product. The software product may be stored in a storage medium comprising multiple instructions to cause a computing device (which may be a personal computer, server, network device, etc.) to perform all or some steps of the methods of the embodiments of this disclosure. The storage medium includes flash drives, portable hard disk drives, ROM, RAM, magnetic disks, optical disks, other media suitable for storing program code, or any combination thereof.

[0069] A further embodiment provides a system including a processor and a non-transitory computer-readable storage medium storing instructions executable by the processor to cause the system to perform operations corresponding to the steps in any of the methods of the above embodiments. The embodiment also provides a non-transitory computer-readable storage medium configured with instructions executable by one or more processors to cause one or more processors to perform operations corresponding to the steps in any of the methods of the above embodiments.

[0070] The embodiments disclosed herein can be implemented through a cloud platform, server, or group of servers (collectively referred to as the "Service System") that interacts with a client. The client can be a terminal device or a client registered by a user on the platform, wherein the terminal device can be a mobile terminal, a personal computer (PC), or any device that can have the platform application installed.

[0071] The various features and processes described above can be used independently of each other or combined in various ways. All possible combinations and sub-combinations are within the scope of this disclosure. Furthermore, certain method or process blocks may be omitted in some implementations. The methods and processes described herein are not limited to any particular sequence and can be executed in other suitable sequences, including associated blocks or states. For example, described blocks or states may be executed in a different order than the definitive disclosed sequence, or multiple blocks or states may be combined within a single block or state. Example blocks or states may be executed serially, in parallel, or in some other manner. Blocks or states may be added to or removed from the disclosed example embodiments. The configuration of the exemplary systems and components described herein may differ from that described. For example, elements may be added to, removed from, or rearranged from the disclosed exemplary embodiments compared to the disclosed exemplary embodiments.

[0072] The various operations of the exemplary methods described herein can be performed at least partially by an algorithm. This algorithm may be contained in program code or instructions stored in memory (e.g., the aforementioned non-transitory computer-readable storage medium). Such an algorithm may include a machine learning algorithm. In some embodiments, the machine learning algorithm does not explicitly program the computer to perform the function, but learns from training data to build a predictive model for performing that function.

[0073] The various operations of the example methods described herein can be performed at least partially by one or more processors, which are either temporarily configured (e.g., by software) or permanently configured to perform the relevant operations. Whether temporarily or permanently configured, these processors constitute the engine of a processor implementation that runs to perform one or more of the operations or functions described herein.

[0074] Similarly, taking one or more specific processors as hardware examples, the methods described herein can be implemented at least partially by a processor. For example, at least some operations of the methods can be performed by one or more processors or an engine implemented by a processor. Furthermore, one or more processors can also support the performance of the related operations in a "cloud computing" environment or as "Software as a Service" (SaaS). For example, at least some operations can be performed by a set of computers (as an example of a machine including processors), which can be accessed via a network (e.g., the Internet) and one or more appropriate interfaces (e.g., application programming interfaces (APIs)).

[0075] The performance of certain operations may be distributed across processors, residing not only within a single machine but also deployed across multiple machines. In some exemplary embodiments, the processor or processor-implemented engine may reside in a single geographic location (e.g., within a home environment, office environment, or server farm). In other exemplary embodiments, the processor or processor-implemented engine may be distributed across multiple geographic locations.

[0076] In this specification, multiple instances can be implemented as components, operations, or structures described as single instances. Although a single operation of one or more methods is shown and described as a separate operation, one or more individual operations can be performed simultaneously, and the operations do not need to be performed in the order shown. Structures and functions presented as separate components in the exemplary configuration can be implemented as composite structures or components. Similarly, structures and functions presented as single components can be implemented as separate components. These and other changes, modifications, additions, and improvements are within the scope of this document.

[0077] While a summary of the subject matter has been described with reference to specific exemplary embodiments, various modifications and alterations may be made to these embodiments without departing from the broader scope of embodiments of this disclosure. For convenience only, the term "disclosure" may be used herein, individually or in its entirety, to refer to such embodiments of the subject matter, and if multiple pieces of information or concepts are indeed disclosed, it is not intended to voluntarily limit the scope of this disclosure to any single piece of information or concept.

[0078] The embodiments shown herein have been described in sufficient detail to enable those skilled in the art to practice the disclosed teachings. Other embodiments may be used and derived therefrom, allowing for structural and logical substitutions and changes without departing from the scope of this disclosure. Therefore, the detailed description is not intended to be limiting, and the scope of the various embodiments is defined only by the appended claims and all their equivalents.

[0079] Any process description, element, or block in the flowcharts described herein and / or in the accompanying drawings should be understood as a potential representation of a module, segment, or code segment, including one or more executable instructions for implementing a specific logical function or step in the process. Alternative implementations are included within the scope of the embodiments described herein, wherein, as those skilled in the art will understand, depending on the functionality involved, elements or functions may be removed from what is shown or discussed, or elements or functions may be executed out of order (including substantially parallel or reverse execution).

[0080] Unless otherwise expressly stated or the context otherwise requires, the word "or" as used herein is inclusive rather than exclusive. Therefore, "A, B, or C" here means "A, B, A and B, A and C, B and C, or A, B, and C," unless otherwise expressly stated or the context otherwise requires. Furthermore, "and" is consequential unless otherwise expressly stated or the context otherwise requires. Therefore, "A and B" here means "A and B, together or separately," unless otherwise expressly stated or the context otherwise requires. Furthermore, multiple instances may be provided for a resource, operation, or structure described herein as a single instance. Moreover, the boundaries between various resources, operations, engines, and data stores are somewhat arbitrary, and a particular operation is illustrative within the context of a particular illustrative configuration. Other allocations of functionality may be envisioned and fall within the scope of various embodiments herein. In general, structures and functions presented as separate resources in exemplary configurations can be implemented as combined structures or resources. Similarly, structures and functions presented as single resources can be implemented as separate resources. These and other variations, modifications, additions, and improvements fall within the scope of embodiments of this disclosure as represented by the appended claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

[0081] The terms “comprising” or “including” are used to indicate the presence of a subsequently declared feature, but do not preclude the addition of other features. Unless otherwise expressly stated or otherwise understood in the context in which they are used, conditional language (e.g., “may”) is generally intended to convey that certain embodiments include certain features, elements, and / or steps that are not included in other embodiments. Therefore, such conditional language generally does not imply that one or more embodiments require features, elements, and / or steps in any way, or that one or more embodiments necessarily include logic for determining, with or without user input or prompting, whether such features, elements, and / or steps are included in or will be performed in any particular embodiment.

Claims

1. A computer system, comprising: The host, and Circuit board, the circuit board comprising: Multiple memory drives for storing structural and attribute data of a graph, said multiple memory drives including flash memory drives; and An access engine circuit, communicatively coupled to each of the plurality of memory drives and the host, wherein the access engine circuit is used for: Extract partial structural data of the graph from one or more of the plurality of memory drivers; Node sampling is performed using the extracted partial structural data of the graph to select one or more sampling nodes; Based on one or more selected sampling nodes, partial attribute data of the graph are extracted in parallel from two or more of the plurality of memory drives; and The extracted partial attribute data of the graph is sent to the host. The host is communicatively coupled to the circuit board and is used to receive partial attribute data of the diagram from the circuit board. The host includes: One or more processors are configured to perform graph neural network processing on the graph using partial attribute data of the graph.

2. The system according to claim 1, wherein, The access engine circuitry is implemented on a field-programmable gate array located on the circuit board.

3. The system according to claim 1, wherein, The multiple memory drivers on the circuit board are all solid-state drivers.

4. The system according to claim 3, wherein, The multiple memory drivers on the circuit board have the same storage capacity.

5. The system according to claim 1, wherein, The access engine circuitry is further configured to access the structural and attribute data of the graph from a storage location outside the circuit board.

6. The system according to claim 1, wherein, One or more processors of the host include a central processing unit, a graphics processing unit, a tensor processing unit, a neural network processing unit, or a graph neural network processing unit.

7. The system according to claim 1, wherein, The host also includes: One or more dual data rate synchronous dynamic random access memories (DRAMs) are communicatively coupled to one or more processors of the host and the circuit board, wherein the one or more DRAMs are used for: Store partial attribute data from the diagram of the circuit board; and This facilitates one or more processors of the host computer to perform GNN processing.

8. The system according to claim 1, wherein, The circuit board also includes a dedicated memory communicatively coupled to the access engine circuitry, the dedicated memory being one or more dual data rate synchronous dynamic random access memories and used to facilitate access control of the plurality of memory drivers by one or more controllers.

9. The system according to claim 1, wherein, The host is communicatively coupled to a plurality of the circuit boards, and the host communicates with the plurality of circuit boards in parallel.

10. The system according to claim 9, wherein, The host is also used to perform memory management on the plurality of said circuit boards using an open channel controller of the plurality of access engine circuits in the plurality of said circuit boards.

11. A computer-implemented method, comprising: Partial structural data of a graph is extracted from one or more memory drives among a plurality of memory drives implemented on the circuit board via an access engine circuit implemented on the circuit board, wherein the plurality of memory drives include flash memory drives; Through the access engine circuit, node sampling is performed using the extracted partial structural data of the graph to select one or more sampling nodes; Through the access engine circuit, partial attribute data of the graph is extracted in parallel from two or more memory drives among the plurality of memory drives, based on one or more selected sampling nodes; The access engine circuitry transmits extracted partial attribute data of the graph to a host located outside the circuit board; and One or more processors of the host computer perform graph neural network processing on the graph using extracted partial attribute data of the graph.

12. The method according to claim 11, wherein, The access engine circuitry is implemented on a field-programmable gate array located on the circuit board.

13. The method according to claim 11, wherein, The multiple memory drivers on the circuit board are all solid-state drivers.

14. The method according to claim 13, wherein, The multiple memory drivers on the circuit board have the same storage capacity.

15. The method of claim 11, further comprising: The structural and attribute data of the graph are accessed from a storage location outside the circuit board via the access engine circuit.

16. The method according to claim 11, wherein, One or more processors of the host include a central processing unit, a graphics processing unit, a tensor processing unit, a neural network processing unit, or a graph neural network processing unit.

17. The method of claim 11, further comprising: Partial attribute data of the diagram from the circuit board is stored through one or more dual data rate synchronous dynamic random access memories of the host. and The host facilitates the execution of GNN processing by one or more processors of the host through one or more dual data rate synchronous dynamic random access memories.

18. The method of claim 11, further comprising: The dedicated memory on the circuit board facilitates access control of the plurality of memory drivers by one or more controllers, wherein the dedicated memory is one or more dual data rate synchronous dynamic random access memories and is communicatively coupled to the access engine circuitry.

19. The method according to claim 11, wherein, The host is communicatively coupled to a plurality of the circuit boards, and the method further includes: communicating in parallel with the plurality of circuit boards through the host.

20. A non-transitory computer-readable storage medium storing instructions that, when executed by one or more processors, cause the one or more processors to perform the following operations: Partial structural data of a graph is extracted from one or more memory drives, including flash memory drives, from a plurality of memory drives implemented on the circuit board via an access engine circuit implemented on the circuit board. Through the access engine circuit, node sampling is performed using the extracted partial structural data of the graph to select one or more sampling nodes; Through the access engine circuit, partial attribute data of the graph is extracted in parallel from two or more memory drives among the plurality of memory drives, based on one or more selected sampling nodes; The access engine circuit sends the extracted partial attribute data of the graph to the host, so that the host can use the extracted partial attribute data of the graph to perform graph neural network processing on the graph, wherein the host is located outside the circuit board.

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