Memory clock driver, memory device, and operating method thereof

Abstract

Memory clock drivers, memory devices, and methods of operating memory devices, memory clock drivers are provided. A memory device includes two memory clock drivers disposed opposite each other across an array of memory cell rows. The memory clock drivers include decoders that decode addresses corresponding to one or more memory cell rows. The decoders are configured to decode the addresses to provide a plurality of word line signals to the corresponding memory cell rows. The memory device also includes a row selection circuit that receives a row selection address and activates a corresponding memory cell row. The memory device includes control circuitry to control the memory cell array at local and global levels, and includes I / O modules to send signals to different parts of the memory device and to integrate the memory device into external devices.

Description

Technical Field

[0001] Embodiments of the present invention relate to memory clock drivers, memory devices, and methods of operation thereof. Background Technology

[0002] Memory devices are used to store data, typically in an array of rows and columns. A memory device receives the address of the data to be accessed, and uses that address to activate a portion of the array to access the requested data. In some memory devices, a row is activated by clock addressing to that row. Summary of the Invention

[0003] According to one aspect of the present application, a memory device is provided, comprising: a plurality of memory cells in a plurality of rows; a first memory clock driver disposed on a first side of the plurality of rows; and a second memory clock driver disposed on a second side of the plurality of rows opposite to the first side, wherein the first memory clock driver and the second memory clock driver are configured to transmit word line clock signals in response to a master clock signal to activate rows of memory cells in the plurality of rows using the first memory clock driver and the second memory clock driver.

[0004] According to another aspect of the embodiments of this application, a method for operating a memory device is provided, comprising the steps of: decoding the address of a memory cell row at a first memory clock driver; activating the memory cell row corresponding to the address via a first memory clock driver and a second memory clock driver, wherein the second memory clock driver is positioned on the side of a plurality of memory cells in a plurality of rows opposite to the first memory clock driver.

[0005] According to another aspect of the embodiments of this application, a memory clock driver circuit is provided, the memory clock driver circuit being coupled to a memory cell array, the memory clock driver circuit including: a first memory clock driver disposed on a first side of a plurality of rows of memory cells, and a second memory clock driver disposed on a second side opposite to the first side of the plurality of rows, wherein the first memory clock driver and the second memory clock driver are configured to transmit word line clock signals in response to a master clock signal to activate the rows of memory cells in the plurality of rows through conductive lines coupled between the first memory clock driver and the second memory clock driver. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 This is a block diagram depicting a memory device comprising multiple memory cell arrays according to some embodiments, each memory cell array having two memory clock drivers disposed opposite to each other.

[0008] Figure 2 This is a circuit diagram depicting a memory cell array of a memory device having two memory clock drivers arranged opposite each other and exemplary local control circuitry for selecting rows of memory cells, according to some embodiments.

[0009] Figure 3 This is a block diagram depicting the layout of a memory device comprising a plurality of memory cell arrays according to some embodiments, the memory cell array having two memory clock drivers disposed opposite to each other and associated control devices.

[0010] Figure 4 This is a block diagram depicting the layout of a memory device comprising an array of multiple memory cells according to some embodiments, the memory cell array having two memory clock drivers disposed opposite to each other and control devices associated with a number of signal lines.

[0011] Figure 5 It describes, according to some embodiments, in the time domain Figure 2 Timing diagram of the signals at both ends of the memory clock signal line of the memory cell array.

[0012] Figure 6 It is a circuit diagram depicting a memory cell array of a memory device according to some embodiments, having two memory clock drivers arranged opposite to each other and circuitry for selecting rows, wherein the two memory clock drivers are directly electrically coupled to word line clock signal lines.

[0013] Figure 7 It describes, according to some embodiments, in the time domain Figure 6 Timing diagram of the signals at both ends of the memory clock signal line of the memory cell array.

[0014] Figure 8 This describes example circuitry, including an implementation for a memory clock driver, according to some embodiments. Figure 2 The circuit diagram of the memory cell array.

[0015] Figure 9 This is a circuit diagram depicting an array of memory cells including example circuitry for a memory clock driver implementation, according to some embodiments.

[0016] Figure 10 This is a flowchart depicting the steps of an example method for operating a memory clock driver according to some embodiments. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0019] A semiconductor memory may include at least one two-dimensional array of memory cells in which information is stored. Word lines may be configured to select rows of the memory cell array to activate cells, and bit lines to select columns whose cells are accessed (i.e., read or written). When word lines and bit lines are activated, specific memory cells connected to word lines and bit lines are selected.

[0020] To activate a word line, the word line voltage is typically set to a high voltage, equal to the positive supply voltage in a complementary metal-oxide-semiconductor (CMOS) circuit. Setting the word line to a low voltage, which is complementary to the positive supply voltage, deactivates it. While the low voltage is typically set to ground or 0V, the value of the high voltage can vary depending on the semiconductor manufacturing technology. For example, in deep submicron technology, the high voltage can be 1.2V or even lower, while in submicron technology, it can be 2.5V. However, for a given memory chip and a given technology, the high voltage is usually designed to be a fixed value, especially for CMOS memory circuits.

[0021] Memory clocks are typically used to time the activation of numerous word lines in a memory device. Some implementations of word line driver circuitry in memory devices utilize a single memory clock driver to select and drive specific rows of memory cells in the memory array. This approach using a single memory clock driver is susceptible to timing issues, such as time contamination delays in the signal generated by the memory clock driver. Contamination delays occur in digital circuits when the input changes and, as the changed input value propagates through components or sections of the circuit, the corresponding change in the output value lags behind the input change. Contamination delays are particularly problematic for high-speed applications, including computation and memory applications, because delays can lead to unexpected errors if the expected output value of an event does not arrive in time. In memory circuits driven by a single memory clock driver, this can result in word lines relatively far from the memory clock driver being activated or driven near the memory clock driver. This can lead to fewer expected rows of memory cells being updated at the correct time with the correct set of information. Otherwise, to ensure the avoidance of such errors, the circuit may need to operate at a lower speed to allow time for the output state to change while experiencing contamination delays. In this case, time delay becomes a speed limiting factor for safe operation of the circuit. These scenarios are not ideal for memory devices, where both accuracy and speed are critical.

[0022] In memory devices implemented using a single memory clock driver, contamination delay occurs in the memory clock signal when the memory clock driver changes state to activate or deactivate a specific row of memory cells, and the voltage change requires a finite amount of time to propagate across the length of the word line. Therefore, the magnitude of the contamination delay and the associated risk of errors are greatest at the end of the word line furthest from the memory clock driver, where changes in the signal on the word line generated by the memory clock driver take the longest to arrive. In high-speed circuits, this can result in the required row of memory cells not being activated in time to store information, leading to errors. Alternatively, as previously described, it may be necessary to reduce the speed of the circuit to prevent such errors.

[0023] Some embodiments described herein can mitigate the risk of contamination by implementing a second memory clock driver at the opposite end of the memory clock line from the first memory clock driver. In this configuration, the two memory clock drivers pull both sides of the memory clock line to the desired voltage, eliminating contamination delays associated with voltage variations propagating across the memory clock line to the ends of the memory clock line from a single memory clock driver.

[0024] Figure 1This is a block diagram depicting a memory device 100 including a plurality of memory cell arrays 110 according to some embodiments, each memory cell array 110 having a first memory clock driver 120 and a second memory clock driver 121 disposed opposite to each other. Each of the memory cell arrays 110 includes a plurality of memory cell rows 111 and is electrically coupled to a corresponding row selection circuit 130, which activates and selects the memory cell row 111 by transmitting a local control output signal 151 to the memory cell row 111 to be selected.

[0025] In one embodiment, global control circuitry 140 provides primary control over memory device 100. Global control circuitry 140 generates appropriate internal signals to perform a requested operation within memory device 100 and outputs the signals as global control output 152. In another embodiment, global control circuitry 140, used to generate global control output 152, receives input from the external world (e.g., chip-level input).

[0026] The first memory clock driver 120, the second memory clock driver 121, and the row selection circuit 130 are electrically coupled to the global control output 152. At positions 153 and 154, the first memory clock driver 120 and the second memory clock driver 121 receive and are driven the first address of the memory cell row 111. In some embodiments, the memory clock drivers 120 and 121 also receive a master clock signal at positions 153 and 154, respectively. In some embodiments, the first memory clock driver 120 receives the master clock signal at position 153, and transmits the master clock signal at position 155 to the second memory clock driver 121, while the second memory clock driver 121 does not receive the master clock signal at position 154. The first memory clock driver 120 and the second memory clock driver 121 decode the first address received at positions 153 and 154 and drive the word line clock corresponding to the first address at position 156, the first address being input to the row selection circuit 130. At position 157, row selection circuit 130 receives the row selection address to select the corresponding memory cell row 111. Then, row selection circuit 130 drives and selects the appropriate memory cell row 111 based on the inputs it receives at positions 156 and 157.

[0027] Figure 2 This is a circuit diagram 200 depicting a memory cell array 110 of a memory device having a first memory clock driver 120 and a second memory clock driver 121 arranged opposite to each other and an example row selection circuit 130 for selecting memory cell rows 111, according to some embodiments. Figure 2The devices depicted correspond to a single memory cell array 110 and corresponding first memory clock driver 120 and second memory clock driver 121, as well as a row selection circuit 130 for selecting and driving. Figure 1 The memory cell array 110 depicted has rows 111 of memory cells. A first memory clock driver 120 is disposed on a first side of the memory cell array 110. A second memory clock driver 121 is disposed on a second side of the memory cell array 110 opposite to the first memory clock driver 120.

[0028] The first memory clock driver 120 and the second memory clock driver 121 are both electrically coupled to a plurality of conductive word line clock signal lines (“WLCS lines”) 206. In some embodiments, the number of WLCS lines 206 corresponds to the number of memory cell rows 111. Each WLCS line 206 is electrically coupled at a first end to the first memory clock driver 120 to receive the output of the first memory clock driver 120 and at a second end to the second memory clock driver 121 to receive a corresponding output of the second memory clock driver 121, such that when the same input value is given to the first memory clock driver 120 and the second memory clock driver 121, the outputs of the first memory clock driver 120 and the second memory clock driver 121 provide the same signal to the WLCS line.

[0029] In some embodiments, a master clock signal 207 is received as an input to a first memory clock driver 120 and transmitted by the first memory clock driver 120 to a second memory clock driver 121 at position 155. Both the first and second memory clock drivers 120 and 121 receive an address 209 corresponding to a memory cell row 111 in the memory cell array 110 to be activated. In some embodiments, address 209 has n / 2 bits, where n is the number of memory cell rows in the memory cell array 110.

[0030] Upon receiving an address 209 corresponding to a row of memory cells in memory cell array 110, the first memory clock driver 120 and the second memory clock driver 121 decode the address 209 and activate the WLCS line 206 corresponding to the address 209 and the row of memory cells in memory cell array 110 to be activated. The activation of the WLCS line in WLCS line 206 occurs at a timed interval with clock signal 207. The activated WLCS line in WLCS line 206 is driven at both ends by the first memory clock driver 120 and the second memory clock driver 121.

[0031] WLCS line 206 is received as input by row selection circuit 130. Row selection circuit 130 also receives row selection address 210, which corresponds to the memory cell row 111 to be selected in memory cell array 110 as input. In some embodiments, row selection address 210 consists of a thermometer code with n*2 bits, where n is the number of memory cell rows 111 in memory cell array 110. In some embodiments, two bits of address 210 correspond to each memory cell row 111 in memory cell array 110.

[0032] In some embodiments, row selection circuit 130 includes row selection circuit 211 corresponding to each memory cell row 111 in memory cell array 110. In embodiments, row selection circuit 211 includes multiple stages. Row selection circuit 211 includes a first stage 212, which consists of a logic AND gate receiving a row selection address 210 as input. The output of the first stage 212 is received by a second stage 213, which includes a logic NAND gate and also receives a WLCS line corresponding to the memory cell row 111 of memory cell array 110 corresponding to row selection circuit 211. A third stage 214 of row selection circuit 211 consists of a logic NOT gate receiving the output of second stage 213 as input. The output of third stage 214 is electrically coupled to the memory cell row of memory cell array corresponding to row selection circuit 211.

[0033] When two logic high bits of address 210 are received at stage 212, stage 1 outputs a logic high signal, which is received by the NAND gate at stage 213. When stage 213 receives the logic high signal from stage 1 and the high signal on the corresponding WLCS line in WLCS line 206, stage 213 outputs a logic low signal. When a logic low signal is received from stage 213 at stage 214, stage 214 outputs a logic high signal, which activates the corresponding memory cell row 111 of memory cell array 110. Various memory cell types (e.g., static random access memory (SRAM) cells, dynamic random access memory (DRAM) cells, etc.) can be used to implement memory cells 215 of memory cell array 110.

[0034] Figure 3This is a block diagram depicting the layout of a memory device 300 including a plurality of memory cell arrays 110 according to some embodiments. The memory cell arrays 110 have two memory clock drivers 120, 121 disposed opposite to each other and associated control devices. According to some embodiments, the memory device 300 includes a plurality of memory cell arrays 110. Each of the memory cell arrays 110 includes a plurality of memory cells (e.g., static random access memory (SRAM) cells, dynamic random access memory (DRAM) cells, etc.) arranged in rows and columns.

[0035] Word lines WL[0]-[n] select the respective rows of the memory cell array 110. A first memory clock driver 120 is disposed on a first side of each memory cell array 110, and a second memory clock driver 121 is disposed on the opposite side of each memory cell array 110. The first memory clock driver 120 is electrically coupled to a first end of a plurality of conductive lines 206, and the second memory clock driver 121 is electrically coupled to a second end of a plurality of conductive lines 206, which serve as... Figure 2 The WLCS line 206 in the memory cell array 110. The plurality of conductive lines 206 include one line corresponding to each memory cell row in the memory cell array 110, and drive the corresponding word lines WL[0]-[n] of each memory cell row. In some embodiments, the first memory clock driver 120 transmits the master clock signal 155 to the second memory clock driver 121. In some embodiments, the first memory clock driver 120 and the second memory clock driver 121 are disposed between the two memory cell arrays 110.

[0036] In some embodiments, the memory device 300 includes a plurality of memory cell arrays 305, 307, wherein each memory cell array 305, 307 includes a plurality of memory cell arrays 110. In one embodiment, each memory cell array 305, 307 is controlled by a local control circuit 304, which includes control circuitry configured to control the operation of a first memory clock driver 120 and a second memory clock driver 121. In one embodiment, a global control circuit 309 controls the memory device 300 as a whole by generating signals and sending them to the local control circuit 304 to perform a requested operation. The local control circuit 304 then generates additional signals based on signals received from the global control circuit 309 to perform the requested operation, and transmits these signals to the first and second memory clock drivers 121. For example, based on signals received from the global control circuit 309, the local control circuit 304 generates signals to activate a specific first memory clock driver 120 and second memory clock driver 121 coupled to one of the memory cell arrays 110. Furthermore, in this embodiment, based on the signal received from the global controller 309, the local control circuit 304 generates a signal that is sent to the local input / output (I / O) 310.

[0037] In this embodiment, the global control circuit 309 is the main control block of the memory device 300. The global control circuit 309 uses control inputs received from the external world (e.g., chip-level inputs) and generates appropriate internal signals to perform the requested operation. In this embodiment, global I / O 311 is located next to the global control circuit 309 and close to the boundary of the memory device 300, such as... Figure 3 As shown. Global I / O 311 is coupled to the external world, allowing devices (e.g., processors, chips, etc.) to read from and / or write to memory device 300. Therefore, when reading data from memory device 300, data is read from memory cell array 110 and transferred to one or more of global I / O 311 so that the data can be received by the device. Similarly, when writing data to memory device 300, the device transfers data to one or more of global I / O 311 so that the data can be written to memory cell array 110.

[0038] In a memory device 300 that includes multiple memory cell arrays 110, such as Figure 3As shown, local I / O 310 is located next to local control circuitry 304. Local I / O 310 interfaces with bit lines from adjacent memory cell arrays 110 located above and below local I / O 310. Furthermore, local I / O 310 operates according to control signals from local control circuitry 304 to perform appropriate operations (e.g., read or write data) based on the selected bit line. Local I / O 310 also interfaces with global I / O 311. Specifically, in this embodiment, local I / O 310 (i) receives data to be written from global I / O 311, and (ii) sends data read from memory cell array 110 to global I / O 311.

[0039] Figure 4 This is a block diagram depicting the layout of a memory device 400 including multiple memory cell arrays 404, 406, 416, 418 according to some embodiments, the memory cell arrays 404, 406, 416, 418 having two memory clock drivers arranged opposite to each other for each memory clock driver 402, 403 and 413, 414, and control devices having a number of signal lines.

[0040] The memory device 400 includes a first memory clock driver 403 and a second memory clock driver 402 disposed between first and second memory cell arrays 404 and 406. Each of the memory cell arrays 404 and 406 includes a plurality of memory cells (e.g., static random access memory (SRAM) cells, dynamic random access memory (DRAM) cells, etc.) arranged in rows and columns. Word lines WL_L_TOP[0]-[n] and WL_R_TOP[0]-[n] select the respective rows of arrays 404 and 406, and bit lines ( Figure 4 (Not shown in the image) Select column.

[0041] First memory clock driver 403 and second memory clock driver 402 are coupled to the first and second ends of conductive lines WLCS_L_TOP[0]-[n] and WLCS_R_TOP[0]-[n], respectively, and are configured to drive the word lines WL_L_TOP[0]-[n] and WL_R_TOP[0]-[n], respectively. First memory clock driver 403 and second memory clock driver 402 are also electrically coupled to conductive line 425 carrying the master clock signal. Local control circuit 405 (also referenced above) Figure 3 (Description) Includes control circuitry configured to control the operation of the first memory clock driver 403 and the second memory clock driver 402.

[0042] The memory device 400 also includes a second memory clock driver pair, comprising a third memory clock driver 414 and a fourth memory clock driver 413 disposed between the third and fourth memory cell arrays 416 and 418. Word lines WL_L_BOT[0]-[n] and WL_R_BOT[0]-[n] select rows of their respective arrays 416 and 418. The third memory clock driver 414 and the fourth memory clock driver 413 are coupled to a first and a second end of conductive lines WLCS_L_BOT[0]-[n] and WLCS_R_BOT[0]-[n], and are configured to drive the word lines WL_L_BOT[0]-[n] and WL_R_BOT[0]-[n] to which they are coupled. The third memory clock driver 414 and the fourth memory clock driver 413 are also electrically coupled to a conductive line 425 carrying a master clock signal. Local control circuit 405 controls the operation of third memory clock driver 414 and fourth memory clock driver 413 in a manner similar to its control of first memory clock driver 403 and second memory clock driver 402.

[0043] In this embodiment, global control 424 is the main control block of memory device 400. Global control 424 uses control inputs received from the external world (e.g., chip-level inputs) and generates appropriate internal signals to perform the requested operation. In this embodiment, I / Os 420, 422 are located adjacent to global control circuitry 424 and close to the boundary of memory device 400, such as... Figure 4 As shown. Global I / Os 420 and 422 are coupled to the external world, allowing devices (e.g., processors, chips, etc.) to read from and / or write to memory device 400. Therefore, when reading data from memory device 400, data is read from memory cell arrays 404, 406, 416, and 418 and transferred to one or more of global I / Os 420 and 422, enabling the data to be received by the device. Similarly, when writing data to memory device 400, the device transfers data to one or more of global I / Os 420 and 422, enabling the data to be written to memory cell arrays 404, 406, 416, and 418. In this embodiment, a global I / O block exists for each bit of the memory word length.

[0044] like Figure 4As illustrated in the example, local control circuitry 405 and local I / Os 410, 412 exist in a memory device comprising multiple memory cell arrays 404, 406, 416, 418. Local control circuitry 405 includes circuitry that operates based on signals received from global control circuitry 424 and generates additional signals to perform a requested operation. For example, based on signals received from global control 424, local control circuitry 405 generates signals to activate a specific word line driver coupled to one of arrays 404, 406, 416, 418. Furthermore, in this embodiment, local control circuitry 405 generates signals to be sent to local I / Os 410, 412 based on signals received from global control circuitry 424.

[0045] In memory devices comprising multiple memory cell arrays 404, 406, 416, and 418, such as Figure 4 As shown, local I / Os 410 and 412 are located adjacent to the local control circuit 405. Local I / Os 410 and 412 interface with bit lines from the upper memory cell arrays 404 and 406 and the lower memory cell arrays 416 and 418. Furthermore, local I / Os 410 and 412 operate according to control signals from the local control circuit 405 and perform appropriate operations (e.g., read or write data) on the selected bit lines. Local I / Os 410 and 412 also interface with global I / Os 420 and 422. Specifically, in the embodiment, local I / Os 410 and 412 (i) receive data to be written from global I / Os 420 and 422, and (ii) send data read from memory cell arrays 404, 406, 416, and 418 to global I / Os 420 and 422.

[0046] Figure 5 It describes, according to some embodiments, in the time domain Figure 2 Timing diagram 500 shows signals 501 and 502 at both ends of the WLCS lines of the memory cell array. After receiving and decoding the address, the first and second memory clock drivers activate the WLCS lines corresponding to the address when the master clock signal 503 changes. This is because the clock signal is transmitted to... Figure 2 The signal on the first terminal of WLCS line 501 is driven to a high voltage by the first memory clock driver at time 504 after a short propagation delay, before the second memory clock driver arrives at the first memory clock driver. Figure 2 The clock signal is first received and sent by the first memory clock driver to the second memory clock driver. After a relatively long propagation delay, the second end of the WLCS line is driven to a high voltage at time 505. Therefore, the second end of the WLCS line is driven to a high voltage at time 505, which is delayed by the additional propagation delay 506.

[0047] The implementation of the second memory clock driver results in a voltage signal at the second terminal of the WLCS line, represented by solid line 502. Dashed line 507 represents the voltage signal at the second terminal of the WLCS line if the second memory clock driver is not implemented in the memory device. Figure 5 As shown, the implementation of the second memory clock driver causes the voltage signal at the second terminal of the WLCS line to be driven to its high voltage state much faster than when the second memory clock driver is not used, as indicated by 508. When the second memory clock driver is not used, the slower voltage rise at the second terminal of the WLCS line is caused by timing contamination delays across the WLCS line after it has been driven by the first memory clock driver. The implementation of the second memory clock driver eliminates these timing contamination delays and, in some embodiments, reduces the propagation delay between signal 501 at the first terminal of the WLCS line and the signal at the second terminal of the WLCS line by 5%.

[0048] Similarly, voltage is Figure 5 The time represented as 509 in the diagram decreases more rapidly. Without a second memory clock driver, the voltage drops more slowly than when driven low by the second memory clock driver due to the propagation delay of charge discharged from the second end of the WLCS line through the first memory clock driver.

[0049] Figure 6 This is a circuit diagram depicting a memory cell array 110 of a memory device 600 according to some embodiments, having a first memory clock driver 120 and a second memory clock driver 121 disposed opposite to each other, and circuitry for selecting row 130, wherein the first memory clock driver 120 and the second memory clock driver 121 are directly electrically coupled to a main clock signal line 607. The memory device 600 and... Figure 2 The memory device 200 is the same, except that the clock signal line 607 is directly coupled to both the first memory clock driver 120 and the second memory clock driver 121.

[0050] A first memory clock driver 120 is disposed on a first side of the memory cell array 110. A second memory clock driver 121 is disposed on a second side of the memory cell array 110 opposite to the first memory clock driver 120. Both the first memory clock driver 120 and the second memory clock driver 121 are electrically coupled to a plurality of conductive WLCS lines 206. In some embodiments, the number of WLCS lines in the plurality of WLCS lines 206 corresponds to the number of memory cell rows 111. Each WLCS line in the plurality of WLCS lines 206 is electrically coupled at a first end to the first memory clock driver 120 to receive the output of the first memory clock driver 120, and at a second end to the second memory clock driver 121 to receive the corresponding output of the second memory clock driver 121, such that when the same input value is given to the first memory clock driver 120 and the second memory clock driver 121, the outputs of the first memory clock driver 120 and the second memory clock driver 121 provide the same signal to the WLCS line.

[0051] In some embodiments, a master clock signal 607 is received as an input to both the first memory clock driver 120 and the second memory clock driver 121. Both the first memory clock driver 120 and the second memory clock driver 121 receive an address 209 corresponding to a memory cell row 111 in the memory cell array 110 to be activated. In some embodiments, the address 209 has n / 2 bits, where n is the number of memory cell rows in the memory cell array 110.

[0052] Upon receiving address 209 corresponding to a row of memory cells in memory cell array 110, the first memory clock driver 120 and the second memory clock driver 121 decode address 209 and activate the WLCS line in WLCS line 206 corresponding to address 209 and the row of memory cells in memory cell array 110 to be activated. The activation of the WLCS line in WLCS line 206 occurs at a timed interval with clock signal 607. The activated WLCS line in WLCS line 206 is driven at both ends by the first memory clock driver 120 and the second memory clock driver 121.

[0053] WLCS line 206 is received as input by row selection circuit 130. Row selection circuit 130 also receives row selection address 210, which corresponds to the row of memory cells 111 to be selected in memory cell array 110, as input. In some embodiments, row selection address 210 consists of a thermometer code with n*2 bits, where n is the number of memory cell rows in memory cell array 110. In some embodiments, two bits of address 210 correspond to each memory cell row 111 in memory cell array 110.

[0054] In some embodiments, row selection circuit 130 includes row selection circuit 211 corresponding to each memory cell row 111 in memory cell array 110. In embodiments, row selection circuit 211 includes multiple stages. Row selection circuit 211 includes a first stage 612, which consists of logic AND gates that receive row selection address 210 as input. The output of the first stage 612 is received by a second stage 613, which consists of logic NAND gates and also receives a WLCS line corresponding to the memory cell row 111 of memory cell array 110 corresponding to row selection circuit 211. A third stage 614 of row selection circuit 211 consists of logic NOT gates that receive the output of second stage 613 as input. The output of third stage 614 is electrically coupled to the memory cell row of memory cell array corresponding to row selection circuit 211.

[0055] When two logic high bits of address 210 are received at the first stage 612, the first stage outputs a logic high signal, which is received by the second stage 613 NAND gate. When the second stage 613 receives the logic high signal from the first stage and the high signal on the corresponding WLCS line in WLCS line 206, the second stage 613 outputs a logic low signal. When a logic low signal is received from the second stage 613 at the third stage 614, the third stage 614 outputs a logic high signal, which activates the corresponding memory cell row 111 of the memory cell array 110. Various memory cell types (e.g., static random access memory (SRAM) cells, dynamic random access memory (DRAM) cells, etc.) can be used to implement the memory cell 615 of the memory cell array 110.

[0056] Figure 7 It describes, according to some embodiments, in the time domain Figure 6 Timing diagram 700 shows signals 701 and 702 at both ends of the WLCS lines of the memory cell array. After receiving and decoding the address, the first and second memory clock drivers activate the WLCS lines corresponding to the address when the master clock signal 703 changes. Because the clock signal 703 arrives at both the first and second memory clock drivers simultaneously, the clock signal is eliminated. Figure 5 The propagation delay is described as 506. Signal 701 at the first end of the WLCS line is driven high by the first memory clock driver at time 705, while signal 702 at the second end of the WLCS line is driven high by the second memory clock driver.

[0057] The implementation of a second memory clock driver results in a voltage signal at the second terminal of the WLCS line, represented by solid line 702. Dashed line 707 represents the voltage signal at the second terminal of the WLCS line if the second memory clock driver is not implemented in the memory device. Figure 7 As shown, the implementation of the second memory clock driver causes the voltage signal at the second terminal of the WLCS line to be driven to its high voltage state much faster than when the second memory clock driver is not used, as indicated by 708. When the second memory clock driver is not used, the slower voltage rise at the second terminal of the WLCS line is caused by timing contamination delays across the WLCS line after it has been driven by the first memory clock driver. The implementation of the second memory clock driver eliminates these timing contamination delays and, in some embodiments, reduces the propagation delay between the signal 701 at the first terminal of the WLCS line and the signal at the second terminal of the WLCS line by 5%.

[0058] Similarly, voltage is Figure 7 The time represented as 709 in the diagram drops more rapidly. Without a second memory clock driver, the voltage drops more slowly than when driven low by the second memory clock driver due to the propagation delay of charge discharged from the second end of the WLCS line through the first memory clock driver.

[0059] Figure 8 This describes example circuitry, including an implementation for a memory clock driver, according to some embodiments. Figure 2 The circuit diagram of the memory cell array. The first memory clock driver 120 and the second memory clock driver 121 respectively include decoders 820 and 821. Decoders 820 and 821 accept the address 809 of the memory cell row 111 in the memory cell array 110 to be activated as input, and decode the address to activate the WLCS line 206 corresponding to the memory cell row 111 to be activated.

[0060] Decoder 820 includes two stages of decoding circuitry 822 corresponding to each memory cell row 111. In some embodiments, the two stages of decoding circuitry 822 include a first stage 823 of logic NAND gates that receives two bits of address 809 as input. The first stage 823 outputs a signal as input to a second stage 824 of logic NOR gates. The second stage 824 receives a master clock signal 207 as a second input and has an output electrically coupled to a WLCS line 206 corresponding to memory cell row 111.

[0061] When the first-stage 823 NAND gate receives two high-order bits, it outputs a low-order signal to the second-stage 824 NOR gate, which also receives the clock signal 207. When the second-stage 824 receives the low-order signal from the first stage and the clock signal 207 goes low, the decoding circuit 822 drives the corresponding WLCS line 206 high.

[0062] In some embodiments, the two-stage decoding circuit 821 corresponds to each memory cell row 111. The two-stage decoding circuit 821 includes a first stage 825, which includes a logic NAND gate that receives two bits of address 809 as input. The first stage 825 outputs a signal to the output stage 826 of the memory clock driver 121. The output stage 826 includes a first transistor 827, which has a first terminal electrically coupled to a voltage source 828, a second terminal electrically coupled to the first terminal of the voltage source 828, and a gate voltage electrically coupled to the inverted output of the first stage 825. A second transistor 829 has a second terminal electrically coupled to the WLCS line 206 corresponding to memory cell row 111 and a third transistor 830. The second transistor 829 also has a gate electrically coupled to the inverted clock signal 207. The third transistor 830 has a second terminal electrically coupled to ground 831 and a gate terminal electrically coupled to the clock signal 207. The two-stage decoding circuit 821 is logically equivalent to the two-stage decoding circuit 822.

[0063] Figure 9 This is a circuit diagram 900 depicting a memory cell array 110 including example circuitry for a memory clock driver implementation according to some embodiments. In some embodiments, decoder circuitry 922 includes NOR gates 923. Each NOR gate 923 corresponds to one or more memory cell rows 111 and is electrically coupled to a WLCS line 906 corresponding to one or more memory cell rows 111. Each NOR gate 923 receives a single bit of an address 909 corresponding to a memory cell row 111 of the memory cell array 110 and a master clock signal 207 as input. When a single bit of address 909 is logic low and clock signal 207 goes low, NOR gate 923 drives the WLCS line high.

[0064] In some embodiments, the decoding circuit 921 corresponds to one or more memory cell rows 111. The decoding circuit 921 includes a first transistor 927 having a first terminal electrically coupled to a voltage source 928, a second terminal electrically coupled to a first terminal of a second transistor 929, and a gate voltage electrically coupled to a bit of address 909. The second transistor 929 has a second terminal electrically coupled to a WLCS line 906 corresponding to memory cell row 111 and a first terminal of a third transistor 930. The second transistor 929 also has a gate electrically coupled to an inverted clock signal 207. The third transistor 930 has a second terminal electrically coupled to electrical ground 931 and a gate terminal electrically coupled to the clock signal 207. The decoding circuit 921 is logically equivalent to the decoding circuit 922.

[0065] Figure 10 This is a flowchart 1000 depicting the steps of an example method of operating a word line driver according to some embodiments. While various structures can be used to perform the steps of the method, references to some example structures are provided herein for clarity. At 1002, the method uses a first memory clock driver 120 to decode address 209 of memory cell row 111. At 1004, the first memory clock driver 120 and a second memory clock driver 121 activate the memory cell row 111 corresponding to address 209, wherein the second memory clock driver 121 and the first memory clock driver 120 are positioned on opposite sides of a plurality of memory cells 215 in the plurality of rows 111.

[0066] In one example, the memory device includes a plurality of memory cells in a plurality of rows, a first memory clock driver disposed on a first side of the plurality of rows, and a second memory clock driver disposed on a second side of the plurality of rows opposite to the first side. The first and second memory clock drivers are configured to transmit word line clock signals in response to a master clock signal to activate rows of memory cells in the plurality of rows using the first and second memory clock drivers.

[0067] In some embodiments, the first memory clock driver includes a first decoder; the second memory clock driver includes a second decoder.

[0068] In some embodiments, the first memory clock driver is configured to receive the master clock signal and transmit the master clock signal to the second memory clock driver.

[0069] In some embodiments, both the first memory clock driver and the second memory clock driver are configured to receive the master clock signal simultaneously.

[0070] In some embodiments, a first memory clock driver and a second memory clock driver are configured to receive addresses corresponding to memory cell rows in a plurality of rows, the addresses being decoded by a first decoder and a second decoder corresponding to memory cell rows in a plurality of rows, wherein the first memory clock driver and the second memory clock driver are configured to transmit word line clock signals in response to a master clock signal to activate memory cell rows in a plurality of rows corresponding to addresses via conductive lines coupled between the first memory clock driver and the second memory clock driver.

[0071] In some embodiments, the memory device further includes a row selection circuit configured to accept a row selection address and select a corresponding memory cell row from a plurality of rows.

[0072] In some embodiments, the memory device further includes a row selection circuit configured to accept a row selection address and select a corresponding memory cell row from a plurality of rows. The row selection circuit has circuitry corresponding to each memory cell row from the plurality of rows, the circuitry including: an AND gate configured to accept two bits of the row selection address as input; a NAND gate electrically coupled to the output of the AND gate as a first input and electrically coupled to a word line clock signal transmitted via a conductive line coupled between a first memory clock driver and a second memory clock driver as a second input; and a NOT gate electrically coupled to the output of the NAND gate as input and electrically coupled to the memory cell row from the plurality of rows as an output.

[0073] In some embodiments, each of the first decoder and the second decoder includes circuitry corresponding to each memory cell row in a plurality of rows. The circuitry includes: a NAND gate configured to receive two bits of an address as input; and a NOR gate electrically coupled to the output of the NAND gate as a first input and electrically coupled to a master clock signal as a second input, wherein the output of the NOR gate is a word line clock signal to activate the memory cell row in the plurality of rows.

[0074] In some embodiments, the logic NOR gate includes: a first transistor having a first terminal electrically coupled to a voltage source and a gate terminal electrically coupled to the output of the logic NAND gate; a second transistor having a first terminal electrically coupled to a second terminal of the first transistor and a gate terminal electrically coupled to a master clock signal; and a third transistor having a second terminal electrically coupled to the second transistor and a first terminal of a conductive line carrying a word line clock signal as the output of the decoder, a gate terminal electrically coupled to the master clock signal, and a second terminal electrically coupled to ground.

[0075] In some embodiments, each of the first decoder and the second decoder includes circuitry corresponding to each memory cell row in a plurality of rows. The circuitry includes a logic NOR gate electrically coupled to a master clock signal as a first input and electrically coupled to bits of an address as a second input, wherein the output of the logic NOR gate is a word line clock signal to activate the memory cell row in the plurality of rows.

[0076] In some embodiments, the memory device further includes local I / O configured to transmit a master clock signal to one or more of a first memory clock driver and a second memory clock driver.

[0077] In some embodiments, the memory device further includes a clock signal generator electrically coupled to one or more of a first memory clock driver and a second memory clock driver, wherein the clock signal generator transmits a master clock signal to one or more of the first memory clock driver and the second memory clock driver.

[0078] In another example, a method of operating a memory device includes: decoding an address of a row of memory cells using a first memory clock driver at the first memory clock driver; activating the row of memory cells corresponding to the address via a first memory clock driver and a second memory clock driver, the second memory clock driver being positioned on the side of a plurality of memory cells in a plurality of rows opposite to the first memory clock driver.

[0079] In some embodiments, the method further includes a first memory clock driver transmitting a master clock signal to a second memory clock driver.

[0080] In some embodiments, the master clock signal is received simultaneously by a first memory clock driver and a second memory clock driver.

[0081] In some embodiments, the method further includes receiving a row selection address at a row selection circuit, wherein the row selection circuit selects a memory cell row corresponding to the row selection address.

[0082] In some embodiments, the first memory clock driver transmits the decoded address corresponding to the memory cell row to the second memory clock driver, and the second memory clock driver activates the memory cell row corresponding to the decoded address.

[0083] In some embodiments, the method further includes a second memory clock driver: receiving an address corresponding to a memory cell row; decoding the address corresponding to the memory cell row; and activating the memory cell row corresponding to the address.

[0084] In another embodiment, a memory clock driver circuit coupled to a memory cell array includes a first memory clock driver disposed on a first side of a plurality of rows of memory cells. A second memory clock driver is disposed on a second side opposite to the first side of the plurality of rows. The first and second memory clock drivers are configured to transmit word line clock signals in response to a master clock signal to activate rows of memory cells in the plurality of rows via conductive lines coupled between the first and second memory clock drivers.

[0085] In some embodiments, a first memory clock driver and a second memory clock driver are configured to receive addresses corresponding to rows of memory cells in a plurality of rows, the addresses being decoded by the first memory clock driver and the second memory clock driver to correspond to rows of memory cells in the plurality of rows, wherein the first memory clock driver and the second memory clock driver are configured to transmit word line clock signals in response to a master clock signal to activate rows of memory cells in the plurality of rows corresponding to the addresses via conductive lines coupled between the first memory clock driver and the second memory clock driver.

[0086] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. A memory device comprising: a plurality of memory cells in a plurality of rows; a first memory clock driver disposed on a first side of the plurality of rows, and a second memory clock driver disposed on a second side of the plurality of rows opposite the first side, wherein the first memory clock driver and the second memory clock driver are configured to transmit a word line clock signal in response to a master clock signal to activate a row of memory cells in the plurality of rows using the first memory clock driver and the second memory clock driver, and a row selection circuit configured to select the row of memory cells in the plurality of rows using an address of the row of memory cells, wherein the row selection circuit comprises: a first logic gate configured to receive the address: a second logic gate coupled to an output of the first logic gate and configured to receive the word line clock signal; a third logic gate connected between an output of the second logic gate and the row of memory cells; wherein the first memory clock driver and the second memory clock driver are configured to transmit a word line clock signal in response to a master clock signal to activate a row of memory cells in the plurality of rows using the first memory clock driver and the second memory clock driver.

2. The memory device of claim 1, wherein: the first memory clock driver comprises a first decoder; and the second memory clock driver comprises a second decoder.

3. The memory device of claim 1, wherein, the first memory clock driver is configured to receive the master clock signal and transmit the master clock signal to the second memory clock driver.

4. The memory device of claim 1, wherein, the first memory clock driver and the second memory clock driver are each configured to receive the master clock signal simultaneously.

5. The memory device of claim 2, wherein: the first memory clock driver and the second memory clock driver are configured to receive an address corresponding to the row of memory cells in the plurality of rows, the address decoded by the first decoder and the second decoder corresponds to the row of memory cells in the plurality of rows, wherein the first memory clock driver and the second memory clock driver are configured to transmit the word line clock signal in response to the master clock signal to activate the row of memory cells in the plurality of rows corresponding to the address through a conductive line coupled between the first memory clock driver and the second memory clock driver.

6. The memory device of claim 1, wherein: the first memory clock driver comprises different components than the second memory clock driver such that the second memory clock driver is capable of receiving the master clock signal through the first memory clock driver.

7. The memory device of claim 5, wherein: the first logic gate is a logical AND gate; the second logic gate is a logical NAND gate; the third logic gate is a logical NOT gate.

8. The memory device of claim 5, wherein, Each of the first decoder and the second decoder includes circuitry corresponding to each memory cell row of the plurality of rows, the circuitry including: a logic NAND gate configured to receive two bits of an address as inputs; and a logic NOR gate electrically coupled to an output of the logic NAND gate as a first input and to a main clock signal as a second input, wherein an output of the logic NOR gate is the word line clock signal to activate the memory cell row of the plurality of rows.

9. The memory device of claim 8, wherein, The logic NOR gate includes: a first transistor having a first terminal electrically coupled to a voltage source and a gate terminal electrically coupled to the output of the logic NAND gate; a second transistor having a first terminal electrically coupled to a second terminal of the first transistor and a gate terminal electrically coupled to the main clock signal; and a third transistor having a first terminal electrically coupled to a second terminal of the second transistor and the conductive line carrying the word line clock signal as an output of a decoder, a gate terminal electrically coupled to the main clock signal, and a second terminal electrically coupled to electrical ground.

10. The memory device of claim 2, wherein, Each of the first decoder and the second decoder includes circuitry corresponding to each memory cell row of the plurality of rows, the circuitry including a logic NOR gate electrically coupled to the main clock signal as a first input and to a bit of the address as a second input, wherein an output of the logic NOR gate is the word line clock signal to activate the memory cell row of the plurality of rows.

11. The memory device of claim 1, further comprising a local I / O configured to transmit the main clock signal to one or more of the first memory clock driver and the second memory clock driver.

12. The memory device of claim 1, further comprising a clock signal generator electrically coupled to one or more of the first memory clock driver and the second memory clock driver, wherein, The clock signal generator transmits the main clock signal to the one or more of the first memory clock driver and the second memory clock driver.

13. A method of operating a memory device, comprising the steps of: decoding an address of a memory cell row at a first memory clock driver; activating, by the first memory clock driver and a second memory clock driver, the memory cell row corresponding to the address, the second memory clock driver positioned on an opposite side of the memory cell row from the first memory clock driver, wherein at least one of the first memory clock driver and the second memory clock driver includes a logic gate configured to receive the address and a main clock signal and produce a word line clock signal to activate the memory cell row.

14. The method of claim 13, further comprising the first memory clock driver transmitting the main clock signal to the second memory clock driver.

15. The method of claim 14, wherein, The main clock signal is received by the first memory clock driver and the second memory clock driver simultaneously.

16. The method of claim 13, further comprising receiving a row select address at a row select circuit, wherein, The row select circuitry selects a memory cell row corresponding to the row select address.

17. The method of claim 13, wherein, The first memory clock driver transmits a decoded address corresponding to the memory cell row to the second memory clock driver, the second memory clock driver activates the memory cell row corresponding to the decoded address.

18. The method of claim 13, further comprising the second memory clock driver: receiving the address corresponding to a memory cell row; decoding the address corresponding to the memory cell row; activating the memory cell row corresponding to the address.

19. A memory clock driver circuit coupled to an array of memory cells, the memory clock driver circuit comprising: a first memory clock driver disposed on a first side of a plurality of rows of memory cells and a second memory clock driver disposed on a second side opposite the first side of the plurality of rows, wherein the first memory clock driver and the second memory clock driver are configured to transmit a word line clock signal in response to a master clock signal to activate a memory cell row of the plurality of rows through a conductive line coupled between the first memory clock driver and the second memory clock driver, wherein the first memory clock driver comprises different components than the second memory clock driver such that the second memory clock driver is capable of receiving the master clock signal through the first memory clock driver.

20. The memory clock driver circuit of claim 19, wherein: the first memory clock driver and the second memory clock driver are configured to receive an address corresponding to a memory cell row of the plurality of rows, the address is decoded by the first memory clock driver and the second memory clock driver to correspond to the memory cell row of the plurality of rows, wherein the first memory clock driver and the second memory clock driver are configured to transmit a word line clock signal in response to the master clock signal to activate the memory cell row of the plurality of rows corresponding to the address through the conductive line coupled between the first memory clock driver and the second memory clock driver.

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