An in-memory computing circuit

Abstract

The present invention relates to a in-memory computing circuit. The sign bit of the input data is input to the first input terminal of the XNOR gate in the circuit. The second terminal of the XNOR gate is connected to the Q of the last SRAM cell in the memory array, and the sign bit of the weight is input to the second terminal of the XNOR gate. The output terminal of the XNOR gate is connected to the gate of transistor PM1. The sources of transistor PM1 and transistor PM2 are connected to one end of capacitor C1. The drains of transistor PM1 and transistor PM2 are connected to the output terminal of transmission gate T1. The other end of capacitor C1 is connected to VDD. The gate of transistor PM2 is connected to the gate of transistor PM3. The sources of transistor PM3 and transistor PM4 are connected to one end of capacitor C2. The other end of capacitor C2 is connected to VDD. The drains of transistor PM3 and transistor PM4 are connected to the output terminal of transmission gate T1. The input terminal of transmission gate T1 is connected to the complementary bit line. The gate of transistor PM4 inputs the opposite of the output result of the XNOR gate. The present invention can improve the concurrency and computing speed of array computing.

Description

Technical Field

[0001] The present invention relates to the field of in - memory computing, and particularly to an in - memory computing circuit. Background Art

[0002] The accuracy of convolutional neural networks (CNNs) in large - scale recognition tasks has been improved unprecedentedly. However, algorithm complexity and memory access limit the energy efficiency and acceleration speed of CNNs hardware. Therefore, it is considered to perform part of the calculations in the storage array, but how to perform calculations in the storage array is an urgent problem to be solved. Summary of the Invention

[0003] The object of the present invention is to provide an in - memory computing circuit, which can improve the concurrency and computing speed of array computing.

[0004] To achieve the above object, the present invention provides the following solutions:

[0005] An in - memory computing circuit includes: 1 column of storage arrays, an exclusive - NOR gate, transistor PM1, transistor PM2, transistor PM3, transistor PM4, transmission gate T1, capacitor C1, and capacitor C2; the storage array includes multiple SRAM cells connected in parallel between bit line BL and complementary bit line BLB.

[0006] The first input terminal of the exclusive - NOR gate is used to input the sign bit of the input data, the second terminal of the exclusive - NOR gate is connected to the weight storage point Q of the last SRAM cell in the storage array, and the second terminal of the exclusive - NOR gate is used to input the sign bit of the weight; the output terminal of the exclusive - NOR gate is connected to the gate of transistor PM1, the source of transistor PM1 and the source of transistor PM2 are both connected to one end of capacitor C1, the drain of transistor PM1 and the drain of transistor PM2 are both connected to the output terminal of transmission gate T1, the other end of capacitor C1 is connected to power supply VDD, the gate of transistor PM2 is connected to the gate of transistor PM3, the source of transistor PM3 and the source of transistor PM4 are both connected to one end of capacitor C2, the other end of capacitor C2 is connected to power supply VDD, the drain of transistor PM3 and the drain of transistor PM4 are both connected to the output terminal of transmission gate T1, the input terminal of transmission gate T1 is connected to complementary bit line BLB, and the control terminal of the transmission gate is used to input a transmission gate control signal; the gate of transistor PM4 inputs the opposite of the output result of the exclusive - NOR gate.

[0007] Optionally, the input terminal of each SRAM cell is connected to word line WL.

[0008] Optionally, the SRAM cell is a 6T SRAM cell.

[0009] Optionally, when entering the calculation stage, the transmission gate T1 is opened by using a transmission gate control signal, and the capacitors C1 and C2 are pre-charged to the power supply voltage and the pre-charging is stopped;

[0010] The XNOR gate determines the output result according to the sign bit of the input data and the sign bit of the weight stored in the weight storage point Q of the last SRAM cell in the storage array;

[0011] The capacitors C1 and C2 are discharged accordingly according to the output sign of the output result.

[0012] According to the specific embodiments provided by the present invention, the following technical effects are disclosed:

[0013] A memory-in-computation circuit provided by the present invention includes: 1 column of storage arrays, an XNOR gate, transistors PM1, PM2, PM3, PM4, a transmission gate T1, a capacitor C1, and a capacitor C2. It is determined whether the capacitor C1 or the capacitor C2 is discharged according to the output sign of the output result of the XNOR gate, and then the product is reflected on the positive result capacitor. The present invention realizes multi-bit memory-in-computation that can distinguish positive and negative, and can simultaneously open the entire array to calculate multiple groups of data, and each array does not affect each other and can be combined into multiple blocks, having high concurrency. Description of the Drawings

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0015] Figure 1 It is a schematic structural diagram of a memory-in-computation circuit provided by the present invention. Detailed Embodiments

[0016] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0017] The purpose of the present invention is to provide a memory-in-computation circuit that can improve the concurrency and calculation speed of array calculations.

[0018] To make the above objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] Figure 1 A schematic diagram of an in-memory computing circuit structure provided by the present invention is shown as Figure 1 shown. An in-memory computing circuit provided by the present invention includes: 1 column of memory arrays, an exclusive-NOR gate, transistor PM1, transistor PM2, transistor PM3, transistor PM4, transmission gate T1, capacitor C1, and capacitor C2; the memory array includes multiple SRAM cells connected in parallel between bit line BL and complementary bit line BLB.

[0020] The first input terminal of the exclusive-NOR gate is used to input the sign bit of the input data, the second terminal of the exclusive-NOR gate is connected to the weight storage point Q of the last SRAM cell in the memory array, and the second terminal of the exclusive-NOR gate is used to input the sign bit of the weight; the output terminal of the exclusive-NOR gate is connected to the gate of transistor PM1, the source of transistor PM1 and the source of transistor PM2 are both connected to one end of capacitor C1, the drain of transistor PM1 and the drain of transistor PM2 are both connected to the output terminal of transmission gate T1, the other end of capacitor C1 is connected to power supply VDD, the gate of transistor PM2 is connected to the gate of transistor PM3, the source of transistor PM3 and the source of transistor PM4 are both connected to one end of capacitor C2, the other end of capacitor C2 is connected to power supply VDD, the drain of transistor PM3 and the drain of transistor PM4 are both connected to the output terminal of transmission gate T1, the input terminal of transmission gate T1 is connected to complementary bit line BLB, and the control terminal of the transmission gate is used to input a transmission gate control signal; the gate of transistor PM4 inputs the opposite of the output result of the exclusive-NOR gate.

[0021] When entering the calculation stage, the transmission gate T1 is opened by using the transmission gate control signal, capacitors C1 and C2 are precharged to the power supply voltage, and the precharging is stopped.

[0022] The exclusive-NOR gate determines the output result according to the sign bit of the input data and the sign bit of the weight stored in the weight storage point Q of the last SRAM cell in the memory array.

[0023] Capacitors C1 and C2 are discharged accordingly according to the output sign of the output result.

[0024] As a specific embodiment, the input data is pulse-width modulated, and the modulated data is input into the SRAM cell through the corresponding word line WL, as Figure 1As shown, the inputs are input word line WL[0], input word line WL[1], input word line WL[2], and input word line WL[n].

[0025] The sign of the input signal is exclusive-NOR operated with the sign bit of the weight stored in the weight storage point Q of the last SRAM cell in the storage array. When the exclusive-NOR result is 1 (the signs are the same, either both positive or both negative, and the product result is positive), at this time, the output sign sign of the output result is 1, and the opposite of sign, sign', is 0. Then, the PMOS transistor corresponding to sign' is turned on to discharge the corresponding capacitor, that is, the product is reflected on the positive result capacitor. If the signs of the two are different (one positive and one negative), the product result is negative.

[0026] As a specific embodiment, the SRAM cell is a 6T SRAM cell.

[0027] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other.

[0028] Specific examples are used in this article to elaborate on the principles and implementation manners of the present invention. The descriptions of the above embodiments are only used to help understand the method of the present invention and its core idea. At the same time, for those of ordinary skill in the art, based on the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. An in-memory computing circuit, characterized in that, Including: 1 column storage array, exclusive-NOR gate, transistor PM1, transistor PM2, transistor PM3, transistor PM4, transmission gate T1, capacitor C1, and capacitor C2; the storage array includes multiple SRAM cells connected in parallel between bit line BL and complementary bit line BLB. The first input terminal of the exclusive-NOR gate is used to input the sign bit of the input data, the second terminal of the exclusive-NOR gate is connected to the weight storage point Q of the last SRAM cell in the storage array, and the second terminal of the exclusive-NOR gate is used to input the sign bit of the weight; the output terminal of the exclusive-NOR gate is connected to the gate of transistor PM1, the source of transistor PM1 and the source of transistor PM2 are both connected to one end of capacitor C1, the drain of transistor PM1 and the drain of transistor PM2 are both connected to the output terminal of transmission gate T1, the other end of capacitor C1 is connected to power supply VDD, the gate of transistor PM2 is connected to the gate of transistor PM3, the source of transistor PM3 and the source of transistor PM4 are both connected to one end of capacitor C2, the other end of capacitor C2 is connected to power supply VDD, the drain of transistor PM3 and the drain of transistor PM4 are both connected to the output terminal of transmission gate T1, the input terminal of transmission gate T1 is connected to complementary bit line BLB, and the control terminal of the transmission gate is used to input a transmission gate control signal; the gate of transistor PM4 inputs the opposite of the output result of the exclusive-NOR gate.

2. The in-memory computing circuit according to claim 1, wherein The input terminal of each SRAM cell is connected to word line WL.

3. The in-memory computing circuit according to claim 1, wherein The SRAM cell is a 6T SRAM cell.

4. The in-memory computing circuit according to claim 1, wherein When entering the calculation stage, the transmission gate T1 is opened by using the transmission gate control signal, capacitors C1 and C2 are precharged to the power supply voltage, and the precharging is stopped. The exclusive-NOR gate determines the output result according to the sign bit of the input data and the sign bit of the weight stored in the weight storage point Q of the last SRAM cell in the storage array. Capacitors C1 and C2 are discharged accordingly according to the output sign of the output result.

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