Memory controller and operating method thereof, storage system and electronic device

Abstract

The present disclosure provides a memory controller and an operating method thereof, a storage system and an electronic device. The memory controller is configured to: determine whether to perform read disturb processing on a first memory block according to a read frequency of the first memory block; the read disturb processing comprises reading a first physical page of the first memory block using a single-state read voltage, and determining whether to perform data migration on the first physical page according to a number of empty-state storage units of the first physical page; and sequentially processing other physical pages to complete the read disturb processing on the first memory block.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of memory devices, and in particular, to a memory controller and an operating method thereof, a storage system, and an electronic device. BACKGROUND

[0002] Semiconductor memories can include volatile memories and non-volatile memories. Non-volatile memories can include flash memories, electrically erasable and programmable read-only memories (EEPROMs), ferroelectric memories (FRAMs), and the like. Flash memories are a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memories can include NOR flash memories and NAND flash memories. Various operations, such as reading, programming (writing), and erasing, can be performed by flash memories.

[0003] As the feature size of a memory cell approaches the lower limit of a process, planar processes and manufacturing techniques become challenging and costly, which causes the storage density of 2D or planar NAND flash memories to approach an upper limit. To overcome the limitations of 2D or planar NAND flash memories, the industry has developed three-dimensional memories (3D NAND) having a three-dimensional structure to improve the storage density by arranging memory cells three-dimensionally above a substrate.

[0004] As the market demand for storage density continues to increase, the industry is developing programming methods with more programming states so that each physical memory cell can represent more bit information. However, the implementation of more programming states has higher requirements for the formation process of a single memory cell and the uniformity of distribution between multiple memory cells. Therefore, how to increase the storage density of a memory cell and improve the performance of a three-dimensional memory is a technical problem that needs to be solved at present. SUMMARY

[0005] The present disclosure provides a memory controller and an operating method thereof, a storage system, and an electronic device, which can effectively improve the read disturbance of a memory.

[0006] To solve the above technical problems, the present disclosure provides an operating method of a memory controller,

[0007] performing read disturbance processing on a first physical page of a first memory block, the read disturbance processing including the following steps:

[0008] performing read disturbance scanning on the first physical page of the first memory block to obtain a number N1 of memory cells in an erased state in the first physical page;

[0009] If N1 is less than a storage unit quantity threshold, data of the first physical page is moved to a second storage block.

[0010] In an embodiment of the present disclosure, the read disturb scan is to apply a single state read voltage V SLR to the physical page, and perform a read operation.

[0011] In an embodiment of the present disclosure, the single state read voltage V SLR is lower than a default read voltage V RL1 of an erased state.

[0012] In an embodiment of the present disclosure, if not subjected to read disturb, a difference between a maximum value of a storage block erased state threshold voltage and the default read voltage V RL1 of the erased state is E0, then V RL1 -E0≤V SLR <V RL1 .

[0013] In an embodiment of the present disclosure, V RL1 -1 / 2E0≤V SLR <V RL1 .

[0014] In an embodiment of the present disclosure, the operation method of the memory controller further comprises:

[0015] After the read disturb processing on the first physical page, read disturb processing is performed on other physical pages of the first storage block.

[0016] In an embodiment of the present disclosure, the read disturb processing on the other physical pages of the first storage block is performed sequentially.

[0017] In an embodiment of the present disclosure, before the read disturb processing on the first storage block, further comprising:

[0018] Obtaining a read frequency of the first storage block;

[0019] Comparing the read frequency of the first storage block with a read frequency threshold;

[0020] If the read frequency of the first storage block is greater than the read frequency threshold, performing read disturb processing on the first storage block.

[0021] In an embodiment of the present disclosure, before the read disturb processing on the first storage block, further comprising:

[0022] After the read disturb processing on the first storage block is completed, resetting the read frequency of the first storage block;

[0023] When the read times of the first memory block is greater than the read times threshold, the read disturb processing is performed on the first memory block again.

[0024] In an embodiment of the present disclosure, the operation method of the memory controller further comprises:

[0025] If N1 is greater than the memory cell quantity threshold, the minimum N1 is recorded as Nmin, and the physical address of Nmin is recorded; when the read disturb processing is performed on the first memory block again, the physical page corresponding to Nmin is preferentially scanned or scanned only.

[0026] In an embodiment of the present disclosure, the read disturb processing operation specifically comprises:

[0027] The single-state read voltage V SLR is set.

[0028] The single-state read voltage V SLR is applied to the first physical page once, and a read operation is performed.

[0029] The quantity N1 of memory cells in an erased state in the first physical page is recorded.

[0030] N1 is compared with the memory cell quantity threshold.

[0031] If N1 is less than the memory cell quantity threshold, the data of the first physical page is moved to a second memory block.

[0032] If N1 is greater than the memory cell quantity threshold, N1 is recorded as the minimum memory cell quantity Nmin, and the address of the first physical page is recorded.

[0033] In an embodiment of the present disclosure, the operation method of the memory controller further comprises:

[0034] After the read disturb processing is performed on the first physical page, read disturb processing is performed on a second physical page, comprising the following steps:

[0035] The single-state read voltage V SLR is applied to the second physical page once, and a read operation is performed.

[0036] The quantity N2 of memory cells in an erased state in the second physical page is recorded.

[0037] N2 is compared with the memory cell quantity threshold.

[0038] If N2 is less than the memory cell quantity threshold, the data of the second physical page is moved to a second memory block.

[0039] If N2 is greater than the memory cell quantity threshold,

[0040] N2 is compared with Nmin,

[0041] If N2 is less than Nmin, N2 is taken as Nmin, and the address of the second physical page is recorded.

[0042] After the read disturb processing of the second physical page, other physical pages of the first memory block are processed by the read disturb processing, and the steps are consistent with the read disturb processing of the second physical page, and specifically as follows,

[0043] The Xth physical page (X is a natural number greater than 2) is applied with a single-state read voltage V SLR , and a read operation is performed;

[0044] The number Nx of storage cells in the Xth physical page in an erased state is recorded;

[0045] Nx is compared with a storage cell number threshold;

[0046] If Nx is less than the storage cell number threshold, the data of the Xth physical page is moved to the second memory block;

[0047] If Nx is greater than the storage cell number threshold,

[0048] Nx is compared with Nmin,

[0049] If Nx is less than Nmin, Nx is taken as Nmin, and the address of the Xth physical page is recorded.

[0050] In an embodiment of the present disclosure, the operation method of the memory controller,

[0051] After the read disturb processing operation of the first memory block, the read times of the first memory block are zeroed;

[0052] When the read times of the first memory block are greater than the read times threshold again, the read disturb processing of the first memory block is performed again.

[0053] In an embodiment of the present disclosure, the operation method of the memory controller, the physical page of Nmin recorded by the previous read disturb processing is preferentially scanned.

[0054] In an embodiment of the present disclosure, the operation method of the memory controller, only the physical page of Nmin recorded by the previous read disturb processing is scanned.

[0055] Another aspect of the present disclosure provides a memory controller, which is configured to:

[0056] Obtain the read count data of the storage block and the read interference scan data of the physical page, as well as the physical page address data; calculate the relationship between the read count data of the storage block and the read count threshold, and the relationship between the read interference scan data of the physical page and the storage cell number threshold; based on the calculation results, determine whether to perform read interference processing and data movement, and control data movement.

[0057] In one embodiment of this disclosure, the memory controller, the read interference scan data, is a single-state read voltage V applied to the physical pages in the memory block. SLR Obtained by performing a read operation.

[0058] In one embodiment of this disclosure, the memory controller, the read interference scan data, includes applying a single-state read voltage V. SLR The number of memory cells in the erased state in the subsequent physical page.

[0059] In one embodiment of this disclosure, the memory controller,

[0060] Let the maximum value of the initial erase state threshold voltage of the memory block be equal to the default read voltage V in the erase state. RL1 If the difference is E0, then the single-state read voltage V SLR The numerical range of V is RL1 -E0≤V SLR <V RL1 .

[0061] In one embodiment of this disclosure, the memory controller is configured to reset the read count of the first memory block to zero after performing a read interference processing operation on the first memory block.

[0062] In one embodiment of this disclosure, the memory controller is configured to instruct the physical page address data to be stored at a designated location on the storage device.

[0063] In another aspect, this disclosure provides a storage system including a storage device and the aforementioned memory controller or a memory controller capable of performing the control method.

[0064] In another aspect, this disclosure provides an electronic device including the aforementioned storage system.

[0065] Because of the adoption of the above technical solution, this disclosure has the following significant advantages compared with the prior art:

[0066] The control method of the three-dimensional memory of the present invention,

[0067] First, the present disclosure uses a single-state read voltage to read a physical page, and the number of storage cells in an erased state accurately represents the physical effect of read disturbance, eliminating the interference of other factors such as data retention, cross temperature, and other reliability issues.

[0068] Second, when the storage block is a TLC, QLC, PLC or more state storage block, a single-state read is a first physical page read of the first storage block once, obtaining the read disturbance degree of the first physical page; compared with reading each storage state of the first physical page to obtain the read disturbance degree of the first physical page, it is faster and more efficient.

[0069] Third, the read disturbance processing of the present disclosure uses the number of storage cells in an erased state to represent the physical effect of read disturbance, and does not need to go through low-density parity check (LDPC), directly counts the number of storage cells in an erased state, which is accurate and more efficient.

[0070] Fourth, the read disturbance scanning of the present disclosure is carried out in physical page units, and through read disturbance scanning, the physical position with real reliability risk can be accurately located, and data relocation is carried out on the storage page with larger read disturbance degree, without the need for data relocation of the entire storage block, reducing the low processing efficiency and wear caused by a large amount of data relocation.

[0071] Fifth, the present disclosure records the physical page with the largest read disturbance scanning in the physical page that did not undergo data relocation in the previous read disturbance processing process (i.e. the physical page corresponding to Nmin), so in the case of needing to quickly process read disturbance, the physical position with the largest read disturbance degree in the previous process can be scanned first, or in special cases, only the physical position with the largest read disturbance degree in the previous process is scanned, saving read disturbance processing time and improving processing efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0072] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description are only some of the drawings of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0073] Figure 1 A schematic diagram of an exemplary memory device according to some aspects of the present disclosure is shown.

[0074] Figure 2 A side view showing a cross-section of an exemplary memory cell array including NAND memory strings is shown in accordance with some aspects of the present disclosure.

[0075] Figure 3 A block diagram of an exemplary memory device is shown in accordance with some aspects of the present disclosure.

[0076] Figure 4 is a three-dimensional memory read disturb schematic diagram in accordance with exemplary embodiments of the present disclosure;

[0077] Figure 5 is a three-dimensional memory read reference voltage and pass voltage schematic diagram in accordance with exemplary embodiments of the present disclosure;

[0078] Figure 6 is a three-dimensional memory read disturb scan voltage schematic diagram in accordance with exemplary embodiments of the present disclosure;

[0079] Figure 7 is a three-dimensional memory read disturb scan flow schematic diagram in accordance with exemplary embodiments of the present disclosure;

[0080] Figure 8 is a three-dimensional memory read disturb scan first physical page of a first memory block flow schematic diagram in accordance with exemplary embodiments of the present disclosure;

[0081] Figure 9 is a three-dimensional memory read disturb scan other physical pages of a first memory block flow schematic diagram in accordance with exemplary embodiments of the present disclosure;

[0082] Figure 10 A block diagram of an exemplary system having a memory device is shown in accordance with some aspects of the present disclosure.

[0083] Figure 11A A diagram of an exemplary memory card having a memory device is shown in accordance with some aspects of the present disclosure.

[0084] Figure 11B A diagram of an exemplary solid state drive (SSD) having a memory device is shown in accordance with some aspects of the present disclosure. DETAILED DESCRIPTION

[0085] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. It should be apparent that the described embodiments are only a part of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0086] In the description of the disclosure, it needs to be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, which are only for the convenience of describing the disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the disclosure.

[0087] Unless the context clearly requires otherwise, throughout the description and the claims, the term "comprise", "comprising", and the like, are to be construed in an open, inclusive and a non-exclusive sense, that is as "comprising, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "exemplary embodiments", or "some examples" and the like are intended to mean that a particular feature, structure, material, or characteristic included in at least one embodiment or example of the disclosure. The illustrative representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any appropriate manner in any one or more embodiments or examples.

[0088] Hereinafter, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the embodiments of the disclosure, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0089] In describing some embodiments, "coupled" and "connected", and their derivatives, can be used. For example, the term "connected" can be used to describe some embodiments to indicate that two or more components have direct physical or electrical contact with each other. For another example, the term "coupled" can be used to describe some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" can also mean that two or more components have no direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited by the content herein.

[0090] "A, B and C at least one of them" has the same meaning as "at least one of A, B or C", which includes the following combinations of A, B and C: only A, only B, only C, combination of A and B, combination of A and C, combination of B and C, and combination of A, B and C.

[0091] "A and / or B" includes the following three combinations: only A, only B, and combination of A and B.

[0092] The use of “adapted to” or “configured to” herein means open and inclusive language that does not exclude devices that are adapted to or configured to perform additional tasks or steps.

[0093] Additionally, the use of “based on” means open and inclusive, as a process, step, calculation, or other action that is “based on” one or more recited conditions or values can in practice be based on additional conditions or values beyond those recited.

[0094] As used herein, “about,” “approximately,” or “around” includes the recited value and average values falling within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0095] In the present disclosure, the meaning of “on,” “over,” and “above” should be interpreted in the broadest context, such that “on” means not only “directly on” but also includes the meaning of “on” with intervening features or layers therebetween, and “over” or “above” means not only “over” or “above” but also includes the meaning of “over” or “above” with no intervening features or layers therebetween (i.e., directly on).

[0096] Figure 1 A schematic circuit diagram of an exemplary memory device 300 is shown in accordance with some aspects of the present disclosure. The memory device 300 can be an example of the memory device 104 in Figure 1 The memory device 300 can include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 can be a NAND flash memory cell array in which memory cells 306 are disposed in the form of an array of NAND memory strings 308, with each NAND memory string 308 extending vertically above a substrate (not shown). In some implementations, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, e.g., a voltage or charge, that depends on the number of electrons trapped within a region of the memory cell 306. Each memory cell 306 can be a floating gate type of memory cell that includes a floating gate transistor, or a charge trap type of memory cell that includes a charge-trapping transistor.

[0097] In some implementations, each memory cell 306 is a single-level cell (SLC) that has two possible memory states and thus can store one bit of data. For example, a first memory state "0" can correspond to a first voltage range, and a second memory state "1" can correspond to a second voltage range. In some implementations, each memory cell 306 is capable of storing more than a single bit of data in more than two memory states. For example, a multi-level cell (MLC) can store two bits of data per memory cell, a triple-level cell (TLC) stores three bits of data per memory cell, or a quad-level cell (QLC) stores four bits of data per memory cell.

[0098] As shown in Figure 1 As shown in

[0099] Figure 2 A side view of a cross-section of an exemplary memory cell array 301 including NAND memory strings 308 is shown in accordance with some aspects of the present disclosure. As shown in Figure 2 As shown in

[0100] Figure 3 Some exemplary peripheral circuits are shown, including a page buffer 504, a column decoder 506, a row decoder 508, a voltage generator 510, control logic 512, registers 514, input / output (I / O) circuits 516. It should be appreciated that in some examples, other peripheral circuits can also be includedFigure 3 additional peripheral circuitry not shown.

[0101] Figure 4 is a three-dimensional memory read disturb schematic diagram according to an exemplary embodiment of the present disclosure. Read disturb is an important failure mechanism for flash media, and managing read disturb is an important work for flash media storage products. Common read disturbs include single page read disturb and block level read disturb. In order to manage read disturb problems, the memory records the read count of each physical block or super block of the flash memory, the read count is the number of read operations on the storage block, including the number of read operations after programming operation, and the number of read operations alone, the physical block is a set of physical pages connected to the same source that can perform erase operation at the same time; a plurality of physical blocks form a storage plane, and the super block is a storage block formed by a plurality of physical blocks in different storage planes that can perform read and write operations at the same time. Once the read count reaches the read count threshold, the controller will scan all physical pages of the flash to check if there is a risk, here the scan is a read operation under the default voltage condition. If there is a risk (some physical page error bits reach a critical value), the controller will move the valid data of the physical block or super block to a new physical block or super block, and if there is no risk, wait for the next read count to reach the critical value. The default read voltage scans and then obtains the number of error bits from the error correction code engine, and does not really reflect the physical effect of read disturb, but only roughly reflects some physical error conditions, which may be caused by other factors such as data retention, cross temperature and other reliability problems, or even caused by the wrong default read voltage. This will cause unnecessary data scanning and data moving operations, thereby affecting the endurance of the entire system storage product.

[0102] Reference Figure 4As shown, current 3D memory (such as 3D NAND flash) employs a method during read operations: when reading data from a memory cell, a read voltage V-ref is applied to the selected layer word line (gate), while a pass voltage V-pass is applied to the unselected layer gate. Typically, the pass voltage V-pass reaches over 6V. After tens of thousands of read operations, the pass voltage V-pass causes a significant increase in the threshold voltage, especially in erase state (L0) and low programming state, leading to read errors. This is the read interference caused by the pass voltage. Experiments show that read interference is positively correlated with the voltage causing it; the higher the pass voltage V-pass, the more severe the read interference.

[0103] Figure 5 This is a schematic diagram of the read voltage V-ref and the on-state voltage V-pass of a three-dimensional memory according to an exemplary embodiment of this disclosure. Figure 5 As shown, taking an MLC with four storage states as an example, the horizontal axis represents the threshold voltage distribution of the four different storage states, where L0 is the threshold voltage distribution of the erase state, and L1-L3 are the threshold voltage distributions of different programming states. The vertical axis represents the number of storage cells in each state. It can be seen that the number of storage cells in each state follows a Gaussian distribution. The read voltage V-ref is between any two adjacent storage states, and the read voltages from smallest to largest are Vref. RL1 V RL2 V RL3 Among them, V RL1 The default read voltage for the erase state is the maximum value of the turn-on voltage V-pass that is higher than the threshold voltage.

[0104] Figure 6 This is a schematic diagram of a three-dimensional memory read interference scanning voltage according to an exemplary embodiment of the present disclosure. For example... Figure 6 As shown, taking a TLC with eight memory states as an example, the horizontal axis represents the threshold voltage distribution of the eight different memory states, where L0 is the threshold voltage distribution of the erase state, and L1-L7 are the threshold voltage distributions of different programming states. The vertical axis represents the number of memory cells in each state. It can be seen that the number of memory cells in each state follows a Gaussian distribution. Read interference causes the threshold voltages of L0-L8 to broaden and shift to the right. The impact on the threshold voltage distribution of L0 in the erase state is the greatest. This is because when a memory cell is in the erase state, it has no stored charge and is most susceptible to being written charge by the turn-on voltage V-pass, causing the threshold voltage distribution of L0 in the erase state to broaden and shift to the right. Figure 6As shown in the figure. Based on this principle, when any physical page is subjected to read disturbance, the threshold voltages of different states of the physical page are affected and spread and move to the right, among which the threshold voltage distribution of the erase state L0 is affected the most, so that the read disturbance of the whole physical page can be judged by only reading the threshold voltage of the erase state L0. In order to accurately read the number of storage cells in the erase state L0, the single read voltage V SLR lower than the default read voltage V RL1 of the erase state when not subjected to read disturbance is used when performing read disturbance scanning. RL1 The difference between the maximum threshold voltage of the erase state of the storage block and the default read voltage V RL1 of the erase state when not subjected to read disturbance is E0, so that V SLR -E0≤V RL1 <V RL1 .

[0105] In an embodiment of the present disclosure, V SLR -1 / 2E0≤V RL1 <V SLR .

[0106] From the above formula, the single read voltage V RL1 is lower than the default read voltage V SLR of the erase state when not subjected to read disturbance. Since the threshold voltage of the erase state L0 spreads and moves to the right, the smaller the value of V SLR is, the smaller the number of storage cells in L0 read is. Therefore, adjusting the size of the single read voltage can adjust the accuracy of the read disturbance processing. If the accuracy of the read disturbance processing is required to be high, the single read voltage is reduced, and if the accuracy of the read disturbance processing is required to be low, the single read voltage is increased.

[0107] Figure 7 is a flowchart of a three-dimensional memory read disturbance scanning according to an exemplary embodiment of the present disclosure. As shown in the figure, the flow of the three-dimensional memory read disturbance scanning includes the following steps: Figure 7 Step S10, the host performs a read operation on a first storage block;

[0108] Step S20, record the number of read times of the first storage block;

[0109] Step S30, compare the number of read times of the first storage block with a read time threshold to determine whether the number of read times is greater than the read time threshold;

[0110] If the read frequency of the first memory block is greater than the read frequency threshold, it indicates that the read frequency of the first memory block is high, and the first memory block may have read disturbance errors, and thus read disturbance processing is performed on the first memory block. If the read frequency of the first memory block is less than the read frequency threshold, it indicates that the read frequency of the first memory block is not high, and there is no read disturbance error, and thus no read disturbance processing is performed on the first memory block, and the process ends.

[0112] The read disturbance processing on the first memory block includes the following steps:

[0113] In step S40, read disturbance processing is performed on the maximum read disturbance physical page recorded in the first memory block in the last read disturbance scan.

[0114] In step S50, read disturbance processing is sequentially performed on other physical pages of the first memory block.

[0115] After the read disturbance processing on the first memory block is completed, the process ends.

[0116] In an embodiment of the present disclosure, the read disturbance processing on the first memory block can only include step S50, in which read disturbance processing is sequentially performed on all physical pages of the first memory block.

[0117] In an embodiment of the present disclosure, in order to improve the scanning efficiency, the read disturbance processing on the first memory block can only include step S40, in which read disturbance processing is performed on the maximum read disturbance physical page recorded in the first memory block in the last read disturbance scan.

[0118] In an embodiment of the present disclosure, step S40, in which read disturbance processing is performed on the maximum read disturbance physical page recorded in the first memory block in the last read disturbance scan, can be performed first. Then, it is determined whether step S50, in which read disturbance processing is sequentially performed on other physical pages of the first memory block, needs to be performed according to the read disturbance result of step S40. That is, if the read disturbance on the maximum read disturbance physical page recorded in the first memory block in the last read disturbance scan is not serious, and the data of the physical page does not need to be moved, it can be considered that the read disturbance on other physical pages of the first memory block is lower than that on the maximum read disturbance physical page recorded in the last read disturbance scan, and thus step S50 does not need to be performed. Conversely, if the read disturbance on the maximum read disturbance physical page recorded in the first memory block in the last read disturbance scan is serious, and the data of the physical page needs to be moved, it can be considered that other physical pages of the first memory block may also be seriously disturbed, and data movement is needed, and thus step S50 is performed.

[0119] It should be noted that the storage block described in the present disclosure can be a two-dimensional storage block or a three-dimensional storage block. The storage block is composed of storage cells, the storage cells controlled by the same word line form a physical page, and the multiple physical pages connected to the same source line that can be erased simultaneously form a storage block.

[0120] Figure 8 is a flowchart of reading interference processing of a first physical page of a first storage block of a three-dimensional memory according to an exemplary embodiment of the present disclosure. As shown in Figure 8 , the step S50 of reading interference processing of the first physical page specifically includes the following steps:

[0121] S501, setting a single-state reading voltage V SLR . As described above, the single reading voltage is lower than the default reading voltage V RL1 of the erased state when not subjected to read interference, and its value is adjusted according to the characteristics of different storage particles, and the adjustment range is V RL1 -E0≤V SLR <V RL1 , specifically, for example, V SLR =V RL1 -E0, V SLR =V RL1 -1 / 2E0, V SLR =V RL1 -1 / 3E0, etc. Within the adjustment range, the larger V SLR , the closer to V RL1 . When the performance of the storage particles is good and not easy to be subjected to read interference, the threshold voltage distribution of the storage particles in the erased state is less affected, the threshold voltage of the storage particles in the erased state is less widened and moved to the right, and V SLR can be set to a smaller value; on the contrary, when the performance of the storage particles is poor and easy to be subjected to read interference, the threshold voltage distribution of the storage particles in the erased state is more affected, the threshold voltage of the storage particles in the erased state is more widened and moved to the right, and V SLR can be set to a larger value, at this time, V SLR is closer to the default reading voltage V RL1 of the erased state when not subjected to read interference.

[0122] S502, reading the first physical page using V SLR , and recording the number N1 of storage cells in the erased state;

[0123] S503, it is determined whether N1 is less than a storage unit quantity threshold. The storage unit quantity threshold is determined according to the quantity of storage units in the physical page in an erased state when the physical page is not subjected to read disturbance. When the first physical page of the first memory block is programmed and the programming is completed, the quantity of storage units in each state in the first physical page is substantially uniformly distributed. Taking TLC as an example, when the first physical page of the first memory block is not subjected to read disturbance, the quantity of storage units in an erased state in the first physical page storing data accounts for about 1 / 8 of the total quantity of storage units in the physical page. After the first physical page is subjected to read disturbance, the quantity of storage units in an erased state in the physical page decreases. When the read disturbance of the physical page is relatively serious, read disturbance processing needs to be performed. The storage unit quantity threshold is set to determine the degree of read disturbance. The storage unit quantity threshold is lower than 1 / 8 of the total quantity of storage units in the first physical page, and the specific value is affected by the performance of the storage grain, the error correction capability of the controller, the required data stability, and the like.

[0124] According to the determination result of S503, if N1 is less than the storage unit quantity threshold, it indicates that the read disturbance of the read physical page is relatively serious, and S504 is entered to transfer the data of the physical page to the first physical page of the second memory block. The "transfer" refers to copying and writing the data of the physical page, that is, reading the data of the physical page and writing the data to the first physical page of the second memory block.

[0125] In an embodiment of the present disclosure, the address of the first physical page of the first memory block is mapped to the first physical page of the second memory block.

[0126] According to the determination result of S503, if N1 is greater than the storage unit quantity threshold, it indicates that the read disturbance of the read physical page is relatively light, and data transfer is not needed, and the read disturbance processing of the first physical page is completed.

[0127] In an embodiment of the present disclosure, the quantity of storage units of the first physical page of the first memory block is recorded as the minimum storage unit quantity greater than the storage unit threshold, as Nmin.

[0128] In an embodiment of the present disclosure, the address of the physical page corresponding to Nmin is recorded.

[0129] After the read disturbance processing of the first physical page of the first memory is completed, the read disturbance processing is sequentially performed on other physical pages of the first memory.

[0130] Figure 9 is a flowchart of read disturbance processing of other physical pages than the first physical page of the first memory block of the three-dimensional memory according to an exemplary embodiment of the present disclosure. As shown in FIG. 5B, the read disturbance processing of the first physical page of the first memory block is completed, and the read disturbance processing of other physical pages of the first memory block is sequentially performed. Figure 9As shown, the read disturb processing on the other physical page includes the following steps:

[0131] S501' step, setting a single-state read voltage V SLR In an embodiment of the present disclosure, the single-state read voltage set in the S501' step is the same as the single-state read voltage set in the S501 step. In an embodiment of the present disclosure, the single-state read voltage is set only when the first physical page of the first memory block is read, and the single-state read voltage is not re-set when other physical pages of the first memory block are read, but the single-state read voltage set when the first physical page of the first memory block is read is directly used.

[0132] S502' step, using V SLR The second physical page is read, and the number of storage cells in the erased state N2 is recorded;

[0133] S503' step, judging whether N2 is less than a storage cell number threshold. The storage cell number threshold is the same as the storage cell number threshold stored in the S503 step.

[0134] According to the judgment result of the S503' step, if N2 is less than the storage cell number threshold, it indicates that the read disturbance degree of the read physical page is relatively serious, and the S504' step is entered to move the data of the second physical page of the first memory block to the second physical page of the second memory block.

[0135] In an embodiment of the present disclosure, the address of the second physical page of the first memory block is mapped to the second physical page of the second memory block.

[0136] According to the judgment result of the S503' step, if N2 is greater than the storage cell number threshold, it indicates that the read disturbance degree of the read physical page is relatively light, and data movement is not needed, and the read disturb processing on the second physical page is completed.

[0137] In an embodiment of the present disclosure, the read disturb processing on the second physical page further includes the following steps:

[0138] S505' step, judging whether N2 is less than the minimum storage cell number Nmin recorded last time. If N2 is not less than Nmin, the read disturb processing on the second physical page is completed. If N2 is less than Nmin, the S506' step is performed, and N2 is taken as Nmin.

[0139] In an embodiment of the present disclosure, the address of the physical page corresponding to Nmin is recorded.

[0140] After the read disturb processing of the second physical page of the first memory block is completed, the read disturb processing of other physical pages is performed in sequence, and the read disturb processing steps are the same as the read disturb processing steps of the second physical page, until the read disturb scanning of all physical pages of the first memory block is completed.

[0141] At this time, Nmin represents the minimum number of storage cells greater than the storage cell threshold in all physical pages of the first memory block, and the physical page corresponding to Nmin is the physical page with the greatest read disturb degree among the physical pages without data moving.

[0142] After the read disturb processing operation of the first memory block is completed, the first memory block can be regarded as a memory block without read disturb, and therefore the read times of the first memory block are reset to zero; when the read times of the first memory block are greater than the read times threshold again, the read disturb processing of the first memory block is performed again.

[0143] Since the physical page address corresponding to Nmin is recorded during the previous read disturb processing, Nmin corresponds to the physical page with the greatest read disturb degree among the physical pages without data moving, and therefore the read disturb processing of the first memory block can be performed preferentially on the physical page corresponding to Nmin. In special cases, in order to improve the read disturb processing speed, the read disturb processing can be performed only on the physical page corresponding to Nmin.

[0144] Another aspect of the present disclosure provides a memory controller, which is configured to:

[0145] Obtain the read times data of the memory block and the read disturb scanning data of the physical page, and the physical page address data; calculate the relationship between the read times data of the memory block and the read times threshold, and the relationship between the read disturb scanning data of the physical page and the storage cell number threshold; determine whether to perform the read disturb processing and the data moving according to the calculation result, and control the data moving.

[0146] In an embodiment of the present disclosure, the memory controller, the read disturb scanning data is obtained by applying a single-state read voltage V SLR to the physical page in the memory block.

[0147] In an embodiment of the present disclosure, the memory controller, the read disturb scanning data includes applying a single-state read voltage V SLR to the physical page in the memory block.

[0148] In an embodiment of the present disclosure, the memory controller,

[0149] The maximum value of the initial erase state threshold voltage of the memory block and the default read voltage V RL1the difference value of E0, then the single-state reading voltage V SLR the value range of V RL1 -E0≤V SLR <V RL1 .

[0150] In an embodiment of the present disclosure, the memory controller is configured to reset the reading times of the first storage block to zero after performing the read interference processing operation on the first storage block.

[0151] In an embodiment of the present disclosure, the memory controller is configured to instruct to store the physical page address data to a designated location of the storage device.

[0152] In another aspect of the present disclosure, a storage system is provided, which includes a storage device and the memory controller or the memory controller capable of performing the control method.

[0153] The storage system can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system can be applied to and packaged into different types of electronic products, for example, a mobile phone (e.g., a cell phone), a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a game console, a printer, a positioning device, a wearable device, a smart sensor, a mobile power supply, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having a storage.

[0154] In some embodiments, the storage system includes a controller and a three-dimensional memory, and the storage system can be integrated into a three-dimensional memory card.

[0155] The three-dimensional memory card includes any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a three-dimensional memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD) card, or a UFS.

[0156] In other embodiments, the storage system includes a controller and a plurality of three-dimensional memories, the storage system 1000 is integrated into a solid state drive (SSD).

[0157] Some embodiments of the present disclosure also provide an electronic device. The electronic device can be any one of a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0158] The electronic device can include the storage system described above, and can also include at least one of a central processing unit (CPU) and a cache, etc. Figure 10 A block diagram of an exemplary system 100 having a memory device is shown in accordance with some aspects of the present disclosure. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage therein. As shown, Figure 10 The system 100 can include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106, as shown. The host 108 can include a processor of an electronic device, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). The host 108 can also include a storage interface for coupling with the memory system 102, which is configured to comply with a corresponding protocol (such as the NVMe, PCIe, etc. protocol), the host 108 can be configured to send data to or receive data from the memory device 104 through, for example, the storage interface. To send data to or receive data from the memory device 104, the host 108 can send instructions to the memory system 102 in addition to the data. The memory device 104 can be any memory device disclosed in the present disclosure.

[0159] According to some embodiments, a memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 can be specifically implemented by a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gated logic, discrete hardware circuits, or a combination thereof, and other suitable hardware, firmware, and / or software configured to perform the various functions detailed herein. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108 through its front side interface. In some embodiments, the memory controller 106 is designed for operation in low duty cycle environments, such as secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, mobile telephones, etc. In some embodiments, the memory controller 106 is designed for operation in high duty cycle environments, such as SSDs or embedded multi-media-cards (eMMCs) used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays. The memory controller 106 can be configured to control operations of the memory device 104, such as read, erase, and program operations.

[0160] The memory controller 106 can also be configured to manage various functions with respect to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translations, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to handle error correction codes (ECC) with respect to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, e.g., formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., the host 108) in accordance with a particular communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, which can be, e.g., a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0161] The memory controller 106 and the one or more memory devices 104 can be integrated into various types of memory systems, e.g., included in the same package (e.g., a universal Flash storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. In as Figure 11AIn one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include PC cards (Personal Computer Memory Card International Association, PCMCIA), CF cards, smart media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMC micro), SD cards (SD, mini SD, micro SD, SDHC), UFS, etc. The memory card 202 may also include a memory card connector 204 configured to couple the memory card 202 to a host computer (e.g., ...). Figure 10 (Host 108 in the middle). In such Figure 11B In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include an SSD connector 208 configured to couple the SSD 206 to a host computer (e.g., ...). Figure 10 (The host 108 in the middle). In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0162] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for operating a memory controller, characterized in that, The first physical page of the first storage block is subjected to read interference processing, which includes the following steps: A read interference scan is performed on the first physical page of the first storage block to obtain the number N1 of storage cells in the erase state within the first physical page; the read interference scan involves applying a single-state read voltage V to the first physical page. SLR The single-state read voltage V is used for reading operations. SLR The default read voltage V is lower than that of the first physical page erase state. RL1 ; If N1 is less than the number of storage units, the data in the first physical page is moved to the second storage block.

2. The method of operating the memory controller according to claim 1, characterized in that, When there is no read interference, obtain the maximum value V of the physical page erase state threshold voltage. L0 ; Obtain the V RL1 With V L0 The difference is E0; Set single-state read voltage V SLR The single-state read voltage V SLR The range of values ​​for V is RL1 -E0≤V SLR <V RL1 .

3. The method of operating the memory controller according to claim 2, characterized in that, In RL1 -1 / 2E0≤V SLR <V RL1 。 4. The method of operating the memory controller according to claim 1, characterized in that, After performing read interference processing on the first physical page, read interference processing is performed on the other physical pages of the first storage block until the read interference processing of the first storage block is completed.

5. The method of operating the memory controller according to claim 1, characterized in that, Before performing read interference processing on the first storage block, the method further includes: Get the number of reads of the first storage block; Compare the number of reads of the first storage block with the number of reads threshold; If the number of reads of the first storage block exceeds the read count threshold, then read interference processing is applied to the first storage block.

6. The method of operating the memory controller according to claim 5, characterized in that, After completing the read interference processing of the first storage block, the read count of the first storage block is reset to zero; If the number of reads of the first storage block exceeds the read count threshold, read interference processing is applied to the first storage block again.

7. The method of operating the memory controller according to claim 4, characterized in that, The read interference processing of the first storage block includes recording the minimum number of storage cells greater than the storage cell number threshold in all physical pages of the first storage block as Nmin, and recording the address of Nmin; when performing read interference processing on the first storage block again, priority is given to scanning or only scanning the physical page corresponding to Nmin.

8. The method of operating the memory controller according to any one of claims 1-7, characterized in that, The specific read interference processing operation is as follows: Set single-state read voltage V SLR ; Apply a single-state read voltage V to the first physical page SLR Perform a read operation; Record the number N1 of storage units in the first physical page that are in the erase state; Compare N1 with the threshold for the number of memory cells; If N1 is less than the number of storage units, then the data of the first physical page is moved to the second storage block; If N1 is greater than the storage unit number threshold, then N1 is recorded as the minimum storage unit number Nmin, and the address of the first physical page is recorded.

9. The method of operating the memory controller according to claim 8, characterized in that, After performing read interference processing on the first physical page, performing read interference processing on the second physical page includes the following steps: Apply a single-state read voltage V to the second physical page SLR Perform a read operation; Record the number N2 of memory cells in the erased state in the second physical page; Compare N2 with the threshold for the number of storage units; If N2 is less than the number of storage units, then the data of the second physical page is moved to the second storage block; If N2 is greater than the threshold for the number of storage units Then compare N2 with Nmin. If N2 is less than Nmin, then replace N2 with Nmin and record the address of the second physical page.

10. A memory controller, characterized in that, The memory controller is configured as follows: The first physical page of the first storage block is subjected to read interference processing, which includes the following steps: A read interference scan is performed on the first physical page of the first storage block to obtain the number N1 of storage cells in the erase state within the first physical page; the read interference scan involves applying a single-state read voltage V to the first physical page. SLR The single-state read voltage V is used for reading operations. SLR The default read voltage V is lower than that of the first physical page erase state. RL1 ; If N1 is less than the number of storage units, the data in the first physical page is moved to the second storage block.

11. The memory controller according to claim 10, characterized in that, When there is no read interference, obtain the maximum value V of the physical page erase state threshold voltage. L0 ; Obtain the V RL1 With V L0 The difference is E0; Set single-state read voltage V SLR The single-state read voltage V SLR The range of values ​​for V is RL1 -E0≤V SLR <V RL1 .

12. The memory controller according to claim 10, characterized in that, The memory controller is configured to further include, before performing read interference processing on the first physical page of the first memory block: Get the number of reads of the first storage block; Compare the number of reads of the first storage block with the number of reads threshold; If the number of reads of the first storage block exceeds the read count threshold, then read interference processing is applied to the first physical page of the first storage block.

13. The memory controller according to claim 10, characterized in that, The memory controller is configured to reset the read count of the first memory block to zero after performing read interference processing on the first memory block; If the number of reads of the first storage block exceeds the read count threshold again, the read interference processing of the first storage block will be performed again.

14. A storage system comprising a memory device and a memory controller as described in claims 10-13 or a memory controller capable of performing the operating methods described in claims 1-9.

15. An electronic device comprising the storage system of claim 14.

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