Semiconductor device and method for forming the same

Abstract

The presently disclosed embodiment discloses a semiconductor device and a method for forming the same, the method comprising: providing a substrate; injecting first doping ions into a first depth interval of the substrate to form a first doping layer; activating the first doping layer at high temperature to form a drain layer; injecting second doping ions into a second depth interval of the substrate to form a second doping layer; the second depth interval does not overlap with the first depth interval; activating the second doping layer at high temperature to form a source layer; etching the source layer, the drain layer, and the substrate between the source layer and the drain layer to form a channel column array; the channel column array comprises a plurality of transistor channel columns; the two ends of the transistor channel column respectively comprise a source and a drain; and forming a plurality of storage capacitors that are not connected to each other on the sources of the plurality of channel columns of the channel column array.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and relate to, but are not limited to, a semiconductor device and a method for forming the same. Background Art

[0002] DRAM (Dynamic Random Access Memory) architecture can be a buried channel transistor (BCT) architecture. In this architecture, the transistor's source S and drain D are located horizontally on either side of the gate G. The source S can be connected to a bit line, and the drain D can be connected to a capacitor. This occupies different locations on the horizontal plane, resulting in a larger horizontal area for the buried channel transistor. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for forming the same.

[0004] In a first aspect, an embodiment of the present disclosure provides a method for forming a semiconductor device, comprising:

[0005] Providing a substrate; the substrate having a first surface and a second surface;

[0006] Implanting first doping ions into a first depth interval of the substrate to form a first doping layer;

[0007] activating the first doped layer at high temperature to form a drain layer;

[0008] implanting second doping ions into a second depth interval of the substrate to form a second doping layer; wherein the second depth interval does not overlap with the first depth interval;

[0009] activating the second doped layer at a high temperature to form a source layer;

[0010] Etching the source layer, the drain layer, and the substrate between the source layer and the drain layer to form a channel pillar array; the channel pillar array includes a plurality of transistor channel pillars; both ends of the transistor channel pillar include a source and a drain respectively;

[0011] A plurality of storage capacitors that are not connected to each other are formed on the sources of the plurality of channel pillars in the channel pillar array.

[0012] In some embodiments, the method further comprises:

[0013] An oxide layer is formed on the first surface of the substrate; the oxide layer is used as an etching stop layer for etching the source layer, the drain layer, and the substrate between the source layer and the drain layer.

[0014] In some embodiments, the step of forming an oxide layer on the first surface of the substrate is before the step of forming the first doping layer; and the step of implanting first doping ions into the first region of the substrate to form the first doping layer includes:

[0015] The first doping ions are implanted from the surface of the oxide layer along a first direction into a first depth range in the substrate to form the first doping layer; wherein the first direction is from the first surface to the second surface of the substrate.

[0016] In some embodiments, before forming the first doping layer, the method further includes:

[0017] Performing ion implantation from the oxide layer into a third depth interval of the substrate along a first direction to form an ion implantation layer; the distance between the third depth interval and the first surface is greater than the distance between the first depth interval and the first surface;

[0018] After the step of forming the first doping layer, the method further includes:

[0019] removing a portion of the substrate between the ion implantation layer and the second surface using the ion implantation layer;

[0020] The ion implantation layer is removed to expose the third surface of the substrate.

[0021] In some embodiments, the method further comprises:

[0022] Provide carrier wafers;

[0023] The oxide layer is bonded to the carrier wafer.

[0024] In some embodiments, the method further comprises:

[0025] The carrier wafer and the substrate are turned over so that the third surface of the substrate faces vertically upward.

[0026] In some embodiments, the method further comprises:

[0027] The third surface is planarized.

[0028] In some embodiments, the step of implanting second doping ions into the second depth interval of the substrate to form a second doping layer includes:

[0029] The second doping ions are implanted from the third surface into a second depth range of the substrate along a second direction to form the second doping layer; wherein the second direction is from the third surface to the first surface.

[0030] In some embodiments, after forming the plurality of storage capacitors, the method further includes:

[0031] The oxide layer is removed.

[0032] In some embodiments, after etching, a plurality of parallel first trenches are formed between the channel pillar arrays along a third direction; the third direction is a direction parallel to the first surface of the substrate;

[0033] The method further comprises:

[0034] A word line structure is formed in the first trench.

[0035] In some embodiments, before forming the word line structure in the first trench, the method further includes:

[0036] Filling a first dielectric material between the etched channel pillar arrays;

[0037] A plurality of first trenches are formed in the first dielectric material along the third direction.

[0038] In some embodiments, the method further comprises:

[0039] A bit line structure connecting the plurality of storage capacitors is formed.

[0040] In a second aspect, an embodiment of the present disclosure provides a semiconductor device, which is formed by the method described in any of the above embodiments.

[0041] In the disclosed embodiment, high-temperature activation of the first and second ion-implanted layers, along with the formation of the source and drain electrodes, has already been completed before forming the storage capacitor. This eliminates the need for high-temperature activation of the device after the storage capacitor is formed. This ensures that the performance of the storage capacitor's materials is not damaged by high temperatures and that the resulting device meets design requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a schematic diagram of a semiconductor structure in some embodiments;

[0043] Figure 2 is a schematic diagram of a semiconductor structure in some embodiments;

[0044] Figures 3 to 13 A flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0045] Figures 14 to 30 A schematic diagram of forming a semiconductor device and an intermediate structure thereof using a method provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] To facilitate understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0047] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of an actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0048] Generally, terms can be understood, at least in part, from their use in context. For example, depending, at least in part, on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "the" can likewise be understood to convey singular usage or to convey plural usage, depending, at least in part, on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending, at least in part, on the context.

[0049] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0050] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0051] like Figure 1As shown, the DRAM architecture can be a BCT architecture. In this architecture, the source S and drain D of the transistor are located on either side of the gate G. The source S can be connected to a bit line, and the drain D can be connected to a capacitor. In this way, the source S and drain D occupy different positions on the horizontal plane, resulting in a larger horizontal area for the buried channel transistor.

[0052] In the embodiment of the present disclosure, the DRAM architecture can be as follows: Figure 2 The vertical channel memory architecture (VerticalChannel Array Transistor, VCAT) shown. Figure 2 The source S and drain D of the transistor 20 are located at the upper and lower ends of the vertical channel region. In some embodiments, during the formation of the semiconductor device, the wires or other structures connecting the devices can be respectively arranged on the upper and lower surfaces of the semiconductor structure (for example, a wafer) in combination with wafer bonding and back substrate thinning technology. The specific formation method can be: first define the source on the upper surface of the semiconductor structure, and then flip the semiconductor structure using bonding technology, so that the drain can be defined on the upper surface of the flipped semiconductor structure (that is, the lower surface of the semiconductor structure before flipping (the other side opposite to the upper surface)). In this way, the industry's most advanced 4F 2 However, because the drain and source are located at both ends of the semiconductor structure, they need to be activated separately at high temperatures. If the drain is flipped and the source is facing upward, the drain will be activated at high temperatures. Since single-crystal silicon has good thermal conductivity, it will absorb the high temperature of activation and conduct the temperature downward. When the temperature at the drain exceeds 950 degrees, the temperature at the capacitor structure 30 is only slightly less than 800 degrees. The high-k dielectric material used in the capacitor structure 30 will degrade and decompose at high temperatures. This method also adds a high-temperature activation process at the drain, which increases the cost.

[0053] If the source is defined on the upper surface of the semiconductor structure first and then the drain is defined from the upper surface of the semiconductor structure, the ion implanted impurities will diffuse too widely and the target semiconductor device cannot be formed.

[0054] The present disclosure provides a method for forming a semiconductor device, such as Figure 3 As shown, including:

[0055] Step S101: providing a substrate;

[0056] Step S102: implanting first doping ions into a first depth interval of the substrate to form a first doping layer;

[0057] Step S103: activating the first doped layer at high temperature to form a drain layer;

[0058] Step S104: implanting second doping ions into a second depth interval of the substrate to form a second doping layer; the second depth interval does not overlap with the first depth interval;

[0059] Step S105: activating the second doped layer at high temperature to form a source layer;

[0060] Step S106: etching the source layer, the drain layer, and the substrate between the source layer and the drain layer to form a channel pillar array; the channel pillar array includes a plurality of transistor channel pillars; the two ends of the transistor channel pillar include a source and a drain respectively;

[0061] Step S107 , forming a plurality of storage capacitors that are not connected to each other on the sources of the plurality of channel pillars in the channel pillar array.

[0062] First, step S101 is performed, and the substrate provided may be Figure 14 The substrate 100 shown may include a P-type semiconductor material substrate (e.g., a silicon (Si) substrate or a germanium (Ge) substrate), an N-type semiconductor substrate (e.g., an indium phosphide (InP) substrate), a compound semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate), a silicon-on-insulator (SOI) substrate, and a germanium-on-insulator (GeOI) substrate.

[0063] Execute step S102, and implant the first dopant ions into the first depth interval of the substrate to form a first doped layer. The first dopant ions include two types of ions, N-type and P-type, wherein N-type ions include phosphorus (P), arsenic (As) and antimony (Sb), etc. P-type ions include boron (B) and indium (In), etc. The depth interval of ion implantation is determined by the energy of ion implantation, and the implantation depth of the first dopant ions can be adjusted by adjusting the energy of ion implantation. Ion implantation can also consider the concentration of ion implantation. Different implantation concentrations of the same implanted ions will have different effects on device performance. In some embodiments, a lower concentration of ions can be used to form a lightly doped first doped layer to prevent hot carrier effects generated by the device.

[0064] Execute step S103, high temperature activation of the first doped layer to form a drain layer. After the first doped layer is formed, in order to reduce the ion diffusion in the first doped layer, the first doped layer can also be activated at high temperature to fix the injected ions in the first doped layer. Here, the first doped layer after high temperature activation is called the drain layer, and the drain layer can form the drain of the MOS device in the subsequent process. In order to activate the injected first doped ions and restore the mobility and other material parameters, the first doped layer can be annealed at an appropriate time and temperature, that is, the above-mentioned high temperature activation operation. Exemplarily, the temperature of the high temperature activation can be 900 degrees.

[0065] Step S104 is executed to implant second doping ions into a second depth interval of the substrate to form a second doping layer; the second depth interval does not overlap with the first depth interval.

[0066] Second doping ions are injected into the second depth interval of the substrate to form a second doping layer. The second doping ions include two types of ions, N-type and P-type, among which N-type ions include phosphorus (P), arsenic (As) and antimony (Sb). P-type ions include boron (B) and indium (In). The depth interval of ion injection is determined by the energy of ion injection, and the injection depth of the second doping ions can be adjusted by adjusting the energy of ion injection. Here, the first depth interval and the second depth interval represent the injection depth ranges of the two ion injections, that is, the positions of the first doping layer and the second doping layer in the substrate. The second depth interval does not overlap with the first depth interval, and there is a certain thickness of substrate between the two, so the injection energy of the second doping ions can be different from the injection energy of the first ions.

[0067] In some embodiments, the ion implantation directions of the first doping layer formed by the first ion implantation and the second doping layer formed by the second ion implantation can be different. Figure 4 The first ion implantation is performed from the S1 surface of the substrate 100 into the substrate 100 to form a first doped layer. The second ion implantation is performed from the S2 surface of the substrate 100 into the substrate 100 to form a second doped layer. The ion implantation depths of the two ion implantations extend from the S1 surface and the S2 surface into the substrate, respectively, and thus can be the same or different. However, the first depth interval where the first doped layer is formed and the second depth interval where the second doped layer is formed are located at different locations and do not overlap.

[0068] Furthermore, in some embodiments, the ion implantation concentration of the second doping layer may be the same as or different from the ion implantation concentration of the first doping layer.

[0069] Step S105 is executed to activate the second doped layer at high temperature to form a source layer. In some embodiments, after forming the second doped layer, the second doped layer may be activated at high temperature to reduce ion diffusion in the second doped layer, thereby fixing the implanted ions in the second doped layer. Here, the second doped layer after high temperature activation is referred to as the source layer. The source layer may form the source of the device in subsequent processes. The depth of the source layer in the substrate is greater than the depth of the drain layer in the substrate.

[0070] Step S106 is performed to etch the source layer, drain layer, and the substrate between the source and drain layers to form a channel pillar array. The channel pillar array includes multiple transistor channel pillars. The transistor channel pillars have a source and a drain at each end, respectively, and a channel between the source and drain. Because the source and drain layers are at different depths in the substrate, a portion of the substrate remains between the source and drain layers.

[0071] The above-mentioned etching process includes but is not limited to dry etching and wet etching, wherein dry etching includes but is not limited to ion milling etching, plasma etching and reactive ion etching. The etching process can also include pattern etching, in which a masking layer (a patterned photoresist) is used to define the surface material area to be etched, and only the selected portion of the substrate (the portion not covered by the photoresist) is etched away during the etching process. Pattern etching can be used to produce a variety of different feature patterns on the substrate. The two ends of the multiple transistor channel pillars formed after etching are respectively a source composed of a portion of the source layer and a drain formed by a portion of the drain layer. That is to say, since the source and drain of the transistor have been doped and high-temperature activated in the above-mentioned steps S102 to S105, the transistor channel pillar and the source and drain at both ends can be formed after etching here.

[0072] Execute step S107 to form a plurality of storage capacitors that are not connected to each other on the source electrodes of the plurality of channel pillars of the channel pillar array. In some embodiments, the substrate above the source electrode can be removed first, and then the storage capacitor can be formed on the source electrode. A storage node contact structure can also be included between the storage capacitor and the source electrode. It can be understood that, when the structure remains unchanged, a high-k (dielectric constant) dielectric material can be selected to increase the capacity of the storage capacitor. The storage capacitor can be a columnar capacitor. In some embodiments, the dielectric material in the storage capacitor can be a material having a relative dielectric constant value greater than a preset relative dielectric constant value, for example, the preset relative dielectric constant value can be 3.9, and the dielectric material can be TiN (titanium nitride).

[0073] After performing the above steps, the semiconductor device according to the embodiment of the present disclosure can be formed.

[0074] In the disclosed embodiment, high-temperature activation of the first and second ion-implanted layers, along with the formation of the source and drain electrodes, has already been completed before forming the storage capacitor. This eliminates the need for high-temperature activation of the device after the storage capacitor is formed. This ensures that the performance of the storage capacitor's materials is not damaged by high temperatures, ensuring that the performance of the resulting device meets design requirements.

[0075] In some embodiments, the above method may further include:

[0076] Step S201: forming an oxide layer on the first surface of the substrate; the oxide layer is used as an etching stop layer for etching the source layer, the drain layer, and the substrate between the source layer and the drain layer. Therefore, step S201 can be performed between step S106 and step S101. For example, Figure 4 As shown, step S201 may be executed after step S101.

[0077] An oxide layer is formed between the drain layer and the substrate, so that when etching the source layer, the drain layer, and the substrate between the source layer and the drain layer, the oxide layer can be used as an etch stop layer for this etching to avoid over-etching the substrate. The oxide layer can be formed using a growth process, for example, in-situ steam generation (ISSG) in a selective growth manner. The in-situ steam generation method is a thermal annealing deposition method that forms a high-quality oxide film by heating in a cavity and introducing oxygen atoms to combine with atoms in the semiconductor substrate. A deposition process can also be used, and the deposition process can include chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, metal organic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD). The material of the oxide layer can be silicon dioxide.

[0078] In some embodiments, the above step S201 may be performed before step S102; Figure 4 As shown, in the above step S102, first doping ions are implanted into the first interval of the substrate to form a first doping layer, including:

[0079] Step S301 : implanting first doping ions into a first depth interval in the substrate from the surface of the oxide layer along a first direction to form a first doping layer; wherein the first direction is from the first surface to the second surface of the substrate.

[0080] In other words, the ion implantation process can be performed through the oxide layer. During the ion implantation process, the first dopant ions can be implanted into the substrate from the surface of the oxide layer. The first dopant ions penetrate the oxide layer based on a certain energy and are implanted into the first depth range, thereby forming a first doped layer.

[0081] It is understood that the subsequent activation step of the first doped layer also requires performing a high-temperature activation step on the first doped layer within the first depth range within the substrate through the oxide layer. The oxide layer can also enhance the randomness of the direction of dopant ion implantation and suppress the channeling effect of ion implantation.

[0082] In some embodiments, before step S102, Figure 5 As shown, the above method also includes:

[0083] Step S401: performing ion implantation from the oxide layer into a third depth interval of the substrate along a first direction to form an ion implantation layer; the distance between the third depth interval and the first surface is greater than the distance between the first depth interval and the first surface;

[0084] After step S102 or step S301, the method further includes:

[0085] Step S402: using the ion implantation layer to remove a portion of the substrate between the ion implantation layer and the second surface;

[0086] Step S403: removing the ion implantation layer to expose the third surface of the substrate.

[0087] An oxide layer is formed on a first surface of the substrate, and the second surface of the substrate is opposite to the first surface. Here, the direction from the first surface to the second surface is defined as a first direction. Step S401 is performed to perform ion implantation from the oxide layer along the first direction into a third depth interval of the substrate to form an ion implantation layer. In some embodiments, the implanted ions may be hydrogen ions, which can form a bubble layer in the silicon wafer.

[0088] The distance from the third depth interval to the first surface is greater than the distance from the first doped layer to the first surface, that is, the first doped layer is not between the ion implantation layer and the second surface of the substrate.

[0089] In some embodiments, after executing step S102 or step S301, the following steps may be continued:

[0090] Step S402 is performed to remove a portion of the substrate between the ion implantation layer and the second surface using the ion implantation layer. For example, the substrate including the ion implantation layer (e.g., hydrogen ion layer) can be completely cleaved from the bubble layer (i.e., the ion implantation layer) by appropriate heat treatment to form a silicon-on-insulator structure.

[0091] Step S403 is performed to remove the ion implanted layer to expose the third surface of the substrate. The remaining cleaved ion implanted layer remaining on the substrate is removed. Removal methods include, but are not limited to, etching and chemical mechanical polishing (CMP) until the substrate is exposed. The exposed surface of the substrate is defined as the third surface, which is opposite to the first surface.

[0092] In some embodiments, as Figure 6 As shown, the above method also includes:

[0093] Step S501: providing a carrier wafer;

[0094] Step S502: Bonding the oxide layer to the carrier wafer.

[0095] In some embodiments, before executing step S402, the oxide layer on the first surface of the substrate may be fixed to a support structure. This support structure can ensure that when the portion of the substrate between the ion implantation layer and the second surface is removed, the structure between the ion implantation layer and the oxide layer will not be damaged. The support structure can be a carrier wafer, and the carrier wafer can be made of the same material as the substrate. For example, when the substrate is a silicon substrate, the carrier wafer can be a silicon wafer. The oxide layer on the first surface of the substrate can be connected to the carrier wafer by bonding.

[0096] In some embodiments, as Figure 7 As shown, the above method also includes:

[0097] Step S601 , flipping the carrier wafer and the substrate so that the second surface of the substrate faces vertically upward.

[0098] In some embodiments, the oxide layer has been bonded to the carrier wafer, and the carrier wafer is currently located on the uppermost layer. Because the portion of the substrate between the ion implantation layer and the second surface needs to be removed, step S601 may be performed to facilitate removal of this portion of the substrate.

[0099] In some embodiments, as Figure 8 As shown, the above method also includes:

[0100] Step S701: performing a planarization process on the third surface.

[0101] In some embodiments, the third surface of the substrate formed after step S403 may be uneven. In this case, step S701 may be performed to planarize the third surface of the thinned substrate to facilitate subsequent steps. Planarization methods include, but are not limited to, CMP.

[0102] In some embodiments, as Figure 9 As shown, in the above step S104, second doping ions are implanted into the second depth interval of the substrate to form a second doping layer, including:

[0103] Step S801 : implanting second doping ions into a second depth interval of the substrate from the third surface along a second direction to form a second doping layer; wherein the second direction is from the second surface to the first surface.

[0104] In some embodiments, the second doped layer may be formed by performing a second ion implantation from the third surface toward the first surface.

[0105] It is understood that the second doped layer can be formed by first ion implantation from the first surface or by ion implantation from the third surface. However, the implantation energy required for these two implantation methods is different. This is because, viewed from the first surface of the substrate in the first direction, the implantation depth of the second doped layer is greater than the implantation depth of the first doped layer. Viewed from the third surface in the second direction, the implantation depth of the second doped layer is less than the implantation depth of the first doped layer.

[0106] In some embodiments, after performing step S107 to form a plurality of storage capacitors, as shown in FIG. Figure 10 As shown, the above method also includes:

[0107] Step S901: removing the oxide layer.

[0108] In some embodiments, the oxide layer may be removed to expose the drain of the transistor channel pillar, and other structures, such as a bit line structure, may be subsequently formed on the exposed drain.

[0109] In some embodiments, before executing step S901, the surface of the above-mentioned storage capacitor can be fixed on another supporting structure. The support structure can ensure that the device structure formed on the oxide layer will not be destroyed when the oxide layer is removed. The supporting structure can be a second carrier wafer, and the second carrier wafer can use the same material as the substrate. For example, when the substrate is a silicon substrate, the second carrier wafer can be a silicon wafer. The surface of the storage capacitor can be connected to the second carrier wafer by bonding. Then flip the second carrier wafer and the substrate so that the first carrier wafer on the oxide layer is facing upward, and then remove the first carrier wafer and the oxide layer.

[0110] In some embodiments, after step S106 is performed, a plurality of parallel first trenches along a third direction are formed between the etched channel pillar arrays; the third direction is a direction parallel to the first surface of the substrate; Figure 11 As shown, the above method also includes:

[0111] Step S1001: forming a word line structure in a first trench.

[0112] In some embodiments, a wordline structure may be formed between two adjacent channel pillars. The wordline structure includes a gate insulating layer and a gate oxide layer. The wordline structure and the channel pillar may form a transistor. Two channel pillars may share a wordline structure to form a transistor, or one channel pillar may use a wordline structure to form a transistor. The wordline structure is formed at least within the first trench between the channel pillar arrays. The wordline structure may cover at least one sidewall of the channel pillar. The wordline structure may also be formed around the channel pillar, without limitation herein.

[0113] In some embodiments, before forming the word line structure in the first trench, as shown in FIG. Figure 12 As shown, the above method also includes:

[0114] Step S1101, filling a first dielectric material between the etched channel pillar arrays;

[0115] Step S1102 : forming a plurality of first trenches along the third direction in the first dielectric material.

[0116] In some embodiments, transistors or channel pillars can be separated by a first dielectric material to ensure electrical isolation between the transistors. Therefore, the trenches between the channel pillar arrays can be filled with the first dielectric material to form an insulating structure. The insulating structure is then etched to form the first trenches. The first dielectric material can be an insulating material, such as an oxide, nitride, or a combination thereof.

[0117] In some embodiments, as Figure 13 As shown, the above method also includes:

[0118] Step S1201: forming a conductive layer connecting a plurality of storage capacitors.

[0119] After forming the storage capacitor, a conductive layer may be formed on top of the storage capacitor. When using the DRAM formed by the method of the present disclosure, the conductive layer may be grounded. The conductive layer may be formed of a conductive material, such as tungsten, aluminum, copper, etc.

[0120] The conductive layer may include a plurality of metal lines, each of which may be used to connect a plurality of storage node contacts and to ground the storage capacitor or connect the storage capacitor to other circuit structures.

[0121] The present disclosure also provides a semiconductor device formed by the method described in any of the above embodiments. The semiconductor device involved in the present disclosure is at least a portion of a final device structure that will be used in subsequent processes. The final device may include a memory.

[0122] The present disclosure also includes the following examples:

[0123] First, step S101 is performed, and the Figure 14 The substrate 100 shown has a first surface S1 and a second surface S2 opposite to the first surface. The substrate may be a silicon substrate.

[0124] Then, step S201 is performed to form a substrate 100 on the first surface S1. Figure 15The oxide layer 200 is shown. In the embodiment of the present disclosure, the oxide layer 200 may be formed by implanting oxygen ions into the first surface S1 of the substrate 100 to oxidize the first surface S1 of the substrate, and then performing high-temperature annealing to form the oxide layer 200.

[0125] Then, step S401 is performed to perform ion implantation from the oxide layer 200 to the third depth range of the substrate along the first direction, that is, the direction from the first surface S1 to the second surface S2, to form a Figure 16 As shown in the ion implantation layer 300 , in the embodiment of the present disclosure, the ions implanted by the ion implantation may be hydrogen ions, and a hydrogen ion implantation layer is formed.

[0126] Then, step S102 is performed to implant first dopant ions from the oxide layer 200 into the first depth range of the substrate 100 along the first direction to form a Figure 17 The first doping layer 400 is shown. The first doping layer 400 is located below the oxide layer 200 and on the ion implantation layer 300 , with a portion of the substrate 100 between the first doping layer 400 and the hydrogen ion implantation layer 300 .

[0127] Then, step S501 is performed to provide a carrier wafer, which may be a silicon wafer.

[0128] Then, step S502 is performed to bond the oxide layer to the carrier wafer.

[0129] Then, step S601 is performed to flip the carrier wafer and the substrate so that the second surface of the substrate faces vertically upward. Figure 18 As shown, at this time, the second surface S2 of the substrate 100 is at the top layer, and the carrier wafer 500 is at the bottom layer.

[0130] Then, step S402 is performed to remove the portion of the substrate between the ion implantation layer and the second surface using the ion implantation layer. Figure 18 The semiconductor structure shown is subjected to low temperature annealing to form a micro bubble layer or micro cavity layer in the ion implantation layer 300, so that the carrier wafer 500 and the substrate 100 can be cleaved from the ion implantation layer 300, thereby removing a portion of the substrate 100 between the ion implantation layer 300 and the second surface S2, forming Figure 19 The semiconductor structure shown in FIG. The semiconductor structure comprises, from top to bottom, an ion implantation layer 300 , a substrate 100 , a first ion implantation layer 400 , an oxide layer 200 and a carrier wafer 500 .

[0131] Then, step S403 is performed to remove the ion implantation layer to expose the third surface of the substrate.

[0132] Then, step S103 is performed to activate the first doped layer at high temperature to form a drain layer. Activating the first doped layer at high temperature at an appropriate temperature and time can restore the mobility and other material parameters of the implanted first ions, so that the drain layer has the target mobility and other target material parameters.

[0133] Then, step S701 is executed to perform a planarization process on the third surface. The planarization process may be performed by CMP to form a planarized surface. Figure 20 The semiconductor structure shown in FIG. The semiconductor structure shown in FIG. 1 includes, from top to bottom, a substrate 100 , a drain layer 410 , an oxide layer 200 and a carrier wafer 500 .

[0134] Then, step S104 is performed to implant second doping ions into the second depth interval of the substrate to form a second doping layer 600; the second depth interval does not overlap with the first depth interval. In the embodiment of the present disclosure, the second doping ion implantation can be performed on the third surface after the planarization process to form a second doping layer 600. Figure 21 The second doping layer 600 is shown. The second doping layer 600 does not overlap with the drain layer 410 , and a portion of the substrate 100 is located between the second doping layer 600 and the drain layer 410 .

[0135] Then, step S105 is performed to activate the second doping layer at high temperature to form Figure 22 The source layer 610 is shown; high-temperature activation of the second doping layer at an appropriate temperature and time can restore the mobility and other material parameters of the implanted second ions, so that the source layer 610 has target mobility and other target material parameters.

[0136] Then, step S106 is performed, etching Figure 22 The source layer 610, the drain layer 410 and the substrate 100 between the source layer 610 and the drain layer 410 are shown in FIG. Among them, the oxide layer 200 can be used as an etching stop layer to form Figure 23 The channel pillar array shown includes a plurality of transistor channel pillars 700 ; the two ends of the transistor channel pillar 700 include a drain 411 and a source 611 respectively, and a channel 110 is provided between the drain 411 and the source 611 . There is a trench 701 between adjacent channel pillars 700 .

[0137] Then, step S1101 is performed to fill the trenches 701 between the etched channel pillar arrays with a first dielectric material. The first dielectric material may be an oxide, a nitride (eg, silicon nitride), or other insulating materials. Figure 24 The insulating structure 702 shown covers the sidewalls of adjacent transistors and the bottom of the trench between adjacent transistors. The insulating structure 702 can be used to electrically isolate adjacent channel pillars 700 .

[0138] Then, step S1102 is performed to form a plurality of first trenches along the third direction in the first dielectric material. The third direction can be any direction parallel to the third surface of the substrate. The portion between the channel pillar arrays not filled with the first dielectric material forms the first trench. The insulating structure 702 is etched along the third direction to form a first trench. Figure 25 The first trench 703 is shown.

[0139] Then, step S1001 is performed to form a wordline structure in the first trench. The wordline structure includes a gate insulating layer and a gate conductive layer. The gate insulating layer can be formed of an insulating material such as an oxide, silicide, or a combination thereof. The gate conductive layer can be formed of a conductive material such as tungsten metal, polysilicon, or the like.

[0140] like Figure 26 As shown, a gate insulating layer 704 and a gate conductive layer 705 can be formed in the first trench through a deposition process, which together constitute a word line structure 706. The projection of the word line structure 706 in the Z direction can overlap with a portion of the source 611 and a portion of the drain 411. Therefore, the bottom height of the word line structure 706 can be lower than the upper surface of the drain 411 in the Z direction, and the top height of the word line structure 706 can be higher than the lower surface of the source 611 in the Z direction. The recessed structure above the word line structure 706 can further be filled with an insulating material to form an insulating layer. The upper surface of the insulating layer can be flush with the third surface S3. The insulating material can be the same as or different from the first dielectric material. Figure 26 The shape and position of the word line structure 706 in FIG. 7 is only an example. In some embodiments, the word line structure may be shared by two adjacent transistors, and the shape of the word line structure may surround one or more sidewalls of the transistor.

[0141] Then, step S107 is executed to form Figure 27 As shown, multiple storage capacitors 800 are not connected to each other on the source 611 of multiple channel pillars in the channel pillar array. A second dielectric layer of the same material as the first dielectric layer can be filled between adjacent storage capacitors 800. For example, the material of the second dielectric layer can be nitride (for example, silicon nitride). The storage capacitor 800 can be made of high-k material. A first storage node contact 803 can be included between the storage capacitor 800 and the source 611 and / or a second storage node contact 801 can be included above the storage capacitor 800. Figure 27 As shown, the left side of the dotted line AA' is the memory cell array region, and each memory cell may include a transistor and a storage capacitor 800. The right side of the dotted line AA' is the peripheral circuit region of the memory cell array.

[0142] Then, step S1201 is executed to form Figure 28The conductive layer 900 shown is connected to the plurality of storage capacitors 800, and a second storage node contact 801 may be provided between the conductive layer 900 and the storage capacitors 800. The conductive layer 900 may electrically connect the memory cell array and the peripheral circuitry of the memory cell array. The conductive layer 900 may be formed of a metal material, such as tungsten, aluminum, copper, etc. A third dielectric layer of the same material as the first dielectric layer may also be provided above the conductive layer 900. The material of the third dielectric layer may be a nitride (e.g., silicon nitride).

[0143] In the embodiment of the present disclosure, before executing step S901, the surface of the third dielectric layer can be fixed on another supporting structure. The support structure can ensure that the memory cell array and peripheral circuit parts formed on the oxide layer will not be damaged when the oxide layer is removed. The supporting structure can be a second carrier wafer, and the second carrier wafer can use the same material as the substrate. For example, when the substrate is a silicon substrate, the second carrier wafer can be a silicon wafer. The surface of the third dielectric layer can be connected to the second carrier wafer by bonding. Then flip the second carrier wafer and the substrate, as shown in FIG. Figure 29 As shown, the first carrier wafer 500 on the oxide layer 200 faces upward, and the second carrier wafer 502 is located at the bottom. Then, step S901 is performed to remove the oxide layer 200.

[0144] The first carrier wafer 500 and the oxide layer 200 can be removed to obtain Figure 30 A bit line structure may be further formed on the drain 411 of the semiconductor structure, which will not be described in detail here.

[0145] In the semiconductor device formed using the method of the embodiment of the present disclosure, high-temperature activation of the source and drain terminals is completed before the storage capacitor is formed. Therefore, the high-temperature activation step is no longer required after the storage capacitor is formed. This avoids the loss caused by the degradation and decomposition of the dielectric composed of high-k dielectric material in the storage capacitor, thereby ensuring the performance of the storage capacitor and even the semiconductor device.

[0146] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0147] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0148] The above description is merely an embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for forming a semiconductor device, characterized in that: The method comprises: Providing a substrate; the substrate having a first surface and a second surface; Implanting first doping ions into a first depth interval of the substrate to form a first doping layer; activating the first doped layer at high temperature to form a drain layer; implanting second doping ions into a second depth interval of the substrate to form a second doping layer; wherein the second depth interval does not overlap with the first depth interval; activating the second doped layer at a high temperature to form a source layer; Etching the source layer, the drain layer, and the substrate between the source layer and the drain layer to form a channel pillar array; the channel pillar array includes a plurality of transistor channel pillars; both ends of the transistor channel pillar include a source and a drain respectively; A plurality of storage capacitors that are not connected to each other are formed on the sources of the plurality of channel pillars in the channel pillar array.

2. The method according to claim 1, characterized in that The method further comprises: An oxide layer is formed on the first surface of the substrate; the oxide layer is used as an etching stop layer for etching the source layer, the drain layer, and the substrate between the source layer and the drain layer.

3. The method according to claim 2, characterized in that The step of forming an oxide layer on the first surface of the substrate is before the step of forming the first doping layer; The step of implanting first doping ions into the first region of the substrate to form a first doping layer includes: The first doping ions are implanted from the surface of the oxide layer along a first direction into a first depth range in the substrate to form the first doping layer; wherein the first direction is from the first surface to the second surface of the substrate.

4. The method according to claim 2, characterized in that Before the step of forming the first doping layer, the method further includes: Performing ion implantation from the oxide layer into a third depth interval of the substrate along a first direction to form an ion implantation layer; the distance between the third depth interval and the first surface is greater than the distance between the first depth interval and the first surface; After the step of forming the first doping layer, the method further includes: removing a portion of the substrate between the ion implantation layer and the second surface using the ion implantation layer; The ion implantation layer is removed to expose the third surface of the substrate.

5. The method according to claim 4, characterized in that The method further comprises: Provide carrier wafers; The oxide layer is bonded to the carrier wafer.

6. The method according to claim 5, characterized in that The method further comprises: The carrier wafer and the substrate are turned over so that the third surface of the substrate faces vertically upward.

7. The method according to claim 4, characterized in that The method further comprises: The third surface is planarized.

8. The method according to claim 4, characterized in that The step of implanting second doping ions into the second depth interval of the substrate to form a second doping layer includes: The second doping ions are implanted from the third surface into a second depth range of the substrate along a second direction to form the second doping layer; wherein the second direction is from the third surface to the first surface.

9. The method according to claim 2, characterized in that After forming the plurality of storage capacitors, the method further includes: The oxide layer is removed.

10. The method according to claim 1, characterized in that After etching, a plurality of parallel first trenches are formed between the channel pillar arrays along the third direction; The third direction is a direction parallel to the first surface of the substrate; The method further comprises: A word line structure is formed in the first trench.

11. The method according to claim 10, characterized in that Before forming the word line structure in the first trench, the method further includes: Filling a first dielectric material between the etched channel pillar arrays; A plurality of first trenches are formed in the first dielectric material along the third direction.

12. The method according to claim 1, characterized in that The method further comprises: A conductive layer connecting the plurality of storage capacitors is formed.

13. A semiconductor device, characterized in that: The semiconductor device is formed by the method according to any one of claims 1 to 12.

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