A semiconductor device

Abstract

The present invention discloses a semiconductor device, comprising: a substrate, comprising a substrate layer on which a gate structure and an active structure are arranged; a first dielectric layer located above the substrate; a connecting member, wherein the connecting member is a conductive member, the connecting member continuously and directly penetrates the first dielectric layer and connects the gate structure and / or the active structure; and a metal layer, wherein the gate structure and / or the active structure that need to be connected to the metal layer are connected to the metal layer via the connecting member. The present invention greatly reduces the problem of misalignment, and the method for preparing the device of the present invention can also reduce the use of a large number of masks and save the middle process in the traditional method, shortening the process flow and greatly reducing the production cycle.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor device. Background Art

[0002] With the miniaturization and high integration of semiconductor devices, problems such as small processing windows, control of critical dimension uniformity (CDU), control of overlap deviation (OVL), and the use of too many masks have gradually become bottlenecks in mass production.

[0003] In the prior art, the connection structure of semiconductor devices generally involves connecting the substrate layer to the metal layer above it via a contact structure, and forming a connection between the substrate and the metal layer via a conductive structure. In particular, in high-volume semiconductor manufacturing, the structural design involved includes metal conductors (MD) connecting the active area, metal conductors (MP) connecting the gate area, via-contact connections (VC), and spacers (CMD).

[0004] refer to Figure 1 Specifically, existing semiconductor devices include:

[0005] A substrate, which specifically includes: a substrate layer 11', a barrier layer 14', a dielectric layer 15', and a termination layer 16'. An active structure 12' and a gate structure 13' are provided on the substrate layer 11'. The barrier layer 14' abuts against the sidewalls of the gate structure 13' and covers the upper surface of the substrate layer 11' located between the gate structures 13' and the upper surface of the active structure 12'. The barrier layer 14' is flush with the gate structures 13' and is recessed inward to form a groove located between the gate structures 13'. The dielectric layer 15' fills the groove and is flush with the gate structures 13'. The termination layer 16' covers the gate structure 13', the barrier layer 14', and the dielectric layer 15'.

[0006] a dielectric layer 21' formed on the termination layer 16';

[0007] a stop layer 212' formed on the dielectric layer 21';

[0008] a dielectric layer 22' formed on the stop layer 212';

[0009] A metal layer 4' is formed on the dielectric layer 22';

[0010] The contact member 3' and the conducting member 5' are used to achieve communication between the gate structure 13' or the active structure 12' and the metal layer 4'. The conducting member 5' penetrates the dielectric layer 22' and the stop layer 4' and then communicates with the contact member 3'. There are three types of contact members 3'. One type connects the gate structure 13' and the conductive member 5'. This type of contact member 3' penetrates the dielectric layer 21' and the termination layer 16' and then abuts against the gate structure 13'. The second type of contact member 3' connects the active structure 12' and the conductive member 5'. This type of contact member 3' penetrates the dielectric layer 21', the termination layer 16', the dielectric layer 15', and the barrier layer 14' and then abuts against the active structure 12'. The third type is an adjacent structure that simultaneously realizes the connection between the gate structure 13', the active structure 12' and the conductive member 5'. This type of contact member penetrates the dielectric layer 21' and the termination layer 16', with part of it directly contacting the gate structure 13', and the other part continuing to penetrate the dielectric layer 15' and the barrier layer 14' and then contacting the active structure 12'.

[0011] A drawback of the aforementioned device is that the contact member 3' and the conductive member 5' are prone to offset or misalignment. This offset problem is becoming increasingly serious as technology advances towards miniaturization. This misalignment can lead to deviations and poor uniformity in the critical dimensions of the resulting device and also cause significant parasitic capacitance. Summary of the Invention

[0012] The technical problem to be solved by the present invention is to provide a semiconductor device in view of the above-mentioned defect in the prior art that contact components and conducting components are easily offset or misaligned.

[0013] The technical solution adopted by the present invention to solve the technical problem is to construct a semiconductor device, including:

[0014] A substrate, comprising a substrate layer on which a gate structure and an active structure are arranged;

[0015] a first dielectric layer located above the substrate;

[0016] A connecting member, wherein the connecting member is a conductive member, the connecting member continuously and directly penetrates the first dielectric layer and connects the gate structure and / or the active structure;

[0017] The metal layer, the gate structure and / or active structure that need to be connected to the metal layer realizes the connection of the metal layer via the connecting member.

[0018] Preferably, the gate structure and active structure in the semiconductor device that need to be connected to the metal layer are connected to the metal layer through the corresponding connecting members;

[0019] Alternatively, the semiconductor device further includes a contact member penetrating the lower interlayer dielectric layer and a conductive member penetrating the upper interlayer dielectric layer, and some gate structures or / and active structures that need to be connected to the metal layer are connected to the metal layer through the corresponding connecting members, and some gate structures or / and active structures that need to be connected to the metal layer are connected to the metal layer through the contact member and the conductive member.

[0020] Preferably, the substrate further comprises:

[0021] a barrier layer abutting against sidewalls of the gate structures and covering an upper surface of a portion of the substrate layer located between the gate structures and an upper surface of the active structure, wherein the barrier layer is flush with the gate structures and is recessed inwardly to form a groove located between the gate structures;

[0022] a second dielectric layer filling the groove and being flush with the height of the gate structure;

[0023] a termination layer covering the gate structure, the barrier layer, and the dielectric layer;

[0024] Among them: the connecting component connected to the gate structure penetrates the first dielectric layer and the termination layer and then contacts the gate structure; the connecting component connected to the active structure penetrates the first dielectric layer, the termination layer, the dielectric layer, and the barrier layer and then contacts the active structure.

[0025] Preferably, the first dielectric layer includes a lower interlayer dielectric layer disposed on the substrate and an upper interlayer dielectric layer disposed on the lower interlayer dielectric layer, and a material K value of the upper interlayer dielectric layer is lower than a material K value of the lower interlayer dielectric layer.

[0026] Preferably, the peripheral wall of the connecting member is inclined, and the angle between the peripheral wall of the connecting member and the horizontal plane of the base is 65° to 90°.

[0027] Preferably, the coupling member is a separate coupling piece, or the coupling member consists of a coupling piece and a cushion layer covering a bottom and all / part of a side wall of the coupling piece.

[0028] Preferably, the connecting member is at least two layers of connecting structures stacked along the depth direction of the first dielectric layer, the bottom layer of the connecting structure abuts the gate structure and / or the active structure, and the top layer of the connecting structure abuts the metal layer. The at least two layers of connecting structures are formed by filling in batches in the openings opened along the depth direction of the first dielectric layer after the first dielectric layer is formed.

[0029] Preferably, the coupling structure is a separate coupling member, or is composed of a coupling member and a lining layer covering the bottom and all / part of the side walls of the coupling member.

[0030] Preferably, the connecting member is made of tungsten, copper, cobalt, rubidium, molybdenum, or an alloy of the above components.

[0031] Preferably, the material of the liner layer is at least one of a single metal, a metal alloy, a metal nitride, and a metal silicide, and the metal is selected from at least one of titanium, copper, and manganese.

[0032] The semiconductor device of the present invention has the following beneficial effects: a separate connecting member is designed in the present invention, which continuously and directly penetrates the first dielectric layer and then connects to the gate structure and / or the active structure. A single connecting member is used to connect the metal layer with the gate structure and the active structure, greatly reducing the problem of misalignment. In addition, the method for preparing the device of the present invention can also reduce the use of a large number of masks and save the middle-of-line (MEOL) process in traditional methods, shortening the process flow and greatly reducing the production cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only embodiments of the present invention. Those skilled in the art can also derive other drawings based on the provided drawings without inventive work.

[0034] Figure 1 is a cross-sectional view of a conventional semiconductor device;

[0035] Figure 2 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention;

[0036] Figure 3 It is a second structural diagram of the connecting member;

[0037] Figure 4 It is a third structural diagram of the connecting component;

[0038] Figure 5 It is a fourth structural diagram of the connecting member;

[0039] Figure 6 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0040] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. The drawings illustrate exemplary embodiments of the present invention. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present invention.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. It should be noted that the terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only.

[0042] As used in this specification, terms containing ordinal numbers such as "first" and "second" may be used to describe various components, but these components are not limited by these terms. The purpose of using these terms is only to distinguish one component from other components. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. The term "and / or" as used herein includes any and all combinations of one or more of the relevant listed items.

[0043] The overall concept of the present invention is to design a separate connecting member that continuously and directly penetrates the first dielectric layer and then connects to the gate structure and / or the active structure. A single connecting member is used to connect the metal layer with the gate structure and the active structure, greatly reducing the problem of misalignment. In addition, the method for preparing the device of the present invention can also reduce the use of a large number of masks and save the middle-of-line (MEOL) process in traditional methods, shortening the process flow and greatly reducing the production cycle.

[0044] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the drawings and specific implementation methods of the specification. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present application, rather than limitations on the technical solution of the present application. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0045] Example 1

[0046] refer to Figure 2 The semiconductor device of the first embodiment includes: a substrate, a first dielectric layer, a connecting member 3, a stop layer 4, and a metal layer 41. The substrate serves as the first layer structure, the first dielectric layer serves as the second layer structure, and the stop layer 4 and metal layer 41 serve as the third layer structure. The connecting member 3 is a conductive member that penetrates the second layer structure to connect the structures that need to be connected between the first layer structure and the third layer structure.

[0047] The substrate in this embodiment includes a substrate layer 11 , a barrier layer 14 , a second dielectric layer 15 and a termination layer 16 .

[0048] A gate structure 13 and an active structure 12 are provided on the substrate layer 11. The active structure 12 includes source and drain structures. The present invention primarily improves the connection between the gate structure 13 and the active structure 12 in the first layer and the metal layer 41 in the third layer. The gate structure 13 and the active structure 12 are common knowledge in the art and will not be further described here.

[0049] The barrier layer 14 abuts the sidewalls of the gate structure 13 and covers the upper surface of the portion of the substrate layer 11 located between the gate structures 13 and the upper surface of the active structure 12. The barrier layer 14 is flush with the gate structure 13 and is recessed inward to form a groove located between the gate structures 13.

[0050] The dielectric layer fills the groove of the barrier layer 14 and is flush with the gate structure 13 .

[0051] The termination layer 16 covers the gate structure 13 , the barrier layer 14 , and the second dielectric layer 15 .

[0052] The first dielectric layer is composed of a lower interlayer dielectric layer 21 and an upper interlayer dielectric layer 22. The lower interlayer dielectric layer 21 covers the upper surface of the substrate termination layer 16, and the upper interlayer dielectric layer 22 covers the upper surface of the lower interlayer dielectric layer 21. The lower interlayer dielectric layer 21 is made of a low-K dielectric material. The upper interlayer dielectric layer 22 is made of an extremely low-K (ELK) dielectric material, such as a dielectric material with a K value (i.e., a dielectric constant) less than 2.9.

[0053] The connecting member 3 directly and continuously penetrates the first dielectric layer and connects the gate structure 13 and / or the active structure 12. The connecting member 3 connected to the gate structure 13 penetrates the first dielectric layer and the termination layer 16 and then contacts the gate structure 13. The connecting member 3 connected to the active structure 12 penetrates the first dielectric layer, the termination layer 16, the second dielectric layer 15, and the barrier layer 14 and then contacts the active structure 12. It is understood that the connecting member 3 can also connect the gate structure 13 and the active structure 12 at the same time. This structure is an adjacent structure, for example Figure 2 In the figure, the gate structure 13 and the active structure 12 on the left are connected to the metal layer 41 through independent connecting members 3, respectively, while the gate structure 13 and the active structure 12 on the right are connected to the metal layer 41 through the same connecting member 3. The connecting member 3 on the right realizes the function of the adjacent structure.

[0054] The so-called continuous and direct penetration means that the connecting member 3 is an integral whole. In the prior art, a contact member and a conductive member are used to abut each other, with the conductive member connected to the metal layer and the contact member connected to the active structure or gate structure. In the present invention, there is only one connecting member 3 between the metal layer and the source structure or gate structure. Accordingly, when making the connecting member 3, the opening is opened once. In the prior art, the openings of the contact member and the conductive member are opened in steps, while in the present invention, after forming the upper interlayer dielectric layer 22 and the lower interlayer dielectric layer 21, the opening can be opened in one step, without the need for opening in batches. In addition, it should be noted that in the prior art, because the contact member and the conductive member are formed in two steps, the corresponding dielectric layer in the prior art must be formed in two steps. Although the dielectric layer in the present invention is formed in two steps in this embodiment, it is actually also possible to use a dielectric layer formed in one step.

[0055] Specifically, the connecting member 3 can be formed by etching a groove in the first dielectric layer and then filling it with material. The radial dimension of the connecting member 3 gradually increases from bottom to top. Accordingly, the peripheral wall of the connecting member 3 forms an acute angle with the horizontal plane of the substrate. For example, in this embodiment, the angle between the peripheral wall of the connecting member 3 and the horizontal plane of the substrate is 65° to 90°. In the prior art, the peripheral wall of the contact member forms a rounded corner or chamfer with the bottom surface of the metal layer 41. However, in the present invention, the connecting member 3 forms a turning angle with the bottom surface of the metal layer 41.

[0056] In this embodiment, the connecting member 3 is composed of a connecting piece 32 and a liner layer 31 covering the bottom and sidewalls of the connecting piece 32. The material of the connecting piece 32 is tungsten, copper, cobalt, rubidium, molybdenum, or an alloy of the above components. The material of the liner layer 31 is at least one of a metal element, a metal alloy, a metal nitride, and a metal silicide, such as titanium, titanium nitride, and a copper-manganese compound. It can also be selectively grown into a metal silicide, such as a titanium silicon compound and a manganese silicon compound, based on the silicon material in the dielectric layer. For example, after the first dielectric layer is formed, an opening can be opened along the depth direction of the first dielectric layer, and then titanium can be deposited on the inner wall (bottom and sidewall) of the opening. Titanium is then formed into a titanium silicon compound (i.e., a liner layer) under high temperature conditions with the silicon in the first dielectric layer to reduce the resistance value in the device, and then filled with metal material to form a connecting piece.

[0057] Figure 2 The lining layer 31 covers the bottom and the entire side wall of the coupling 32. Figure 3 In other embodiments, only the bottom and sidewalls of the connector 32 may be partially covered. The liner layer 31 serves to act as an adhesive, improving the bonding strength between the connector 32 and the dielectric layer, while preventing or slowing down the diffusion of elements in the connector 32.

[0058] It should be noted that, in other embodiments, the connecting member 3 can also be a separate connecting piece, that is, the entire connecting piece is exposed without a lining layer, such as Figure 4 For example, after the first dielectric layer is formed, an opening can be opened along the depth direction of the first dielectric layer, and then a metal material can be directly deposited in the opening and planarized.

[0059] Considering that during the production process of the connecting member 3, it is necessary to open a hole in the depth direction of the first dielectric layer through the entire first dielectric layer, the depth of the hole is relatively deep, and it is easy to cause problems such as filling gaps when filling the metal material in the later stage. For this reason, reference is made to Figure 5 The connecting member 3 can be optimized and split into a multi-layer connecting structure, that is, the connecting member 3 is a connecting structure of at least two layers stacked along the depth direction of the first dielectric layer. Figure 5 Only three layers are shown. The bottommost layer of the connection structure abuts the gate structure 13 and / or the active structure 12, and the topmost layer of the connection structure abuts the metal layer 41. These at least two layers of connection structures are formed by filling the openings opened along the depth direction of the first dielectric layer after the first dielectric layer is formed. For example, after the first dielectric layer is formed, an opening can be opened along the depth direction of the first dielectric layer, and then the bottom layer of the connection structure is first formed in the opening. Specifically, a liner layer with a groove is deposited along the bottom and sidewalls of the opening by atomic layer deposition, and a dummy part is filled in the groove. Then, the initial liner layer and the dummy part are etched to the required height to form the liner layer of the bottom layer of the connection structure. The dummy part is then removed, and metal material is filled in the opening and above the bottom layer of the liner layer. The metal material is etched to the required height to form the bottom layer of the connection structure. Then, the second layer of the connection structure is formed based on the same steps, and so on. For the top layer of the connection structure, there is a slight change. Specifically, the materials of the liner layer and the connection part are deposited in sequence in the opening with the intermediate connection structure and on the surface of the upper interlayer dielectric layer 22. The excess material is removed by chemical mechanical planarization to expose the surface of the upper interlayer dielectric layer 22 and form the top layer of the connection structure in the opening.

[0060] This embodiment adopts a multi-layer connection structure, which can avoid problems such as filling gaps caused by an excessively large opening depth-to-width ratio and improve filling quality.

[0061] Among them, the stop layer 4 and the metal layer 41 are formed above the upper interlayer dielectric layer 22 and the connecting member 3. The metal layer 41 is distributed in the stop layer 4 and runs through the stop layer 4 and is connected to the connecting member 3. The gate structure 13 and / or the active structure 12 that need to be connected to the metal layer 41 are connected to the metal layer 41 via the connecting member 3. When manufacturing the semiconductor device of this embodiment, a first dielectric layer is first formed on the substrate, and then the connecting member 3 is manufactured. Thereafter, a continuous stop layer 4 is formed above the first dielectric layer and the connecting member 3. The stop layer 4 is then etched to form a trench. The trench is filled with metal material and planarized to form the metal layer 41. In other words, the metal layer 41 can be understood as a conductive pattern in the stop layer 4.

[0062] A feasible manufacturing method of the first embodiment may be:

[0063] S101: Provide a substrate.

[0064] S102 : depositing a first dielectric layer on the substrate. Specifically, depositing a lower interlayer dielectric layer 21 on the substrate, and depositing an upper interlayer dielectric layer 22 on the lower interlayer dielectric layer 21 .

[0065] S103: forming a connecting member 3, including: opening through the first dielectric layer for exposing the gate structure 13 and / or the active structure 12, depositing a conductive material in the opening and planarizing the opening to form a connecting member 3 connecting the gate structure 13 and / or the active structure 12.

[0066] Preferably, before depositing conductive material in the opening to fill the opening, a layer of conductive material is first deposited on the entire bottom surface and part / the entire side surface of the opening to form a lining layer 31, and then conductive material is deposited in the opening until the entire opening is filled to form a connecting member 32. The lining layer 31 and the connecting member 32 together constitute the connecting component 3.

[0067] Preferably, when forming the connecting member 3, the openings opened along the depth direction of the first dielectric layer are filled in batches to form at least two layers of connecting structures stacked along the depth direction of the first dielectric layer. The batch filling specifically includes:

[0068] The non-top connection structure forming step includes: depositing a preliminary liner layer having a groove along the bottom and sidewalls of the opening by atomic layer deposition, and filling the groove with a dummy part; etching the preliminary liner layer and the dummy part to a desired height; removing the dummy part to expose the groove, and filling the groove with a metal material; etching the metal material to a desired height to obtain a layer of connection structure; if a non-top connection structure is to be formed next, the non-top connection structure forming step is performed again; otherwise, the top connection structure forming step is performed as follows:

[0069] The step of forming a top connection structure is as follows: depositing the materials of the liner layer and the connection member in sequence in the opening provided with the connection structure and on the surface of the first dielectric layer, and then removing the excess material by planarization to expose the surface of the first dielectric layer and form the topmost connection structure in the opening.

[0070] S104 , forming a continuous stop layer 4 on the upper interlayer dielectric layer 22 and the connecting member 3 .

[0071] S105. Etch a groove penetrating the stop layer 4 in the continuous stop layer 4 by photolithography to form a patterned stop layer 4; deposit a continuous metal in and above the groove of the patterned stop layer 4, and expose the patterned stop layer by planarization to form a patterned metal layer 41.

[0072] It is understood that not all coupling members 3 and conductive members need to be connected to the metal layer 41. The specific pattern of the metal layer 41 can be designed based on the positions of the coupling members 3 and conductive members that need to be connected to the metal layer 41. In addition, the pattern of the metal layer 41 can be divided into multiple independent sub-patterns, each of which is connected to a different coupling member 3 or conductive member.

[0073] Example 2

[0074] In the above-mentioned embodiment 1, the connecting member 3 is applied to the connection between the gate structure 13 and the metal layer 41, and the connection between the active structure 12 and the metal layer 41. It is understandable that the connecting member 3 involved does not necessarily need to be applied to the connection between the gate structure 13 and the active structure 12 at the same time. It can be applied to only the connection between one of the gate structure 13 and the active structure 12 and the metal layer 41, and the other maintains the original connection scheme of the contact member and the conductive member, which is specifically designed according to the device requirements. Therefore, in other embodiments, the gate structure 13 and the active structure 12 in the semiconductor device that need to be connected to the metal layer 41 can be partially connected to the metal layer 41 through the corresponding connecting member 3, and partially connected to the metal layer 41 through the contact member and the conductive member.

[0075] refer to Figure 6 The second embodiment illustrates a scheme in which the gate structure 13 adopts a connecting member 3 while retaining a contact member connected to the active structure 12. The contact member passes through the lower interlayer dielectric layer 21, and the conductive member passes through the upper interlayer dielectric layer 22. The contact member and the conductive member are in contact with each other.

[0076] The specific manufacturing method of the second embodiment can be:

[0077] S201: Provide a substrate.

[0078] S202: forming a lower interlayer dielectric layer 21 by deposition on the substrate.

[0079] S203: forming a contact member of the active structure 12, specifically comprising: opening an opening penetrating the lower interlayer dielectric layer 21, the termination layer 16, the second dielectric layer 15, and the barrier layer 14 to expose a predetermined area of the active structure 12, and depositing a conductive material in the opening to form a contact member.

[0080] S204 : forming an upper interlayer dielectric layer 22 by deposition on the lower interlayer dielectric layer 21 .

[0081] S205 : forming a conductive member of the active structure 12 . Specifically, a cavity is formed above the contact member through the upper interlayer dielectric layer 22 , and the cavity is filled to form a conductive member connected to the contact member.

[0082] S206: forming a connecting member 3 of the gate structure 13, specifically comprising: opening an opening penetrating the first dielectric layer and the termination layer 16 to expose a predetermined area of the gate structure 13, depositing a conductive material in the opening and planarizing the opening to form a connecting member 3 connecting the gate structure 13.

[0083] S207 : forming a continuous stop layer 4 on the upper interlayer dielectric layer 22 , the connecting member 3 , and the conductive member.

[0084] S208 : etching the stop layer 4 and filling the stop layer 4 to form a metal layer 41 that penetrates the stop layer 4 and communicates with the connection member 3 and the conductive member.

[0085] It can be understood that the specific manufacturing process of the contact component and the conductive component can also refer to the manufacturing process of the connecting component 3 of this embodiment.

[0086] In summary, the semiconductor device of the present invention has the following beneficial effects: a separate connecting member is designed in the present invention, which directly penetrates the first dielectric layer and then connects to the gate structure and / or the active structure. A single connecting member is used to connect the metal layer with the gate structure and the active structure, and there is no misalignment problem. In addition, the method for preparing the device of the present invention can also reduce the use of a large number of masks and save the middle-of-line (MEOL) process in the traditional method, shortening the process flow and greatly reducing the production cycle.

[0087] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. A semiconductor device, characterized in that: include: A substrate, comprising a substrate layer on which a gate structure and an active structure are arranged, wherein the active structure comprises a source electrode and a drain electrode structure; a first dielectric layer located above the substrate; A connecting member, wherein the connecting member is a conductive member, the connecting member continuously and directly penetrates the first dielectric layer and connects the gate structure and / or the active structure; A metal layer, wherein the gate structure and / or active structure that need to be connected to the metal layer realizes the connection of the metal layer via the connecting member; The radial dimension of the connecting member gradually increases from bottom to top, the peripheral wall of the connecting member is inclined, and the angle between the peripheral wall of the connecting member and the horizontal plane of the base is 65° to 90°; The connecting member is a connecting structure of at least three layers stacked along the depth direction of the first dielectric layer, wherein the bottommost connecting structure abuts against the gate structure and / or the active structure, and the topmost connecting structure abuts against the metal layer, and the at least three connecting structures are formed by filling in batches in an opening opened along the depth direction of the first dielectric layer after the first dielectric layer is formed; When forming the connecting member, the openings opened along the depth direction of the first dielectric layer are filled in batches to form at least three layers of connecting structures stacked along the depth direction of the first dielectric layer. The filling in batches specifically includes: The non-top connection structure forming step comprises: depositing a preliminary liner layer having a groove along the bottom and sidewalls of the opening by atomic layer deposition, and filling the groove with a dummy part; etching the preliminary liner layer and the dummy part to a desired height; removing the dummy part to expose the groove, and filling the groove with a metal material; etching the metal material to a desired height to obtain a layer of connection structure; if a non-top connection structure is to be formed next, performing the non-top connection structure forming step again; otherwise, performing the following top connection structure forming step: depositing a liner layer and connection part materials in sequence in the opening provided with the connection structure and on the surface of the first dielectric layer, and removing excess material by planarization to expose the surface of the first dielectric layer and form a top connection structure layer in the opening; The first dielectric layer includes a lower interlayer dielectric layer provided on the substrate and an upper interlayer dielectric layer provided on the lower interlayer dielectric layer, wherein the K value of the material of the upper interlayer dielectric layer is lower than the K value of the material of the lower interlayer dielectric layer; The semiconductor device further comprises a contact member penetrating the lower interlayer dielectric layer and a conducting member penetrating the upper interlayer dielectric layer, wherein some gate structures or / and active structures that need to be connected to the metal layer are connected to the metal layer via the corresponding connecting members, and some gate structures or / and active structures that need to be connected to the metal layer are connected to the metal layer via the contact member and the conducting member; A side surface of the conductive member contacts a side surface of the contact member.

2. The semiconductor device according to claim 1, wherein The substrate further comprises: a barrier layer abutting against sidewalls of the gate structures and covering an upper surface of a portion of the substrate layer located between the gate structures and an upper surface of the active structure, wherein the barrier layer is flush with the gate structures and is recessed inwardly to form a groove located between the gate structures; a second dielectric layer filling the groove and being flush with the height of the gate structure; a termination layer covering the gate structure, the barrier layer, and the dielectric layer; Among them: the connecting component connected to the gate structure penetrates the first dielectric layer and the termination layer and then contacts the gate structure; the connecting component connected to the active structure penetrates the first dielectric layer, the termination layer, the dielectric layer, and the barrier layer and then contacts the active structure.

3. The semiconductor device according to claim 1, wherein The connecting structure consists of a connecting piece and a lining layer covering the bottom and all side walls of the connecting piece.

4. The semiconductor device according to claim 3, wherein The material of the connecting piece is tungsten, copper, cobalt, rubidium, molybdenum, or an alloy of the above components.

5. The semiconductor device according to claim 3, wherein The material of the liner layer is at least one of a metal element, a metal alloy, a metal nitride, and a metal silicide, and the metal is selected from at least one of titanium, copper, and manganese.

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