Memory cell, array thereof and preparation method

Abstract

The present invention discloses a memory cell, an array thereof, and a preparation method thereof. The memory cell comprises: a plurality of transistors provided with active structures and gate structures; a plurality of mutually separated regional metal layers located at the same height above the plurality of transistors; a plurality of conductive plugs connecting the transistors and the regional metal layers, wherein some or all of the conductive plugs use a continuous connecting member to achieve electrical connection between the gate structure and / or the active structure and the corresponding regional metal layers. The present invention uses a single connecting member, saving the misalignment area of traditional contact members and conductive members. Furthermore, in an 8-transistor memory cell, four transistors share a third gate structure as a transistor gate structure and form a connection, and a sixth contact member is connected to the active structure region shared by three pairs of transistors (T2 and T6, T3 and T7, and T4 and T8). The sixth contact member can serve as a data node to achieve data transmission between the six transistors.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a memory cell, an array thereof, and a preparation method thereof. Background Art

[0002] With the miniaturization and high integration of semiconductor devices, problems such as small processing windows, control of critical dimension uniformity (CDU), control of overlap deviation (OVL), and the use of too many masks have gradually become bottlenecks in mass production.

[0003] In the prior art, the connection structure of semiconductor devices generally involves connecting the substrate layer to the metal layer above it via a contact structure, and forming a connection between the substrate and the metal layer via a conductive structure. In particular, in high-volume semiconductor manufacturing, the structural design involved includes metal conductors (MD) connecting the active area, metal conductors (MP) connecting the gate area, via-contact connections (VC), and spacers (CMD).

[0004] The general storage structure is divided into a multi-layer structure in the thickness direction. The multi-layer structure is divided into a plurality of storage units arranged in an array, and any two adjacent storage units are mirrored about the adjacent surface. Figure 1 , each storage unit includes:

[0005] A substrate, which specifically includes: a substrate layer 11', a barrier layer 14', a dielectric layer 15', and a termination layer 16'. An active structure 12' and a gate structure 13' are provided on the substrate layer 11'. The barrier layer 14' abuts against the sidewalls of the gate structure 13' and covers the upper surface of the substrate layer 11' located between the gate structures 13' and the upper surface of the active structure 12'. The barrier layer 14' is flush with the gate structures 13' and is recessed inward to form a groove located between the gate structures 13'. The dielectric layer 15' fills the groove and is flush with the gate structures 13'. The termination layer 16' covers the gate structure 13', the barrier layer 14', and the dielectric layer 15'.

[0006] a dielectric layer 21' formed on the termination layer 16';

[0007] a stop layer 212' formed on the dielectric layer 21';

[0008] a dielectric layer 22' formed on the stop layer 212';

[0009] A metal layer 4' is formed on the dielectric layer 22';

[0010] The contact member 3' and the conducting member 5' are used to achieve communication between the gate structure 13' or the active structure 12' and the metal layer 4'. The conducting member 5' penetrates the dielectric layer 22' and the stop layer 4' and then communicates with the contact member 3'. There are three types of contact members 3'. One type connects the gate structure 13' and the conductive member 5'. This type of contact member 3' penetrates the dielectric layer 21' and the termination layer 16' and then abuts against the gate structure 13'. The second type of contact member 3' connects the active structure 12 and the conductive member 5'. This type of contact member 3' penetrates the dielectric layer 21', the termination layer 16', the dielectric layer 15', and the barrier layer 14' and then abuts against the active structure 12'. The third type is an adjacent structure that simultaneously realizes the connection between the gate structure 13', the active structure 12' and the conductive member 5'. This type of contact member penetrates the dielectric layer 21' and the termination layer 16', and then part of it directly contacts the gate structure 13', while the other part continues to penetrate the dielectric layer 15' and the barrier layer 14' and then contacts the active structure 12'.

[0011] A drawback of these devices is that the contact and conductive components are prone to misalignment or displacement. This misalignment is becoming increasingly severe as technology continues to advance towards miniaturization. This misalignment can lead to deviations and poor uniformity in the critical dimensions of the resulting device, and also creates significant parasitic capacitance due to the misaligned components. Summary of the Invention

[0012] The technical problem to be solved by the present invention is to provide a memory cell, an array thereof and a preparation method thereof in view of the above-mentioned defects of the prior art.

[0013] The technical solution adopted by the present invention to solve its technical problem is:

[0014] In one aspect, a storage unit is constructed, comprising:

[0015] a plurality of transistors having active structures and gate structures;

[0016] a plurality of regional metal layers located above the plurality of transistors and spaced apart from each other at the same height;

[0017] A plurality of conductive plugs are connected to the transistors and the regional metal layer, and part or all of the conductive plugs adopt a continuous connecting member to achieve electrical connection between the gate structure and / or active structure and the corresponding regional metal layer.

[0018] In a second aspect, a storage unit array is constructed, including a plurality of storage units arranged in an array, wherein any two adjacent storage units are mirrored about the adjacent surfaces.

[0019] In a third aspect, a method for preparing a memory cell is constructed, the method comprising forming each layer structure of the memory cell by the following steps:

[0020] Step 1: providing a substrate, wherein the substrate comprises a substrate layer, and the substrate layer comprises a plurality of transistors provided with active structures and gate structures;

[0021] Step 2: depositing a first dielectric layer on the substrate;

[0022] Step three, forming a connecting member, including: opening a first opening penetrating through the first dielectric layer to expose the gate structure and / or the active structure, and depositing a conductive material in the opening to form a connecting member connecting the gate structure and / or the active structure;

[0023] Step 4: forming a continuous stop layer above the first dielectric layer and the connecting member;

[0024] Step five: etching the stop layer and filling it to form multiple metal layers. The multiple metal layers all penetrate the stop layer and are separated from each other. The gate structure and / or active structure that needs to be connected to the metal layer are connected to the metal layer via the connecting member.

[0025] The memory cell, array, and preparation method of the present invention have the following beneficial effects: the present invention can save photomasks and, when applied to a production line, can save a large number of photomasks in the process; a single connecting component is used to connect the metal layer and the gate structure, thereby reducing the possibility of misalignment. Because a large number of photomasks are often required during the mid-stage process, multiple misalignment problems are prone to occur, and the process window is small, each time a photomask is saved, a misalignment problem can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only embodiments of the present invention. Those skilled in the art can also derive other drawings based on the provided drawings without inventive work.

[0027] Figure 1 is a cross-sectional view of a conventional semiconductor device;

[0028] Figure 2 This is a schematic diagram of the distribution of the active area;

[0029] Figure 3 is a schematic diagram of the distribution of the gate structure;

[0030] Figure 4 This is a schematic diagram of the distribution of active structures;

[0031] Figure 5 is a schematic diagram of the distribution of contact components;

[0032] Figure 6 Schematic diagram of the distribution of conductive components;

[0033] Figure 7 is a schematic diagram of the distribution of connecting components;

[0034] Figure 8 It is a schematic diagram of the distribution of metal layers;

[0035] Figure 9 yes Figure 8 The cross-sectional view corresponding to AA;

[0036] Figure 10 yes Figure 8 The cross-sectional view corresponding to BB;

[0037] Figure 11 is a schematic diagram of the second form of connecting member;

[0038] Figure 12 is a schematic diagram of the third form of connecting member;

[0039] Figure 13 is a schematic diagram of the fourth form of connecting member;

[0040] Figure 14 It is a schematic diagram of the distribution of the connecting components and the metal layer in the second embodiment. DETAILED DESCRIPTION

[0041] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. The drawings illustrate exemplary embodiments of the present invention. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present invention.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. It should be noted that the terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only.

[0043] As used in this specification, terms containing ordinal numbers such as "first" and "second" may be used to describe various components, but these components are not limited by these terms. The purpose of using these terms is only to distinguish one component from other components. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. The term "and / or" as used herein includes any and all combinations of one or more of the relevant listed items.

[0044] The general concept of the present invention is that the structure of a typical memory cell includes a transistor, a metal layer, and a conductive plug connecting the transistor and the metal layer to achieve electrical connection of the device. In the prior art, the conductive plugs are arranged in a sequence of contact members and conductive members along the horizontal plane of the device. The concept of the present invention is to design the conductive plugs as continuous connecting members. There are two options: the first option is to use connecting members for some of the conductive plugs connecting the transistor and the metal layer, while the remaining ones follow the original contact member plus conductive member scheme. For example, considering manufacturing issues, it is recommended that all conductive plugs connecting to the transistor gate structure be a single continuous connecting member, while the remaining conductive plugs connecting to the transistor active structure are all composed of conductive members and contact members that abut vertically along the thickness of the entire memory cell, as in the first embodiment of the present invention. The second option is to use connecting members for all conductive plugs connecting the transistor and the metal layer, as in the second embodiment of the present invention. The present invention also provides a corresponding method for manufacturing a memory cell, as in the third embodiment of the present invention.

[0045] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the drawings and specific implementation methods of the specification. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present application, rather than limitations on the technical solution of the present application. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0046] Example 1

[0047] Taking into account that memory cell arrays are directly produced in actual production, the drawings given in this embodiment are actually drawings of a memory cell array composed of multiple memory cells. The multiple memory cells are arranged in an array in a horizontal plane, and each cell is divided into a multi-layer structure in the thickness direction. Any two adjacent cells are mirrored about the adjacent surface. The so-called adjacent surface refers to the vertical plane at the connection position of the two cells, that is, the structures of each layer of adjacent cells are mirrored.

[0048] Each memory cell includes: a plurality of transistors having active structures and gate structures; a plurality of regional metal layers spaced apart from each other at the same height above the plurality of transistors; and a plurality of conductive plugs connecting the transistors and the regional metal layers, wherein some or all of the conductive plugs use a continuous connecting member to achieve electrical connection between the gate structure and / or active structure and the corresponding regional metal layer.

[0049] Specifically, the bottom layer of each unit is a substrate, which includes a substrate layer where a gate structure and an active structure are arranged. Figure 2 , the figure is a top-down perspective, each figure shows eight memory cells, and the two adjacent cells are mirrored about the adjacent surface, as shown by the dotted line in the figure. It can be seen that the two adjacent unit cells in the figure are mirrored relative to the horizontal dotted line between them, and the two adjacent cells on the left and right are mirrored relative to the vertical dotted line between them. Each cell in the memory cell array is rectangular, and these cells include two mutually perpendicular arrangement directions on the horizontal plane: left-right direction and up-down direction. Hereinafter, we use X-axis and Y-axis to represent left-right direction and up-down direction. Each cell has four active areas distributed along the Y-axis. Each active area is parallel to the X-axis and its two ends extend to the adjacent cells along the X-axis. The four active areas include a first active area AA1, a second active area AA2, a third active area AA3 and a fourth active area AA4.

[0050] refer to Figure 3 Three gate structures parallel to the Y-axis are distributed within each unit. The three gate structures include a first gate structure P1, a second gate structure P2, and a third gate structure P3. The first gate structure P1 crosses the first active area AA1 and the second active area AA2, and the second gate structure P2 crosses the third active area AA3 and the fourth active area AA4. The first gate structure P1 and the second gate structure P2 are collinear and spaced apart, and their ends away from each other extend along the Y-axis to adjacent units. The third gate structure P3 crosses the four active areas AA1-AA4. The third gate structure P3 is staggered with the first gate structure P1 and the second gate structure P2, and both ends of the third gate structure P3 maintain a certain distance from the adjacent units. Using the gate structure as an ion implantation mask, N-type impurities or P-type impurities are implanted on both sides of each gate structure in the four active areas, thereby forming eight groups of active structures. Figure 4 , specifically:

[0051] A set of active structures is formed on both sides of the first gate structure P1 and in the first active area AA1, so that the first transistor T1 is formed together with a portion of the first gate structure P1 overlapping with the first active area AA1;

[0052] A set of active structures is formed on both sides of the first gate structure P1 and in the second active area AA2, so that the active structures and the portion of the first gate structure P1 overlapping with the second active area AA2 constitute the second transistor T2;

[0053] A set of active structures is formed on both sides of the second gate structure P2 and in the third active area AA3, thereby forming a third transistor T3 together with a portion of the second gate structure P2 overlapping with the third active area AA3;

[0054] A set of active structures is formed on both sides of the second gate structure P2 and in the fourth active area AA4, thereby forming a fourth transistor T4 together with a portion of the second gate structure P2 overlapping with the fourth active area AA4;

[0055] A set of active structures is formed on both sides of the third gate structure P3 and in the first active area AA1, thereby forming a fifth transistor T5 together with a portion of the third gate structure P3 overlapping with the first active area AA1;

[0056] A set of active structures is formed on both sides of the third gate structure P3 and in the second active area AA2, thereby forming a sixth transistor T6 together with a portion of the third gate structure P3 overlapping with the second active area AA2;

[0057] A set of active structures is formed on both sides of the third gate structure P3 and in the third active area AA3, thereby forming a seventh transistor T7 together with a portion of the third gate structure P3 overlapping the third active area AA3;

[0058] A set of active structures is formed on both sides of the third gate structure P3 and in the fourth active area AA4 , thereby forming the eighth transistor T8 together with a portion of the third gate structure P3 overlapping with the fourth active area AA4 .

[0059] In this embodiment, the plurality of conductive plugs specifically include: three connection members SCP1 to SCP3, six contact members C1 to C6 and four conducting members V1 - 1 to V1 - 4.

[0060] refer to Figure 5 , the six contact components specifically include:

[0061] The first contact member C1 abuts against the active structure of the first transistor T1 on a side away from the fifth transistor T5 , and extends along the X-axis to the adjacent memory cell to achieve sharing with the transistor of the adjacent cell.

[0062] The second contact member C2 abuts against the active structure of the sixth transistor T6 on a side away from the second transistor T2, and the second contact member C2 extends along the X-axis to the adjacent memory cell to achieve sharing with the transistor of the adjacent cell;

[0063] The third contact member C3 abuts against the active structure of the third transistor T3 and the fourth transistor T4 on a side away from the seventh transistor T7 and the eighth transistor T8 and crosses the third active area AA3 and the fourth active area AA4. The third contact member C3 extends along the X-axis to the adjacent memory cell to achieve sharing with the transistor of the adjacent cell.

[0064] The fourth contact member C4 abuts against the active structure of the seventh transistor T7 and the eighth transistor T8 on a side away from the third transistor T3 and the fourth transistor T4 and crosses the third active area AA3 and the fourth active area AA4. The fourth contact member C4 extends along the X-axis and the Y-axis to the adjacent memory cell, respectively, to achieve sharing with the transistors of the adjacent cell.

[0065] A fifth contact member C5 is located between the first transistor T1 and the fifth transistor T5 and above the first active area AA1. The fifth contact member C5 simultaneously connects two adjacent active structures of the first transistor T1 and the fifth transistor T5. The fifth contact member C5 extends along the Y-axis to an adjacent memory cell, thereby sharing transistors with adjacent cells.

[0066] The sixth contact member C6 is between the second transistor T2, the third transistor T3, the fourth transistor T4 and the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 and crosses over the second active area AA2, the third active area AA3, and the fourth active area AA4, and the sixth contact member C6 connects the two active structures close to each other between the second transistor T2 and the sixth transistor T6, connects the two active structures close to each other between the third transistor T3 and the seventh transistor T7, and connects the two active structures close to each other between the fourth transistor T4 and the eighth transistor T8.

[0067] Specifically, refer to Figure 6 The present invention requires that the contact members connected to the metal layer are C1, C2, C3, and C4. Therefore, a first conductive member V1-1 is formed above the first contact member C1 to abut against it, a second conductive member V1-2 is formed above the second contact member C2 to abut against it, a third conductive member V1-3 is formed above a specific area of the third contact member C3 to abut against it, and a fourth conductive member V1-4 is formed above a specific area of the fourth contact member C4 to abut against it.

[0068] Continue to refer Figure 7 , specifically:

[0069] The first connecting member SCP1 is above the gate structure of the fifth transistor T5 , and the first connecting member SCP1 extends toward the X-axis to connect with the fifth contact member C5 to form a first adjacent structure;

[0070] The second connecting member SCP2 is above the gate structure of the second transistor T2, and the second connecting member SCP2 extends to connect with the sixth contact member C6 to form a second adjacent structure;

[0071] The third connecting member SCP3 is above an end of the second gate structure away from the first gate structure, and the third connecting member SCP3 extends in the Y-axis direction to the adjacent memory cell.

[0072] refer to Figure 8 Specifically, the multiple metal layers include four regional metal layers M1-1 to M1-4, and M1-1 to M1-4 are all on the same layer. Specifically:

[0073] First-region metal layer M1-1: The first-region metal layer M1-1 is not connected to other connecting members in the same cell. Specifically, the first-region metal layer M1-1 includes a strip portion and two protrusions. The strip portion extends along the X-axis, with both ends extending to adjacent memory cells. One protrusion extends from the strip portion near the first conductive member V1-1 along the Y-axis to abut above the first conductive member V1-1. The other protrusion extends from the strip portion near the second conductive member V1-2 along the Y-axis to abut above the second conductive member V1-2.

[0074] The second region metal layer M1-2 is in contact with the upper portion of the third conductive element V1-3 to achieve electrical connection with the active structure of the third transistor T3 through the third conductive element V1-3. Both ends of the second region metal layer M1-2 extend along the X-axis to the adjacent memory cell.

[0075] The third-region metal layer M1-3 is in contact with the top of the third connecting member SCP3 to achieve common electrical connection with the gate structures of the third transistor T3 and the fourth transistor T4 through the third connecting member SCP3. The third-region metal layer M1-3 is in a rectangular block shape. An end of the third-region metal layer M1-3 away from the second-region metal layer M1-2 extends along the Y-axis to the adjacent memory cell.

[0076] The fourth regional metal layer M1-4 is in contact with the top of the fourth conductive component V1-4 to achieve common electrical connection with the active structure of the seventh transistor T7 and the eighth transistor T8 through the fourth conductive component V1-4. One end of the fourth regional metal layer M1-4 away from the second regional metal layer M1-2 extends along the Y-axis to the adjacent memory cell, and one end of the fourth regional metal layer away from the third regional metal layer M1-3 extends along the X-axis to the adjacent memory cell.

[0077] Thus, T1 and T6 are electrically connected to M1-1 through C1 and C2, V1-1 and V1-2 in sequence, and M1-1 serves as a common active area of T1 and T6, such as Vcc, and the power supply voltage is applied to the common active area.

[0078] The active structure at one end of T7 away from T3 and the active structure at one end of T8 away from T4 are electrically connected in sequence through C4, V1-4 and M1-4, and the fourth region metal layer M1-4 serves as a common active area of T7 and T8, such as Vss;

[0079] The active structure at one end of T3 away from T7 and the active structure at one end of T4 away from T8 are electrically connected to M1-2 via C3, V1-3 and M1-2 in sequence. M1-2 serves as a bit line BL and is arranged parallel to the active area.

[0080] The gate structures in T3 and T4 are electrically connected to M1-3 via continuous P2 and SCP3, with M1-3 serving as word lines WL. The active structure in T2 near T6, the active structure in T3 near T7, the active structure in T4 near T8, the active structure in T6 near T2, the active structure in T7 near T3, and the active structure in T8 near T4 are electrically connected via C6, which serves as a data transmission node.

[0081] The above mainly introduces the positional relationship of transistors, contact components, conductive components, connecting components, etc. In terms of hierarchical structure, combined with Figure 9-10A gate structure 13 (i.e., the aforementioned gate structures P1 to P3) and an active structure 12 are provided on the substrate layer 11. The active structure 12 includes a source and a drain structure. A barrier layer 14 abuts against the sidewalls of the gate structure 13 and covers the upper surface of the portion of the substrate layer 11 located between the gate structures 13 and the upper surface of the active structure 12. The barrier layer 14 is flush with the gate structure 13 in height and is recessed inward to form a groove located between the gate structures 13. The dielectric layer 15 fills the groove of the barrier layer 14 and is flush with the gate structure 13 in height. A termination layer 16 covers the gate structure 13, the barrier layer 14, and the dielectric layer 15. The termination layer 16 covers the gate structure 13, the barrier layer 14, and the dielectric layer 15. A dielectric layer is disposed above the termination layer 16, specifically comprising a lower interlayer dielectric layer 21 and an upper interlayer dielectric layer 22. A stop layer 4 is disposed on the upper interlayer dielectric layer 22, which is then etched and filled with metal layers 41 (i.e., the aforementioned metal layers M1-1 to M1-4). A conductive plug is a structure used to electrically connect the gate structure 13, the active structure 12, and the metal layer 41. In the prior art, conductive plugs are typically bottom contact members coupled with upper conductive members. The present invention proposes replacing some or all of the conductive plugs with a single, continuous connection member SCP, which extends through all structures between the gate structure / active structure and the metal layer to be connected.

[0082] Reference below Figure 9-13 , introduces three feasible solutions for connecting components SCP:

[0083] The first option is to refer to Figure 10 An opening is opened above the gate structure 13, penetrating the lower interlayer dielectric layer 21 and the upper interlayer dielectric layer 22 and exposing the gate structure 13. Then, a conductive material is directly deposited in the opening to form a connecting member SCP. The conductive material is tungsten, copper, cobalt, rubidium, molybdenum, or an alloy of the above components.

[0084] The second option is: Reference Figure 11 An opening is formed above the gate structure 13, penetrating the lower interlayer dielectric layer 21 and the upper interlayer dielectric layer 22 and exposing the gate structure 13. A conductive material is deposited in the opening to form a liner layer 31 to reduce the resistance of the device. Then, a conductive material is deposited to fill the entire opening to form a connector 32. In other words, the entire connector SCP is composed of the liner layer 31 and the connector 32. The liner layer 31 is made of at least one of a single metal, a metal alloy, a metal nitride, and a metal silicide, such as titanium, titanium nitride, or a copper-manganese compound. Depending on the silicon material in the dielectric layer, a metal silicide, such as a titanium-silicon compound or a manganese-silicon compound, can also be selectively grown. Figure 11 The lining layer 31 covers the bottom and side walls of the entire coupling 32. Figure 12In other embodiments, only the bottom and sidewalls of the connector 32 may be partially covered. The liner layer 31 serves to act as an adhesive, improving the bonding strength between the connector 32 and the dielectric layer, while preventing or slowing down the diffusion of elements in the connector 32.

[0085] Considering that during the production process of the connecting component SCP, it is necessary to open a hole in the depth direction of the double-layer dielectric layer to penetrate the entire double-layer dielectric layer, the depth of the hole is relatively deep, and problems such as filling gaps are likely to occur when filling the metal material later. The preferred third solution is:

[0086] refer to Figure 13 An opening is opened above the gate structure 13, penetrating the lower interlayer dielectric layer 21 and the upper interlayer dielectric layer 22 and exposing the gate structure 13. The opened opening is filled in batches to form at least two layers of stacked connection structures, first forming a bottom layer of connection structure that abuts the gate structure, and finally forming a top layer of connection structure that abuts the metal layer.

[0087] Among them, the steps for forming a non-top connection structure are: forming a preliminary liner layer with a groove by atomic layer deposition along the bottom and side walls of the opening, and filling the groove with a dummy part; etching the preliminary liner layer and the dummy part to the required height; removing the dummy part to expose the groove, and filling the groove with metal material; etching the metal material to the required height to obtain a layer of connection structure; if a non-top connection structure is to be formed next, the non-top connection structure forming step is performed again, otherwise the following top connection structure forming step is performed.

[0088] The steps of forming the top connection structure are: depositing the materials of the liner layer and the connection member in sequence in the opening provided with the connection structure and on the surface of the first dielectric layer, and then removing the excess material by planarization to expose the surface of the first dielectric layer and form the topmost connection structure in the opening.

[0089] For example, Figure 13 Taking the three-layer connection structure as an example, the manufacturing process of the three-layer connection structure is:

[0090] First, a bottom layer of connection structure is produced: a preliminary liner layer with a groove is deposited along the bottom and sidewalls of the opening by atomic layer deposition, and a dummy part is filled in the groove; a first liner layer is formed by etching the preliminary liner layer and the dummy part to a desired height; the dummy part is removed to expose the groove, and a metal material is filled in the groove; the metal material is etched to a desired height to form a bottom layer of connection structure.

[0091] Then, a middle layer of connection structure is made: in the opening provided with the bottommost connection structure, a preliminary liner layer with a groove is deposited along the bottom and sidewalls of the opening by atomic layer deposition, and a dummy part is filled in the groove; a second liner layer is formed by etching the preliminary liner layer and the dummy part to a desired height; the dummy part is removed to expose the groove, and a metal material is filled in the groove; the metal material is etched to a desired height to form a middle layer of connection structure.

[0092] Finally, the topmost connection structure is produced: the materials of the liner layer and the connection member are sequentially deposited in the opening provided with the intermediate connection structure and on the surface of the upper interlayer dielectric layer 22, and the excess material is removed by chemical mechanical planarization to expose the surface of the upper interlayer dielectric layer 22 and form the topmost connection structure in the opening.

[0093] In this way, the connection member SCP is split into a multi-layer connection structure to achieve this. The use of the multi-layer connection structure can avoid problems such as filling gaps caused by an excessively large aspect ratio of the opening, thereby improving the filling quality.

[0094] It can be understood that the forming schemes of the contact member C and the conductive member V may refer to the three forming schemes of the connection member SCP.

[0095] It can be seen that the technical solution of the 8-transistor memory cell of this embodiment greatly optimizes the arrangement of transistors and improves the effective utilization rate of the transistor circuit layout area. The above effects are mainly reflected in two aspects:

[0096] 1) A single connecting component is used, which saves the misalignment area of traditional contact components and conductive components.

[0097] 2) Structural design in the memory cell, such as four transistors sharing a third gate structure as a transistor gate structure and forming a connection; a sixth contact member is designed to be connected to the active structure area shared by three pairs of transistors (T2 and T6, T3 and T7, T4 and T8), and the sixth contact member serves as a data node to achieve data transmission between the six transistors.

[0098] In this embodiment, although the connecting member SCP is only used to connect the gate structure and the metal layer, the active structure maintains the original contact member and conductive member connection scheme. It is understood that it can actually be used only to connect the active structure and the metal layer, while the gate structure maintains the original contact member and conductive member connection scheme, depending on the specific design requirements of the device. It can also be used to connect the gate structure and the active structure simultaneously, as shown in the following embodiment 2.

[0099] Example 2

[0100] refer to Figure 14The memory cell of this embodiment still includes four active areas (AA1-AA4), three gate structures (P1-P3), and eight transistors (T1-T8). The difference is that no conductive plugs formed by contact members and conductive members are used. All conductive plugs are connecting members. Specifically, this embodiment includes a total of seven connecting members S1-S7:

[0101] The first connecting member S1 serves as a first adjacent structure, abutting above the gate structure of the fifth transistor T5 and located above the first active area AA1, while connecting the two adjacent active structures of the first transistor T1 and the fifth transistor T5. The first connecting member S1 extends along the Y-axis to the adjacent memory cell. For details, please refer to the first adjacent structure in Example 1, except that the first adjacent structure in Example 1 is not a continuous whole.

[0102] The second connecting member S2 serves as a second adjacent structure, abutting above the gate structure of the second transistor T2, and being located between the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8, and crossing over the second active area AA2, the third active area AA3, and the fourth active area AA4. The second connecting member S2 connects the two adjacent active structures between the second transistor T2 and the sixth transistor T6, the two adjacent active structures between the third transistor T3 and the seventh transistor T7, and the two adjacent active structures between the fourth transistor T4 and the eighth transistor T8. For details, reference may be made to the second adjacent structure in the first embodiment, except that the second adjacent structure in the first embodiment is not a continuous whole.

[0103] The third connecting member S3 is above the end of the second gate structure away from the first gate structure, refer to the third connecting member SCP3 in the first embodiment.

[0104] The fourth connecting member S4 abuts against the active structure of the first transistor T1 on a side away from the fifth transistor T5, and the fourth connecting member S4 extends along the X-axis to the adjacent memory cell;

[0105] The fifth connecting member S5 abuts against the active structure of the sixth transistor T6 on a side away from the second transistor T2, and the fifth connecting member S5 extends along the X-axis to the adjacent memory cell;

[0106] The sixth connecting member S6 abuts against the active structure of the third transistor T3 and the fourth transistor T4 on a side away from the seventh transistor T7 and the eighth transistor T8 and crosses the third active area AA3 and the fourth active area AA4, and the sixth connecting member S6 extends along the X-axis to the adjacent memory cell;

[0107] The seventh connecting member S7 abuts against the active structure of the seventh transistor T7 and the eighth transistor T8 on the side away from the third transistor T3 and the fourth transistor T4 and crosses the third active area AA3 and the fourth active area AA4, and the seventh connecting member S7 extends along the X-axis and the Y-axis to the adjacent memory cell.

[0108] The metal layer of this embodiment includes:

[0109] The first region metal layer M1-1 includes a strip portion and two protruding portions. The strip portion extends along the X-axis and extends adjacent units at both ends. One protruding portion extends from a position of the strip portion near the fourth connecting member S4 along the Y-axis to above the fourth connecting member S4 and abuts against it. The other protruding portion extends from a position of the strip portion near the top of the fifth connecting member S5 along the Y-axis to above the fifth connecting member S5 and abuts against it.

[0110] The second region metal layer M1-2 abuts against the upper portion of the sixth coupling member S6 to electrically connect to the active structures of the third transistor T3 and the fourth transistor T4 through the sixth coupling member S6;

[0111] a third-region metal layer M1-3 abutting against an upper portion of the third coupling member S3 to achieve common electrical connection with the gate structures of the third transistor T3 and the fourth transistor T4 via the third coupling member S3; an end of the third-region metal layer M1-3 away from the second-region metal layer M1-2 extending along the Y-axis to an adjacent memory cell;

[0112] The fourth-region metal layer M1-4 abuts against the top of the seventh connecting member S7 to achieve common electrical connection with the active structures of the seventh transistor T7 and the eighth transistor T8 through the seventh connecting member S7. One end of the fourth-region metal layer M1-4 away from the second-region metal layer M1-2 extends along the Y-axis to the adjacent memory cell, and one end of the fourth-region metal layer M1-4 away from the third-region metal layer M1-3 extends along the X-axis to the adjacent memory cell.

[0113] That is, the metal layers of this embodiment are equivalent to the regional metal layers M1-1, M1-3, and M1-4 remaining unchanged compared to the first embodiment, but the regional metal layer M1-2 needs to avoid S2 and cannot extend to adjacent units along the X axis at both ends as in the first embodiment.

[0114] It is understandable that, since all components in this embodiment are connecting members, only one dielectric layer may replace the lower interlayer dielectric layer 21 and the upper interlayer dielectric layer 22 .

[0115] Example 3

[0116] This embodiment mainly discloses a method for preparing a memory cell, the method comprising:

[0117] S101: Provide a substrate.

[0118] This step is specifically divided into the following sub-steps: providing active areas AA1 to AA4 on the substrate; providing a gate structure; using the gate structure as an ion implantation mask, implanting N-type or P-type impurities on both sides of each gate structure in the four active areas to form eight groups of active structures, ultimately obtaining transistors T1 to T8; and forming a barrier layer 14, a dielectric layer 15, and a termination layer 16 in sequence from bottom to top above the substrate, the active structures, and the gate structures. For details, please refer to the Examples section.

[0119] S102: depositing a lower interlayer dielectric layer on the substrate, specifically depositing a lower interlayer dielectric layer 21 on the stop layer 16;

[0120] S103: forming contact members C1 to C6 for connecting the active structure above the active structure to be connected to the metal layer, penetrating the lower interlayer dielectric layer 21 , the termination layer 16 , the dielectric layer 15 and the barrier layer 14 , for details, refer to the embodiment part.

[0121] S104: forming an upper interlayer dielectric layer 22 by deposition on the lower interlayer dielectric layer 21;

[0122] S105 : Conductive components V1 - 1 to V1 - 4 are formed above the contact components C1 to C4 that need to be directly connected to the metal layer, penetrating the upper interlayer dielectric layer 22 . For details, please refer to the embodiment section.

[0123] S106 : forming connection members SCP1 - SCP3 for connecting the gate structure above the gate structure to be connected to the metal layer, which penetrate the lower interlayer dielectric layer 21 , the upper interlayer dielectric layer 22 and the termination layer 16 . For details, refer to the embodiment section.

[0124] S107: forming a continuous stop layer 4 on the upper interlayer dielectric layer 22 and the connection components SCP1 to SCP3 and the conductive components V1-1 to V1-4;

[0125] S108: etching the stop layer 4 and filling the layer to form a plurality of metal layers 41 (specifically M1-1 to M1-4).

[0126] As described above, the six contact members of this embodiment can all be formed in a single photolithography step, the three connecting members can all be formed in a single photolithography step, and the four metal layers can be formed in the same photolithography step. It should be noted that in the prior art, the formation of the contact members and conductive members connecting the gate, and the formation of the contact members and conductive members connecting the source and drain, are often performed in separate steps. One reason is that the depths of the two contact members are inconsistent. If all are done in one step, it is difficult to ensure the accuracy of the two types of contact holes formed. The second reason is that due to factors such as diffraction of the light source, the patterned photoresist layer formed during the photolithography process is prone to dimensional deviation. As devices become smaller, the clearance between the two types of contact holes, and even the two corresponding types of through holes, is too low, providing insufficient space for optical proximity correction. This is because a separate step process is required to achieve more precise dimensions. Therefore, the present invention can save some photomasks (e.g., photomasks for connecting the gate structure).

[0127] Example 4

[0128] This embodiment mainly discloses a method for preparing the memory cell according to embodiment 2, the method comprising:

[0129] S101: Provide a substrate, refer to the third embodiment for details.

[0130] S102: depositing a first dielectric layer on the substrate, specifically depositing the first dielectric layer on the stop layer 16. The first dielectric layer can be a single dielectric layer or multiple dielectric layers, such as a lower interlayer dielectric layer 21 and an upper interlayer dielectric layer 22.

[0131] S103: Form openings through the first dielectric layer, the termination layer 16 or through the first dielectric layer, the termination layer 16, the dielectric layer 15, and the barrier layer 14 above the active structure and the gate structure that need to be connected to the metal layer to form seven connecting components S1-S7. For details, refer to the second embodiment.

[0132] S104: forming a continuous stop layer 4 above the first dielectric layer and the connecting components S1-S7;

[0133] S108: etching the stop layer 4 and filling to form a plurality of metal layers 41 (specifically M1-1 to M1-4), refer to the second embodiment for details.

[0134] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. A storage unit, characterized in that: include: a plurality of transistors having active structures and gate structures; a plurality of regional metal layers located above the plurality of transistors and spaced apart from each other at the same height; a plurality of conductive plugs connecting the transistors and the regional metal layer, wherein some or all of the conductive plugs adopt a continuous connecting member to achieve electrical connection between the gate structure and / or active structure and the corresponding regional metal layer; The bottom layer of each unit is a substrate, which has a substrate layer, a gate structure and an active structure arranged on the substrate layer, a barrier layer abutting the sidewall of the gate structure, the barrier layer being flush with the gate structure, and a dielectric layer filling the groove of the barrier layer and being flush with the gate structure; a stop layer covering the gate structure, the barrier layer, and the dielectric layer, a dielectric layer being arranged above the stop layer, the dielectric layer including a lower interlayer dielectric layer and an upper interlayer dielectric layer, a stop layer being arranged on the upper interlayer dielectric layer, the stop layer being etched and filled to form multiple metal layers; An opening is opened above the gate structure, penetrating the lower interlayer dielectric layer and the upper interlayer dielectric layer and exposing the gate structure. The opening is filled in batches to form at least three stacked connection structures. First, a bottom layer of connection structure abutting the gate structure is formed, and finally a top layer of connection structure abutting the metal layer is formed. This is achieved by splitting the connection component into a multi-layer connection structure. The use of a multi-layer connection structure can avoid the filling gap problem caused by an excessively large aspect ratio of the opening and improve the filling quality.

2. The storage unit according to claim 1, wherein The regional metal layer includes a branch-shaped metal layer, which includes a strip portion and a plurality of protrusions formed by branches from the strip portion. The protrusions are electrically connected to corresponding transistors through conductive plugs respectively, and the strip portion does not abut other conductive plugs in the same unit.

3. The storage unit according to claim 1, wherein The conductive plugs connected to the gate structure / active structure of the transistor are all connecting components, and the remaining conductive plugs connected to the active structure / gate structure of the transistor are all composed of conductive structures and contact components that are abutted up and down along the thickness direction of the entire memory cell.

4. The storage unit according to claim 3, wherein: The memory cell includes four active areas and three gate structures, the four active areas are arranged separately along the Y-axis direction, each active area is parallel to the X-axis direction and both ends extend to the adjacent memory cell along the X-axis direction, the three gate structures are parallel to the Y-axis, each active area and two of the gate structures have an intersection, each cell has a total of eight intersections, and eight transistors are formed at the eight intersections, wherein the X-axis and the Y-axis represent two mutually perpendicular arrangement directions of the multiple cells on a horizontal plane; The four active areas include a first active area, a second active area, a third active area, and a fourth active area; the three gate structures include a first gate structure, a second gate structure, and a third gate structure; the first gate structure crosses the first active area and the second active area, the second gate structure crosses the third active area and the fourth active area, the first gate structure and the second gate structure are collinear and spaced apart, and the third gate structure crosses the four active areas and is staggered from the first gate structure and the second gate structure; forming a set of active structures on both sides of the first gate structure and in the first active region, thereby forming a first transistor together with a portion of the first gate structure overlapping the first active region; forming a set of active structures on both sides of the first gate structure and in the second active region, thereby forming a second transistor together with a portion of the first gate structure overlapping with the second active region; forming a set of active structures on both sides of the second gate structure and in the third active region, thereby forming a third transistor together with a portion of the second gate structure overlapping the third active region; forming a set of active structures on both sides of the second gate structure and in the fourth active region, thereby forming a fourth transistor together with a portion of the second gate structure overlapping the fourth active region; forming a set of active structures on both sides of the third gate structure and in the first active region, thereby forming a fifth transistor together with a portion of the third gate structure overlapping with the first active region; forming a set of active structures on both sides of the third gate structure and in the second active region, thereby forming a sixth transistor together with a portion of the third gate structure overlapping the second active region; forming a set of active structures on both sides of the third gate structure and in the third active region, thereby forming a seventh transistor together with a portion of the third gate structure overlapping the third active region; A set of active structures is formed on both sides of the third gate structure and in the fourth active region, and together with a portion of the third gate structure overlapping the fourth active region, constitutes an eighth transistor.

5. The storage unit according to claim 4, wherein: The plurality of conductive plugs include four conducting members, six contact members and three coupling members; The first contact member abuts against an upper portion of the active structure of the first transistor on a side away from the fifth transistor; The second contact member abuts against the active structure of the sixth transistor on a side away from the second transistor; The third contact member abuts against the active structures of the third transistor and the fourth transistor on a side away from the seventh transistor and the eighth transistor and crosses the third active area and the fourth active area; The fourth contact member abuts against the active structures of the seventh transistor and the eighth transistor on a side away from the third transistor and the fourth transistor and crosses the third active area and the fourth active area; A fifth contact member is located between the first transistor and the fifth transistor and above the first active region, and the fifth contact member simultaneously connects two active structures of the first transistor and the fifth transistor that are close to each other; a sixth contact member between the second transistor, the third transistor, the fourth transistor, and the sixth transistor, the seventh transistor, and the eighth transistor and crossing over the second active region, the third active region, and the fourth active region, wherein the sixth contact member connects two active structures adjacent to each other between the second transistor and the sixth transistor, connects two active structures adjacent to each other between the third transistor and the seventh transistor, and connects two active structures adjacent to each other between the fourth transistor and the eighth transistor; The first conductive member abuts against the top of the first contact member, the second conductive member abuts against the top of the second contact member, the third conductive member abuts against a specific area of the third contact member, and the fourth conductive member abuts against a specific area of the fourth contact member; The first connecting member is above the gate structure of the fifth transistor, and the first connecting member extends toward the X-axis to connect with the fifth contact member to form a first adjacent structure; The second coupling member is above the gate structure of the second transistor, and the second coupling member extends to connect with the sixth contact member to form a second adjacent structure; The third coupling member is above an end of the second gate structure away from the first gate structure. The storage unit according to claim 5 , wherein: The plurality of regional metal layers include: a first-region metal layer, the first-region metal layer including a strip portion and two protruding portions, the strip portion extending along the X-axis, one protruding portion extending from a position of the strip portion close to the first conductive member along the Y-axis to above the first conductive member and abutting against the first conductive member, and the other protruding portion extending from a position of the strip portion close to above the second conductive member along the Y-axis to above the second conductive member and abutting against the second conductive member; The second region metal layer abuts against the upper portion of the third conductive component to achieve electrical connection with the active structures of the third transistor and the fourth transistor through the third conductive component; a third region metal layer abutting against an upper portion of the third connecting member to achieve common electrical connection with the gate structures of the third transistor and the fourth transistor through the third connecting member; The fourth region metal layer abuts against the upper portion of the fourth conductive component to achieve common electrical connection with the active structures of the seventh transistor and the eighth transistor through the fourth conductive component.

7. The storage unit according to claim 4, wherein: The plurality of conductive plugs includes seven coupling members: The first connecting member serves as a first adjacent structure, abutting against the gate structure of the fifth transistor and being located above the first active region, while connecting two adjacent active structures of the first transistor and the fifth transistor; The second coupling member serves as a second adjacent structure, abutting against the gate structure of the second transistor, and being located between the second transistor, the third transistor, the fourth transistor, and the sixth transistor, the seventh transistor, and the eighth transistor, and crossing over the second active region, the third active region, and the fourth active region, wherein the second coupling member connects two adjacent active structures between the second transistor and the sixth transistor, connects two adjacent active structures between the third transistor and the seventh transistor, and connects two adjacent active structures between the fourth transistor and the eighth transistor; The third coupling member is above an end of the second gate structure away from the first gate structure; The fourth connecting member abuts against the upper portion of the active structure of the first transistor on a side away from the fifth transistor; The fifth connecting member abuts against the upper portion of the active structure of the sixth transistor on a side away from the second transistor; The sixth connecting member abuts against the active structures of the third transistor and the fourth transistor on a side away from the seventh transistor and the eighth transistor and crosses the third active area and the fourth active area; The seventh connecting member abuts against the active structures of the seventh and eighth transistors at a side away from the third and fourth transistors and crosses the third and fourth active regions.

8. The storage unit according to claim 7, wherein: The plurality of regional metal layers include: a first-region metal layer, the first-region metal layer comprising a strip portion and two protruding portions, the strip portion extending along the X-axis, one protruding portion extending from a position of the strip portion near the fourth coupling member along the Y-axis to above the fourth coupling member and abutting against the fourth coupling member, and the other protruding portion extending from a position of the strip portion near the top of the fifth coupling member along the Y-axis to above the fifth coupling member and abutting against the fifth coupling member; The second region metal layer abuts against the upper portion of the sixth connecting member to achieve electrical connection with the active structures of the third transistor and the fourth transistor through the sixth connecting member; a third region metal layer abutting against an upper portion of the third connecting member to achieve common electrical connection with the gate structures of the third transistor and the fourth transistor through the third connecting member; The fourth region metal layer abuts against the seventh connecting member to achieve common electrical connection with the active structures of the seventh transistor and the eighth transistor through the seventh connecting member.

9. A memory cell array, characterized in that: The invention comprises a plurality of storage units according to any one of claims 1 to 8 arranged in an array, wherein any two adjacent storage units are mirror images about the adjacent surfaces.

10. A method for preparing a memory cell according to any one of claims 1 to 8, characterized in that: The method comprises forming each layer structure of the memory cell by the following steps: Step 1: providing a substrate, wherein the substrate comprises a substrate layer, and the substrate layer comprises a plurality of transistors provided with active structures and gate structures; Step 2: depositing a first dielectric layer on the substrate; Step three, forming a connecting member, including: openings that penetrate the first dielectric layer once to expose the gate structure and / or the active structure, depositing a conductive material in the openings to form connecting members connecting the gate structure and / or the active structure; openings that penetrate the first dielectric layer above the gate structure and expose the gate structure, filling the openings in batches to form at least three stacked connecting structures, first forming a bottommost connecting structure abutting the gate structure, and finally forming a topmost connecting structure abutting the metal layer, and splitting the connecting member into a multi-layer connecting structure to achieve this. Using a multi-layer connecting structure can avoid the filling gap problem caused by an excessively large aspect ratio of the opening, thereby improving the filling quality; Step 4: forming a continuous stop layer above the first dielectric layer and the connecting member; Step five: etching the stop layer and filling it to form multiple metal layers. The multiple metal layers all penetrate the stop layer and are separated from each other. The gate structure and / or active structure that needs to be connected to the metal layer are connected to the metal layer via the connecting member.

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