Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure, the method comprising: forming a mask sidewall layer that conformally covers the top of a target layer, and the top and sidewall of a core layer, wherein in a first region, in a direction perpendicular to the direction in which an opening extends, the mask sidewall layers on opposite sidewalls of the core layer have a minimum spacing value; forming a grinding stop layer that conformally covers the mask sidewall layer, wherein the thickness of the grinding stop layer is greater than or equal to half of the minimum spacing value; forming a filling material layer that covers the top of the grinding stop layer; flattening the filling material layer, wherein the remaining filling material layer serves as a filling layer, and the top of the filling layer is flush with the top of the grinding stop layer in the first region; using the top of the mask sidewall layer as a stop position, etching and removing the grinding stop layer and the filling layer that are higher than the top of the mask sidewall layer, wherein the tops of the remaining grinding stop layer and the filling layer are flush with the top of the mask sidewall layer. The probability of defects on the top and sidewalls of the mask sidewall layer is reduced.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to move towards smaller process nodes driven by Moore's Law, making integrated circuits develop in the direction of smaller size, higher circuit precision and higher circuit complexity.

[0003] In the development of integrated circuits, the functional density (i.e. the number of internal connection structures of each chip) is gradually increasing, while the geometric size (i.e. the minimum component size that can be produced using process steps) is gradually decreasing, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] At present, as technology nodes continue to shrink, how to improve the matching degree between the pattern formed on the wafer and the target pattern has become a challenge. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention further provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a target layer for forming a target pattern, the substrate comprising a first region and a second region, the pitch of adjacent target patterns formed in the first region being smaller than the pitch of adjacent target patterns formed in the second region, a core layer being formed on the top of the target layer in the first region, an opening penetrating the core layer being formed in the core layer; forming a mask sidewall layer conformally covering the top of the target layer, and the top and sidewalls of the core layer, wherein in the first region, in a direction perpendicular to the extension direction of the opening, a mask sidewall layer located opposite to the core layer is formed; There is a minimum spacing value between the mask side wall layers on the side wall; a grinding stop layer is formed to conformally cover the mask side wall layer, and the thickness of the grinding stop layer is greater than or equal to half of the minimum spacing value; a filling material layer is formed to cover the top of the grinding stop layer; the filling material layer is flattened, and the remaining filling material layer is used as a filling layer, and the top of the filling layer is flush with the top of the grinding stop layer in the first area; after forming the filling layer, the grinding stop layer and the filling layer that are higher than the top of the mask side wall layer are etched away with the top of the mask side wall layer as the stop position, and the tops of the remaining grinding stop layer and the filling layer are flush with the top of the mask side wall layer.

[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0008] An embodiment of the present invention provides a method for forming a semiconductor structure, forming a mask sidewall layer that conformally covers the top of a target layer, as well as the top and sidewalls of a core layer, wherein in a first region, in a direction perpendicular to an extension direction of an opening, the mask sidewall layers on opposite sidewalls of the core layer have a minimum spacing value; forming a grinding stop layer that conformally covers the mask sidewall layer, wherein the thickness of the grinding stop layer is greater than or equal to half of the minimum spacing value; forming a filling material layer that covers the top of the grinding stop layer; flattening the filling material layer, wherein the remaining filling material layer serves as a filling layer, and the top of the filling layer is flush with the top of the grinding stop layer in the first region; after forming the filling layer, taking the top of the mask sidewall layer as a stop position, etching away the grinding stop layer and the filling layer that are higher than the top of the mask sidewall layer, wherein the tops of the remaining grinding stop layer and the filling layer are flush with the top of the mask sidewall layer. Compared with the current solution of directly using the top of the mask sidewall layer as the stop position of the planarization process after forming a filling material layer on the top of the grinding stop layer, the embodiment of the present invention forms a grinding stop layer that conformally covers the mask sidewall layer, and the thickness of the grinding stop layer is greater than or equal to half of the minimum spacing value. Therefore, in the first area, the grinding stop layer can at least fill the remaining space of the partial opening exposed by the mask sidewall layer, so that the top surface flatness of the grinding stop layer in the first area is relatively high, providing a good flat surface for the subsequent planarization process, and then forming a filling material layer on the top of the grinding stop layer. The material layer is then formed by taking the top of the grinding stop layer with higher top surface flatness in the first region as the stopping position of the planarization process, and part of the filling material layer is removed so that the top of the filling layer is flush with the top of the grinding stop layer in the first region, and finally the grinding stop layer and the filling layer that are higher than the top of the mask side wall layer are removed as a whole, so that the top of the remaining grinding stop layer and the filling layer have higher flatness than the top of the mask side wall layer. Therefore, by combining the planarization process with the etching process, the probability of defects on the top and side walls of the mask side wall layer is reduced, thereby improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 3 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0010] Figures 4 to 16 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0011] At present, the performance of semiconductor structures still needs to be improved. Now, combined with a method for forming a semiconductor structure, the reasons why the performance of semiconductor structures still needs to be improved are analyzed. Figures 1 to 3 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0012] refer to Figure 1 , providing a substrate, the substrate comprising a target layer 10, the substrate comprising a first region 10A and a second region 10B, a core layer 13 is formed on the top of the target layer 10 in the first region 10A, an opening 20 is formed in the core layer 13 and penetrates the core layer 13; forming a mask sidewall layer 14 conformally covering the top of the target layer 10, and the top and sidewalls of the core layer 13.

[0013] refer to Figure 2 , forming an etch stop layer 15 covering the top and sidewalls of the mask sidewall layer 14 , and after forming the etch stop layer 15 , forming a filling layer 16 covering the top and sidewalls of the etch stop layer 15 , and the filling layer also fills the remaining space of the opening 20 .

[0014] refer to Figure 3 , taking the top of the mask spacer layer 14 as the stop position, planarizing the etching stop layer 15 and the filling layer 16 on the top of the mask spacer layer 14 .

[0015] Through research, it is found that, affected by the pattern density of the core layer 13 in different areas, the removal rates of the etch stop layer 15 and the filling layer 16 on the top of the mask sidewall layer 14 are different. Therefore, in the process of flattening the etch stop layer 15 and the filling layer 16 on the top of the mask sidewall layer 14, the top of the remaining etch stop layer 15 and the filling layer 16 are less flat than the top of the mask sidewall layer 14, and it is easy to grind the mask sidewall layer 14, the etch stop layer 15 and the filling layer 16 at the same time, thereby increasing the probability of defects on the top and sidewalls of the mask sidewall layer, thereby affecting the performance of the semiconductor structure.

[0016] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a target layer for forming a target pattern, the substrate comprising a first region and a second region, the pitch of adjacent target patterns formed in the first region being smaller than the pitch of adjacent target patterns formed in the second region, a core layer being formed on the top of the target layer in the first region, an opening penetrating the core layer being formed in the core layer; forming a mask sidewall layer conformally covering the top of the target layer, and the top and sidewalls of the core layer, wherein in the first region, in a direction perpendicular to the extension direction of the opening, a mask sidewall layer located at the core layer is disposed on the top of the target layer and the top and sidewalls of the core layer are disposed on the top of the target layer and the ... There is a minimum spacing value between the mask side wall layers on the side walls; a grinding stop layer is formed to conformally cover the mask side wall layer, and the thickness of the grinding stop layer is greater than or equal to half of the minimum spacing value; a filling material layer is formed to cover the top of the grinding stop layer; the filling material layer is flattened, and the remaining filling material layer is used as a filling layer, and the top of the filling layer is flush with the top of the grinding stop layer in the first area; after forming the filling layer, the grinding stop layer and the filling layer that are higher than the top of the mask side wall layer are etched away with the top of the mask side wall layer as the stop position, and the tops of the remaining grinding stop layer and the filling layer are flush with the top of the mask side wall layer.

[0017] In the scheme disclosed in the embodiment of the present invention, a mask sidewall layer is formed to conformally cover the top of the target layer, as well as the top and sidewall of the core layer, and in the first region, in a direction perpendicular to the extension direction of the opening, the mask sidewall layers located on the opposite sidewalls of the core layer have a minimum spacing value; a grinding stop layer is formed to conformally cover the mask sidewall layer, and the thickness of the grinding stop layer is greater than or equal to half of the minimum spacing value; a filling material layer is formed to cover the top of the grinding stop layer; the filling material layer is planarized, and the remaining filling material layer serves as a filling layer, and the top of the filling layer is flush with the top of the grinding stop layer in the first region; after the filling layer is formed, the grinding stop layer and the filling layer that are higher than the top of the mask sidewall layer are etched away with the top of the mask sidewall layer as the stop position, and the tops of the remaining grinding stop layer and the filling layer are flush with the top of the mask sidewall layer. Compared with the current solution of directly using the top of the mask sidewall layer as the stop position of the planarization process after forming a filling material layer on the top of the grinding stop layer, the embodiment of the present invention forms a grinding stop layer that conformally covers the mask sidewall layer, and the thickness of the grinding stop layer is greater than or equal to half of the minimum spacing value. Therefore, in the first area, the grinding stop layer can at least fill the remaining space of the partial opening exposed by the mask sidewall layer, so that the top surface flatness of the grinding stop layer in the first area is relatively high, providing a good flat surface for the subsequent planarization process, and then forming a filling material layer on the top of the grinding stop layer. The material layer is then formed by taking the top of the grinding stop layer with higher top surface flatness in the first region as the stopping position of the planarization process, and part of the filling material layer is removed so that the top of the filling layer is flush with the top of the grinding stop layer in the first region, and finally the grinding stop layer and the filling layer that are higher than the top of the mask side wall layer are removed as a whole, so that the top of the remaining grinding stop layer and the filling layer have higher flatness than the top of the mask side wall layer. Therefore, by combining the planarization process with the etching process, the probability of defects on the top and side walls of the mask side wall layer is reduced, thereby improving the performance of the semiconductor device.

[0018] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0019] Figures 4 to 16 Schematic diagram of the structure corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention

[0020] refer to Figure 4, providing a substrate, the substrate including a target layer 101 for forming a target pattern, the substrate including a first area 100A and a second area 100B, a pitch of adjacent target patterns formed in the first area 100A is smaller than a pitch of adjacent target patterns formed in the second area 100B, a core layer 103 is formed on the top of the target layer 101 in the first area 100A, and an opening 160 is formed in the core layer 103 and penetrates the core layer 103.

[0021] The substrate is used to provide a process platform for subsequent process steps.

[0022] In this embodiment, semiconductor devices such as transistors and capacitors may be formed in the substrate, and functional structures such as resistor structures and conductive structures may also be formed in the substrate.

[0023] In this embodiment, the pitch of the adjacent target patterns formed in the first region 100A is smaller than the pitch of the adjacent target patterns formed in the second region 100B. The pitch of the adjacent target patterns refers to the sum of the line width of the target pattern and the space between the adjacent target patterns.

[0024] Since the pitch of adjacent target patterns in the first area 100A is smaller than the pitch of adjacent target patterns formed in the second area 100B, the line width of the target pattern in the first area 100A is usually smaller and the density of the target pattern in the first area 100A is higher. In order to meet the graphic accuracy of target patterns in different areas, the first area 100A needs to adopt a self-aligned double patterning process (Self-aligned Double Patterning, SADP), while the second area 100B does not need to adopt a self-aligned double patterning process.

[0025] The target layer 101 is used as a material layer that needs to be patterned to form a target pattern.

[0026] In this embodiment, the target layer 101 is a hard mask material layer.

[0027] The hard mask material layer is used to form a hard mask layer through a subsequent patterning process.

[0028] In this embodiment, the material of the target layer 101 is silicon nitride. In other embodiments, the material of the target layer 101 may also be silicon oxide, silicon oxynitride, silicon carbide, titanium, titanium oxide, titanium nitride, tantalum, tantalum oxide, tantalum nitride, boron nitride, copper nitride, aluminum nitride or tungsten nitride.

[0029] Correspondingly, the target pattern is a mask opening formed in the hard mask layer, and the mask opening is used to define a functional pattern in the substrate. The functional pattern may be a gate structure, an interconnect opening in a back end of line (BEOL) process, a fin in a fin field effect transistor (FinFET), a channel stack in a gate all around (GAA) transistor or a forksheet transistor, a hard mask (HM) layer, and the like.

[0030] In this embodiment, the substrate further includes a dielectric layer 100 , and the target layer 101 is located on the dielectric layer 100 .

[0031] The dielectric layer 100 is subsequently patterned to form a plurality of interconnect openings in the dielectric layer 100. The interconnect openings serve as functional patterns.

[0032] In this embodiment, the material of the dielectric layer 100 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6), silicon oxide, silicon nitride or silicon oxynitride, etc. Specifically, the material of the dielectric layer 100 may be SiOCH.

[0033] It should be noted that, in this embodiment, other film layers or structures in the substrate located below the dielectric layer 100 are not illustrated.

[0034] In this embodiment, the substrate further includes an etch stop layer 102 , and the etch stop layer 102 is located above the target layer 101 .

[0035] The etch stop layer 102 is used to define the etch stop position in the etching process of the subsequent graphic definition processing, so as to reduce the loss of the target layer 101, improve the depth consistency of the etching process, and further improve the effect of the subsequent graphic process.

[0036] In this embodiment, the material of the etch stop layer 102 is silicon oxide. In other embodiments, the material of the etch stop layer may also be silicon nitride, aluminum oxide, titanium nitride, tungsten nitride or aluminum nitride.

[0037] In this embodiment, the core layer 103 provides a process basis for subsequently forming a mask spacer layer covering the top and sidewalls of the core layer 103 .

[0038] It should be noted that before the subsequent step of etching the target layer 101 to form a target pattern, the core layer 103 needs to be removed first. In order to facilitate the removal of the core layer 103, a material that is easy to remove is selected. In this embodiment, the material of the core layer 103 includes one or more of amorphous silicon, polysilicon, silicon oxide, silicon nitride, and silicon oxynitride. As an embodiment, the material of the core layer 103 is amorphous silicon.

[0039] In this embodiment, the opening 160 provides a spatial position for subsequently forming a mask sidewall layer and a grinding stop layer in the opening 160 , and is also used to define the shape and position of a subsequent target pattern.

[0040] refer to Figure 5 , forming a mask sidewall layer 104 that conformally covers the top of the target layer 101, and the top and sidewalls of the core layer 103. In the first region 100A, in a direction perpendicular to the extension direction of the opening 160, the mask sidewall layers 104 located on opposite sidewalls of the core layer 103 have a minimum spacing value S.

[0041] The mask spacer layer 104 provides a process basis for the subsequent formation of mask spacers.

[0042] In this embodiment, the process of forming the mask spacer layer 104 includes an atomic layer deposition process.

[0043] The atomic layer deposition process includes performing multiple atomic layer deposition cycles, which is beneficial to improving the thickness uniformity of the mask sidewall layer 104 and enabling the mask sidewall layer 104 to conformally cover the sidewall and top of the core layer 103 and the bottom of the opening 160. In other embodiments, the mask sidewall layer can also be formed by a chemical vapor deposition process (CVD).

[0044] In this embodiment, in the step of forming the mask spacer 104 , the material of the mask spacer 104 includes one or more of TiO, SiN and SiO 2 .

[0045] By adopting TiO, SiN or SiO2, in the semiconductor manufacturing process, under the mature atomic layer deposition process, the thickness uniformity of the mask sidewall layer 104 formed on the sidewall and top of the core layer 103 and the bottom of the opening 160 is good, and the material of the core layer 103 (such as amorphous silicon) has a high etching selectivity, which is beneficial to the subsequent removal of the core layer 103.

[0046] In this embodiment, in the first region 100A, in a direction perpendicular to the extending direction of the opening 160 , there is a minimum spacing value S between the mask spacers 104 located on opposite side walls of the core layer 103 .

[0047] Since the core layer 103 in the first region 100A may be discrete and non-uniform, that is, the lateral size of the opening 160 may be non-uniform, the intervals between the mask spacer layers on the opposite sidewalls of the core layer may also be different. When the first region 100A has multiple interval values, the minimum value of the multiple interval values ​​is the minimum interval value S.

[0048] refer to Figure 6 , forming a grinding stop layer 105 conformally covering the mask sidewall layer 104, wherein the thickness of the grinding stop layer 105 is greater than or equal to half of the minimum spacing value.

[0049] It should be noted that by making the thickness of the grinding stop layer 105 greater than or equal to half of the minimum spacing value, the grinding stop layer 105 can at least fill the remaining space of the partial opening 160 exposed by the mask side wall layer 104, so that the top surface flatness of the grinding stop layer 105 in the first area 100A is higher, providing a good flat surface for the subsequent planarization process.

[0050] Among them, since the thickness of the grinding stop layer 105 is greater than or equal to half of the minimum spacing value, when the remaining space of the opening 160 exposed by the mask side wall layer 104 is small, the grinding stop layer 105 located on the opposite side walls of the mask side wall layer 104 contacts each other, thereby filling the remaining space of the opening 160.

[0051] It should also be noted that even if the remaining space of some openings 160 is not filled with the grinding stop layer 105, the remaining space of the openings 160 formed with the grinding stop layer 105 is also relatively small, which is still beneficial for making the top surface flatness of the grinding stop layer 105 in the first area 100A higher.

[0052] In addition, since the core layer 103 in the first region 100A is discrete and non-uniform, that is, the lateral size of the opening 160 is non-uniform, in the first region 100A, the opening 160 with a larger lateral size is affected by the thickness of the grinding stop layer 105, and the grinding stop layer 105 does not completely fill the opening 160 with a larger lateral size.

[0053] In the step of forming a grinding stop layer 105 conformally covering the mask side wall layer 104 according to the size of the remaining space of the opening 160 exposed by the mask side wall layer 104, in the first area 100A, the grinding stop layer 105 fills the remaining space of each opening 160 exposed by the mask side wall layer 104, or the grinding stop layer 105 fills the remaining space of the portion of the opening 160 exposed by the mask side wall layer 104.

[0054] like Figure 6 As shown, as an example, the grinding stop layer 105 fills the remaining space of the portion of the opening 160 exposed by the mask sidewall layer 104 .

[0055] In this embodiment, the process of forming the grinding stop layer 105 includes an atomic layer deposition process.

[0056] The grinding stop layer 105 formed by the atomic layer deposition process has good thickness uniformity and good step coverage, so that the grinding stop layer 105 can conformally cover the mask sidewall layer 104. In the first area 100A, for the opening 160 with a smaller lateral dimension, the grinding stop layer 105 on the opposite sidewalls of the mask sidewall layer 104 is in contact with each other, thereby filling the remaining space of the opening 160 exposed by the mask sidewall layer 104. In other embodiments, the mask sidewall layer can also be formed by a chemical vapor deposition process (CVD).

[0057] In this embodiment, in the step of forming the grinding stop layer 105 , the grinding stop layer 105 has a thickness of 10 nanometers to 30 nanometers.

[0058] It should be noted that the thickness of the grinding stop layer 105 should not be too large or too small. If the thickness of the grinding stop layer 105 is too large, in the subsequent etching process of removing the grinding stop layer 105 above the top of the mask sidewall layer 104, the process difficulty and process cost are increased, and the process efficiency is reduced; if the thickness of the grinding stop layer 105 is too small, in the first area 100A, it is easy to cause the grinding stop layer 105 to occupy too little space in the opening 160, which is easy to cause the top surface flatness of the grinding stop layer 105 in the first area 100A to be poor, and then in the subsequent process of flattening the filling material layer, the probability of residues forming on the top surface of the grinding stop layer 105 is increased, and at the same time, the top surface flatness of the grinding stop layer 105 is reduced, affecting the subsequent process of forming the target pattern in the target layer 101, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, the thickness of the grinding stop layer 105 is 10 nanometers to 30 nanometers. For example, the grinding stop layer 105 has a thickness of 15 nanometers, 20 nanometers, or 25 nanometers.

[0059] refer to Figure 7 , forming a filling material layer 106 covering the top of the grinding stop layer 105.

[0060] The filling material layer 106 provides a process basis for subsequently forming a filling layer.

[0061] In this embodiment, the process of forming the filling material layer 106 includes a chemical vapor deposition process.

[0062] The chemical vapor deposition process has the characteristics of simple operation, high process efficiency and good coverage.

[0063] In this embodiment, the material of the filling material layer 106 includes one or more of silicon oxide, silicon oxynitride, silicon carbide, titanium, titanium oxide, titanium nitride and silicon nitride.

[0064] Silicon oxide, silicon oxynitride, silicon carbide, titanium, titanium oxide, titanium nitride and silicon nitride have characteristics such as high material hardness, so that the hardness of the shielding layer subsequently formed in the second region 100B is also relatively large, so that the shielding layer can be retained during the subsequent removal of the core layer 103.

[0065] refer to Figure 8 , the filling material layer 106 is planarized, and the remaining filling material layer 106 is used as a filling layer 107, and the top of the filling layer 107 is flush with the top of the grinding stop layer 105 in the first area 100A.

[0066] It can be seen from the above records that since the top surface flatness of the grinding stop layer 105 in the first area 100A is relatively high, during the process of flattening the filling material layer 106, the good flat surface environment of the top of the grinding stop layer 105 makes the top of the filling layer 107 flush with the top of the grinding stop layer 105 in the first area 100A.

[0067] In this embodiment, the step of planarizing the filling material layer 106 includes: using the top of the grinding stop layer 105 in the first area 100A as the stop position of the planarization process, and removing a portion of the filling material layer 106 .

[0068] The top surface flatness of the grinding stop layer 105 is relatively high. The top of the grinding stop layer 105 in the first area 100A is used as the stop position of the flattening process, so that a filling layer 107 with a relatively high top surface flatness is formed in the second area 100B, thereby preparing for the subsequent formation of a blocking layer in the second area 100B.

[0069] In this embodiment, the process of planarizing the filling material layer 106 includes a chemical mechanical polishing process.

[0070] The chemical mechanical polishing process has the characteristics of global planarization, low process cost, and high operating efficiency. At the same time, since the top surface flatness of the grinding stop layer 105 in the first area 100A is relatively high, a good flat surface is provided for the planarization process, so that the top surface flatness of the filling layer 107 and the top surface flatness of the grinding stop layer 105 in the first area 100A are also relatively high.

[0071] refer to Fig. 9 After the filling layer 107 is formed, the grinding stop layer 105 and the filling layer 107 that are higher than the top of the mask side wall layer 104 are etched away with the top of the mask side wall layer 104 as the stopping position, and the tops of the remaining grinding stop layer 105 and the filling layer 107 are flush with the top of the mask side wall layer 104.

[0072] The top of the filling layer 107 is flush with the top of the grinding stop layer 105 in the first area 100A, and the grinding stop layer 105 and the filling layer 107 that are higher than the top of the mask sidewall layer 104 are removed as a whole, so that the tops of the remaining grinding stop layer 105 and the filling layer 107 have a high flatness with the top of the mask sidewall layer 104. Therefore, by combining the planarization process with the etching process, the probability of defects on the top and sidewalls of the mask sidewall layer 104 is reduced, thereby improving the performance of the semiconductor device.

[0073] In this embodiment, the process of etching and removing the grinding stop layer 105 and the filling layer 107 above the top of the mask spacer layer 104 includes a plasma dry etching process.

[0074] In the process of removing the grinding stop layer 105 and the filling layer 107 above the top of the mask sidewall layer 104 by using a plasma dry etching process, the removal rate of the grinding stop layer 105 and the filling layer 107 is much greater than the removal rate of the mask sidewall layer 104 .

[0075] Moreover, the plasma dry etching process has the advantages of high etching rate, high etching selectivity and low cost.

[0076] In this embodiment, the parameters of the plasma dry etching process include: the etching gas includes one or more of CF6 and CHF3; the chamber pressure is 3mTorr to 10mTorr; and the RF power is 50W to 1000W.

[0077] It should be noted that the chamber pressure should not be too high or too low. If the chamber pressure is too high, in the process of removing the grinding stop layer 105 and the filling layer 107 above the top of the mask sidewall layer 104, it is easy to cause part of the grinding stop layer 105 to remain on the top of the mask sidewall layer 104, affecting the subsequent process of forming the target pattern in the target layer 101, thereby affecting the performance of the semiconductor; if the chamber pressure is too low, in the process of removing the grinding stop layer 105 and the filling layer 107 above the top of the mask sidewall layer 104, it is easy for the grinding stop layer 105 and the filling layer 107 in the opening 160 to be partially removed, resulting in poor top surface flatness of the remaining grinding stop layer 105 and the filling layer 107, thereby affecting the subsequent formation of the target pattern in the target layer 101. For this reason, in this embodiment, the chamber pressure is 3mTorr to 10mTorr.

[0078] It should be noted that the RF power should not be too large or too small. If the RF power is too large, in the process of removing the grinding stop layer 105 and the filling layer 107 above the top of the mask sidewall layer 104, it is easy for the grinding stop layer 105 and the filling layer 107 in the opening 160 to be partially removed, resulting in poor top surface flatness of the remaining grinding stop layer 105 and the filling layer 107, thereby affecting the subsequent formation of the target pattern in the target layer 101; if the RF power is too small, in the process of removing the grinding stop layer 105 and the filling layer 107 above the top of the mask sidewall layer 104, it is easy to cause the remaining part of the grinding stop layer 105 to be located on the top of the mask sidewall layer 104, affecting the subsequent process of forming the target pattern in the target layer 101, thereby affecting the performance of the semiconductor. For this reason, in this embodiment, the RF power is 50W to 1000W.

[0079] In this embodiment, in the step of etching and removing the grinding stop layer 105 and the filling layer 107 above the top of the mask sidewall layer 104 , the etching selectivity ratio of the grinding stop layer 105 to the mask sidewall layer 104 is greater than 10:1.

[0080] It should be noted that the etching selectivity ratio of the grinding stop layer 105 to the mask sidewall layer 104 should not be too small. If the etching selectivity ratio of the grinding stop layer 105 to the mask sidewall layer 104 is too small, in the process of etching and removing the grinding stop layer 105 above the top of the mask sidewall layer 104, it is easy to cause the mask sidewall layer 104 to be easily etched and removed, thereby affecting the subsequent process of forming the target pattern in the target layer 101, thereby affecting the performance of the semiconductor. For this reason, in the present embodiment, in the step of etching and removing the grinding stop layer 105 and the filling layer 107 above the top of the mask sidewall layer 104, the etching selectivity ratio of the grinding stop layer 105 to the mask sidewall layer 104 is greater than 10:1.

[0081] In this embodiment, the etching selectivity ratio of the filling layer 107 to the mask spacer layer 104 is greater than 10:1.

[0082] It should be noted that the etching selectivity ratio of the filling layer 107 to the mask sidewall layer 104 should not be too small. If the etching selectivity ratio of the filling layer 107 to the mask sidewall layer 104 is too small, in the process of etching and removing the filling layer 107 above the top of the mask sidewall layer 104, it is easy to cause the mask sidewall layer 104 to be easily etched and removed, thereby affecting the subsequent process of forming the target pattern in the target layer 101, thereby affecting the performance of the semiconductor. For this reason, in this embodiment, the etching selectivity ratio of the filling layer 107 to the mask sidewall layer 104 is greater than 10:1.

[0083] refer to Figure 10 to Figure 11 , remove the remaining grinding stop layer 105 and filling layer 107 located in the first area 100A, and part of the filling layer 107 and grinding stop layer 105 located in the second area 100B, form a discrete blocking layer 112 on the top of the mask sidewall layer 104 in the second area 100B, and form a first groove 113 between the side walls of adjacent mask sidewall layers 104, between the side walls of the mask sidewall layer 104 and the blocking layer 112, and between the side walls of adjacent blocking layers 112.

[0084] The bottom of the first trench 113 exposes a portion of the top surface of the mask spacer layer, which provides a process basis for subsequently removing the mask spacer layer 104 at the bottom of the first trench 113 .

[0085] In this embodiment, the step of etching and removing the remaining grinding stop layer 105 and the filling layer 107 located in the first area 100A, and a portion of the filling layer 107 located in the second area 100B includes: Fig.10 As shown, a patterned mask layer 111 is formed on the top of the mask spacer layer 104 and the top of the filling layer 107, and the mask layer 111 in the first region 100A is located on the top of the core layer 103, and the mask layer 111 in the second region 100B is located on the top of the filling layer 107; Fig.11 As shown, the remaining grinding stop layer 105 and the filling layer 107 located in the first area 100A, and a portion of the filling layer 107 located in the second area 100B are etched away using the mask layer 111 as a mask.

[0086] In this embodiment, the process of etching and removing the remaining grinding stop layer 105 and the filling layer 107 located in the first area 100A and a portion of the filling layer 107 and the grinding stop layer 105 located in the second area 100B includes a dry etching process.

[0087] It should be noted that the dry etching process includes an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching, and its longitudinal etching rate is much greater than the lateral etching rate, and can obtain a fairly accurate pattern conversion, which is conducive to accurately controlling the morphology of the mask sidewall layer 104 and the shielding layer in the process of removing the remaining grinding stop layer 105 and the filling layer 107 located in the first area 100A, and the part of the filling layer 107 and the grinding stop layer 105 located in the second area 100B.

[0088] In this embodiment, the mask layer 111 includes a planarization material layer 110 , an anti-reflection coating layer 109 located on the planarization material layer 110 , and a photoresist layer 108 located on the anti-reflection coating layer 109 .

[0089] The planarization material layer 110 provides a flat surface for the formation of the photoresist layer 108, thereby improving the exposure effect during the formation of the photoresist layer 108. The material of the planarization material layer 110 includes an organic material. In this embodiment, the material of the planarization material layer 110 is spin-on carbon (SOC). In other embodiments, the material of the planarization material layer can also be other organic materials, such as: one or more of ODL (organic dielectric layer) materials, DUO (Deep UV Light Absorbing Oxide) materials and APF (Advanced Patterning Film) materials.

[0090] The material of the anti-reflective coating 109 includes a BARC (bottom anti-reflective coating) material. As an example, the BARC material is a Si-ARC (silicon-containing anti-reflective coating) material.

[0091] In this embodiment, before removing the remaining grinding stop layer 105 and filling layer 107 located in the first area 100A, and part of the filling layer 107 and grinding stop layer 105 located in the second area 100B, it also includes: using the photoresist layer 108 as a mask, etching the anti-reflective coating 109 and the planarization material layer 110 in sequence.

[0092] It should be noted that, in other embodiments, during the process of etching the anti-reflective coating and the organic material layer, the photoresist layer will be consumed, and the mask layer may accordingly only include the organic material layer and the anti-reflective coating on the organic material layer.

[0093] refer to Fig.12 After forming the blocking layer 112 and the first trench 113 , the mask sidewall layer 104 located at the top of the core layer 103 and the bottom of the first trench 113 is removed to form a mask sidewall 115 located at the sidewall of the core layer 103 .

[0094] The mask sidewalls 115 and the blocking layer 112 provide a process basis for subsequently etching the target layer 101 and forming a target pattern in the target layer 101 .

[0095] In this embodiment, the process of removing the mask sidewall layer 104 located at the top of the core layer 103 and the bottom of the first trench 113 includes a dry etching process.

[0096] refer to Fig.13 After forming the mask sidewall 115 , the core layer 103 is removed to form a second trench 116 .

[0097] The bottom of the second trench 116 exposes a portion of the top surface of the target layer 101 , so as to prepare for the subsequent formation of a target pattern in the target layer 101 .

[0098] It should be noted that the process of removing the core layer 103 includes one or both of a wet etching process and an ashing process.

[0099] The wet etching process has an isotropic characteristic and can keep the mask sidewalls 115 and the shielding layer 112 while removing the core layer 103 .

[0100] It should be noted that since the core layer 103 is made of amorphous silicon, the hardness of the amorphous silicon is lower than that of the mask sidewalls 115 and the shielding layer 112 , the mask sidewalls 115 and the shielding layer 112 can be retained during the removal of the core layer 103 .

[0101] It should also be noted that the etching selectivity ratio of the core layer 103 to the mask sidewall 115 should not be too small. If the etching selectivity ratio of the core layer 103 to the mask sidewall 115 is too small, it is easy to cause a portion of the core layer 103 to remain, affecting the subsequent process of forming the target pattern in the target layer 101, thereby affecting the performance of the semiconductor. For this reason, in the step of removing the core layer 103 in this embodiment, the etching selectivity ratio of the core layer 103 to the mask sidewall 115 is greater than 10:1.

[0102] refer to Fig.14 , using the mask sidewall 115 and the blocking layer 112 as masks, etching the target layer 101 at the bottom of the second trench 116 and the first trench 113 to form a target pattern 117 in the target layer 101 .

[0103] It can be seen from the above records that by combining the planarization process with the etching process, the probability of defects on the top and side walls of the mask sidewall layer is reduced, so that the top of the blocking layer 112 and the top of the mask sidewall 115 have a higher flatness, which correspondingly improves the graphic accuracy and graphic quality of the target graphic 117.

[0104] In this embodiment, the target layer 101 at the bottom of the second groove 116 and the first groove 113 is etched, and the step of forming a target pattern 117 in the target layer 101 includes: forming a mask opening in the target layer 101, the mask opening is used as the target pattern 117, and the remaining target layer 101 is used as a hard mask layer 180.

[0105] The hard mask layer 180 provides a process basis for subsequently etching the dielectric layer 100 to form interconnect openings in the dielectric layer 100 .

[0106] In this embodiment, the etch stop layer 102 is also formed on the target layer 101 . Therefore, the process of etching the target layer 101 to form the target pattern 117 using the mask sidewalls 115 and the blocking layer 112 as masks also includes: etching the etch stop layer 102 .

[0107] It should be noted that after forming the target pattern 117 , the process further includes: removing the mask sidewalls 115 and the shielding layer 112 .

[0108] refer to Fig.15 After forming the target pattern 117 , the forming method further includes: using the hard mask layer 180 as a mask, etching the dielectric layer 100 along the mask opening to form an interconnect opening 118 in the dielectric layer 100 .

[0109] The interconnection opening 118 provides a space for subsequently forming a metal interconnection line.

[0110] In this embodiment, by first transferring the pattern to the target layer 101 to form the hard mask layer 180 , it is beneficial to improve the process stability and process effect of etching the dielectric layer 100 and improve the accuracy of the target pattern transfer.

[0111] It should be noted that in this embodiment, other film layers or structures in the substrate below the dielectric layer 100 are not illustrated. Therefore, in the actual process, the bottom of the interconnection opening 118 exposes the corresponding conductive structure (eg, contact hole plug, etc.).

[0112] It should also be noted that, in the subsequent process of forming metal interconnection lines in the interconnection openings 118 , the remaining etch stop layer 102 and hard mask layer 180 are removed to expose the top surface of the dielectric layer 100 in preparation for subsequent process technology.

[0113] refer to Fig.16 , a metal interconnection line 120 is formed in the interconnection opening 118 .

[0114] The metal interconnection line 120 is used to realize electrical connection between the semiconductor structure and an external circuit or other interconnection structures.

[0115] In this embodiment, the material of the metal interconnection line 120 is copper. In other embodiments, the material of the metal interconnection line can also be a conductive material such as aluminum.

[0116] In this embodiment, the metal interconnection line 120 is formed in the interconnection groove by electroplating.

[0117] Accordingly, the process of forming the metal interconnection line 120 includes a step of filling with a conductive material and a step of planarizing the conductive material to remove the conductive material above the top of the dielectric layer.

[0118] In this embodiment, a chemical mechanical polishing process is used to planarize the conductive material.

[0119] The chemical mechanical polishing process enables the metal interconnection line 120 formed in the interconnection groove to have a flat surface, thereby improving the electrical connection effect of the metal interconnection line 120 .

[0120] The detailed description of the metal interconnection line 120 is omitted here.

[0121] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a target layer for forming a target pattern, the substrate comprising a first region and a second region, the pitch of adjacent target patterns formed in the first region being smaller than the pitch of adjacent target patterns formed in the second region, a core layer being formed on the top of the target layer in the first region, and an opening penetrating the core layer being formed in the core layer; Forming a mask spacer layer conformally covering the top of the target layer, and the top and sidewalls of the core layer, wherein in the first region, in a direction perpendicular to the extension direction of the opening, the mask spacers on opposite sidewalls of the core layer have a minimum spacing value; forming a grinding stop layer conformally covering the mask sidewall layer, wherein the thickness of the grinding stop layer is greater than or equal to half of the minimum spacing value; forming a filling material layer covering the top of the grinding stop layer; planarizing the filling material layer, and the remaining filling material layer serves as a filling layer, and the top of the filling layer is flush with the top of the grinding stop layer in the first region; After forming the filling layer, the grinding stop layer and the filling layer above the top of the mask sidewall layer are etched away with the top of the mask sidewall layer as the stop position, and the tops of the remaining grinding stop layer and the filling layer are flush with the top of the mask sidewall layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The forming method further comprises: after etching away the grinding stop layer and the filling layer above the top of the mask sidewall layer, removing the remaining grinding stop layer and the filling layer located in the first area, and part of the filling layer and the grinding stop layer located in the second area, forming a discrete shielding layer on the top of the mask sidewall layer in the second area, and forming a first groove between the sidewalls of adjacent mask sidewall layers, between the sidewalls of the mask sidewall layer and the shielding layer, and between the sidewalls of adjacent shielding layers; After forming the shielding layer and the first trench, removing the mask sidewall layer located at the top of the core layer and the bottom of the first trench to form a mask sidewall located at the sidewall of the core layer; After forming the mask sidewalls, removing the core layer to form a second trench; Using the mask sidewall and the shielding layer as masks, the target layer at the bottom of the second trench and the first trench is etched to form a target pattern in the target layer.

3. The method for forming a semiconductor structure according to claim 1, wherein: The process of planarizing the filling material layer includes a chemical mechanical polishing process.

4. The method for forming a semiconductor structure according to claim 1, wherein: The process of etching and removing the grinding stop layer and the filling layer above the top of the mask sidewall layer includes a plasma dry etching process.

5. The method for forming a semiconductor structure according to claim 4, wherein: The parameters of the plasma dry etching process include: the etching gas includes one or two of C2F6 and CHF3; the chamber pressure is 3mTorr to 10mTorr; and the radio frequency power is 50W to 1000W.

6. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the grinding stop layer includes an atomic layer deposition process.

7. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming a grinding stop layer conformally covering the mask side wall layer, in the first region, the grinding stop layer fills the remaining space of each of the openings exposed by the mask side wall layer, or the grinding stop layer fills the remaining space of the portion of the opening exposed by the mask side wall layer.

8. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming the grinding stop layer, the grinding stop layer has a thickness of 10 nanometers to 30 nanometers.

9. The method for forming a semiconductor structure according to claim 1, wherein: In the step of removing the grinding stop layer and the filling layer above the top of the mask sidewall layer, the etching selectivity ratio of the grinding stop layer to the mask sidewall layer is greater than 10:1; The etching selection ratio of the filling layer to the mask sidewall layer is greater than 10:

1.

10. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the mask sidewall layer includes an atomic layer deposition process.

11. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming the mask spacer layer, the material of the mask spacer layer includes one or more of TiO, SiN and SiO2.

12. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the filling material layer includes a chemical vapor deposition process.

13. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming the filling material layer, the material of the filling material layer includes one or more of silicon oxide, silicon oxynitride, silicon carbide, titanium, titanium oxide, titanium nitride and silicon nitride.

14. The method for forming a semiconductor structure according to claim 2, wherein: The step of removing the remaining grinding stop layer and filling layer located in the first area, and part of the filling layer and grinding stop layer located in the second area includes: forming a patterned mask layer on the top of the mask side wall layer and the top of the filling layer, and the mask layer in the first area is located on the top of the core layer, and the mask layer in the second area is located on the top of the filling layer; using the mask layer as a mask, etching and removing the remaining grinding stop layer and filling layer located in the first area, and part of the filling layer and grinding stop layer located in the second area.

15. The method for forming a semiconductor structure according to claim 2, wherein: In the step of providing a substrate, the substrate further comprises a dielectric layer, and the target layer is located on the dielectric layer; The step of etching the target layer at the bottom of the second trench and the first trench to form a target pattern in the target layer comprises: forming a mask opening in the target layer, the mask opening is used as the target pattern, and the remaining target layer is used as a hard mask layer; After forming the target pattern, the forming method further comprises: using the hard mask layer as a mask, etching the dielectric layer along the mask opening to form an interconnect opening in the dielectric layer; and forming a metal interconnect line in the interconnect opening.

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