Method and device for evaluating packaging and sintering of power semiconductor device

Abstract

The invention provides a packaging and sintering evaluation method and device for a power semiconductor device, and the method comprises the steps: carrying out the non-destructive scanning through a high-frequency acoustic microtechnique, carrying out the correction through combining with a temperature-sound velocity relation model, achieving the real-time monitoring of a sintering process, and solving a problem that the transient change cannot be captured. Through frequency domain conversion and an improved inverse Fourier transform algorithm, precise reconstruction of the microstructure of the sintering interface is realized, and the limitation that the microstructure is difficult to evaluate in the prior art is overcome. Based on the reconstructed microstructure, a detailed three-dimensional geometric model is established, and time domain finite element analysis is performed, so that comprehensive thermal stress evolution data is obtained, and the defect of surface information of a traditional method is overcome. And quantitative evaluation is carried out by using the multi-dimensional feature space and the preset discrimination model, so that comprehensive analysis of the sintering quality is realized, and the defect of lack of comprehensive quantitative evaluation capability is overcome. Through organic combination of the steps, the accuracy and comprehensiveness of packaging and sintering evaluation are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of encapsulation sintering, and particularly to an evaluation method and device for the encapsulation sintering of power semiconductor devices. Background Art

[0002] In the evaluation of the encapsulation sintering quality of power semiconductor devices, traditional methods mainly rely on offline detection techniques, such as X-ray inspection, ultrasonic scanning, or cross-sectional analysis, etc. Although these methods can provide partial information about the sintering interface, they have obvious limitations. First, they are usually destructive or semi-destructive detections performed after sintering is completed and cannot reflect the dynamic changes during the sintering process in real time. Second, these methods often can only provide local or surface information and it is difficult to comprehensively and accurately evaluate the quality of the entire sintering interface.

[0003] Especially for semiconductor devices with high power density, the stress distribution and microstructure of their sintering interfaces have important impacts on the performance and reliability of the devices. However, existing evaluation methods are difficult to capture the transient stress changes during the sintering process and cannot accurately reconstruct the microstructure of the sintering interface. This may lead to the neglect of some potential quality problems in practical applications and affect the long-term reliability of the devices. Summary of the Invention

[0004] The main purpose of the present invention is to solve the technical problems in the existing evaluation methods for the encapsulation sintering of power semiconductor devices, including the inability to monitor the sintering process in real time, the difficulty in accurately evaluating the microstructure of the sintering interface, and the lack of comprehensive quantitative analysis capabilities; The first aspect of the present invention provides an evaluation method for the encapsulation sintering of power semiconductor devices, and the evaluation method for the encapsulation sintering of power semiconductor devices includes: Performing non-destructive scanning calculation on a power semiconductor device by using high-frequency acoustic microscopy technology to obtain preliminary stress distribution data of the power semiconductor device, and performing temperature compensation and correction on the preliminary stress distribution data by using the synchronously recorded surface temperature distribution of the device and a pre-established temperature - sound velocity relationship model to obtain a three-dimensional stress distribution map; Performing frequency domain conversion on the three-dimensional stress distribution map to obtain frequency domain information, and performing spatial domain conversion and correction on the frequency domain information by using an improved inverse Fourier transform algorithm to obtain a microstructure model of the sintering interface; Based on the microstructure model of the sintering interface, establishing a three-dimensional geometric model including a chip, a sintering layer, and a heat dissipation substrate, and performing time-domain finite element analysis according to the three-dimensional geometric model to obtain thermal stress evolution data of the power semiconductor device under different working cycles; Construct a multi-dimensional feature space by using the three-dimensional stress distribution diagram, the microscopic structure model of the sintering interface, and the thermal stress evolution data, and input the features of the multi-dimensional feature space into a preset discrimination model to obtain a quantitative evaluation result of the sintering quality of the power semiconductor device.

[0005] Optionally, in the first implementation manner of the first aspect of the present invention, the non-destructive scanning calculation of the power semiconductor device by using the high-frequency acoustic microscopy technology to obtain the preliminary stress distribution data of the power semiconductor device, and using the synchronously recorded device surface temperature distribution and the pre-established temperature-velocity of sound relationship model to perform temperature compensation and correction on the preliminary stress distribution data, and the obtaining of the three-dimensional stress distribution diagram includes: Perform a high-frequency acoustic wave scan on the power semiconductor device by using the high-frequency acoustic microscopy technology to obtain the original acoustic wave signal; Perform time-domain analysis and frequency-domain transformation on the original acoustic wave signal to obtain the acoustic wave propagation characteristic data; According to the acoustic wave propagation characteristic data, use the acoustic inversion algorithm to calculate the preliminary stress distribution data, and collect the temperature distribution data on the surface of the power semiconductor device; Input the preliminary stress distribution data and the temperature distribution data into the pre-established temperature-velocity of sound relationship model, perform temperature compensation calculation on the preliminary stress distribution data, and generate a three-dimensional stress distribution diagram according to the temperature compensation calculation result.

[0006] Optionally, in the second implementation manner of the first aspect of the present invention, the frequency-domain conversion of the three-dimensional stress distribution diagram to obtain the frequency-domain information, and the spatial-domain conversion and correction of the frequency-domain information by using the improved inverse Fourier transform algorithm, and the obtaining of the microscopic structure model of the sintering interface includes: Perform three-dimensional fast Fourier transform on the three-dimensional stress distribution diagram data to obtain the frequency-domain information, and construct a multi-layer interface transfer function according to the structural characteristics of the power semiconductor device; Perform convolution operation on the frequency-domain information and the multi-layer interface transfer function to obtain the corrected frequency-domain data; Apply a preset inverse Fourier transform algorithm to the corrected frequency-domain data, and reconstruct the preliminary microscopic structure of the sintering interface according to the inverse Fourier transform result; Optimize the preliminary microscopic structure by using the morphological algorithm to obtain the microscopic structure model of the sintering interface.

[0007] Optionally, in the third implementation manner of the first aspect of the present invention, the applying a preset inverse Fourier transform algorithm to the corrected frequency-domain data, and reconstructing the preliminary microscopic structure of the sintering interface according to the inverse Fourier transform result includes: Perform frequency band division and noise processing on the corrected frequency-domain data to obtain the optimized complete frequency-domain data; Perform a three-dimensional inverse Fourier transform on the optimized complete frequency-domain data to obtain preliminary spatial-domain data, and use the spatial-domain data to construct a point cloud model of the sintering interface; Apply the Markov random field algorithm to the point cloud model, and reconstruct the continuous structure of the sintering interface through an iterative optimization process to obtain a preliminary microstructure model; Optimize the preliminary microstructure model using a morphological processing algorithm to obtain a preliminary microstructure of the sintering interface.

[0008] Optionally, in the fourth implementation manner of the first aspect of the present invention, based on the microstructure model of the sintering interface, a three-dimensional geometric model including a chip, a sintering layer, and a heat dissipation substrate is established, and time-domain finite element analysis is performed according to the three-dimensional geometric model to obtain thermal stress evolution data of the power semiconductor device under different operating cycles, including: According to the microstructure model of the sintering interface, construct a three-dimensional geometric model including a chip, a sintering layer, and a heat dissipation substrate, and assign material properties to each part of the three-dimensional geometric model and define the operating conditions of the power semiconductor device; According to the defined operating conditions, establish a heat source model, and input the three-dimensional geometric model, material properties, and heat source model into finite element analysis software; Perform a non-linear transient thermo-mechanical coupling analysis through the finite element analysis software, calculate the temperature distribution and stress distribution at different time points, and extract the thermal stress data at key positions according to the temperature distribution and stress distribution at different time points to generate thermal stress evolution data of the power semiconductor device under different operating cycles.

[0009] Optionally, in the fifth implementation manner of the first aspect of the present invention, the non-linear transient thermo-mechanical coupling analysis is performed through the finite element analysis software, the temperature distribution and stress distribution at different time points are calculated, and the thermal stress data at key positions are extracted according to the temperature distribution and stress distribution at different time points to generate thermal stress evolution data of the power semiconductor device under different operating cycles, including: Set a non-linear material model and a thermo-mechanical coupling control equation in the finite element analysis software, set time discretization parameters and solution control parameters, and set periodic thermal loads and mechanical constraint conditions according to the operating characteristics of the power semiconductor device; Using the established thermo-mechanical coupling equations, based on the set periodic thermal loads and mechanical constraint conditions, perform heat conduction analysis and thermal stress analysis for each discrete time point, and obtain the temperature field distribution and stress field distribution through the solution process; According to the obtained temperature field distribution and stress field distribution, at each time step, the node temperatures and stress values at predefined key positions are extracted, and continuous thermal stress evolution curves are generated based on the node temperatures and stress values through data interpolation and smoothing processing; The Fourier analysis method is used to perform spectral decomposition on the thermal stress evolution curve, identify the main stress period and amplitude characteristics, and obtain the thermal stress evolution data of the power semiconductor device under different operating cycles.

[0010] Optionally, in the sixth implementation manner of the first aspect of the present invention, the construction of a multi-dimensional feature space by using the three-dimensional stress distribution diagram, the microscopic structure model of the sintering interface, and the thermal stress evolution data, and inputting the features of the multi-dimensional feature space into a preset discrimination model to obtain a quantitative evaluation result of the sintering quality of the power semiconductor device includes: Statistical features, morphological analysis features, and time series analysis features are respectively extracted from the three-dimensional stress distribution diagram, the microscopic structure model of the sintering interface, and the thermal stress evolution data, and combined to form a multi-dimensional feature vector; The multi-dimensional feature vector is normalized to construct a standardized multi-dimensional feature space, and the features of the multi-dimensional feature space are input into a pre-trained deep neural network discrimination model; The preliminary evaluation result of the sintering quality is obtained through the output layer of the deep neural network discrimination model, and combined with the predefined quality grade standard, the preliminary evaluation result is converted into a quantitative sintering quality score.

[0011] The second aspect of the present invention provides a device for evaluating the encapsulation sintering of a power semiconductor device, and the device for evaluating the encapsulation sintering of the power semiconductor device includes: A stress monitoring module, which is used to perform non-destructive scanning calculation on the power semiconductor device by using high-frequency acoustic microscopy technology to obtain preliminary stress distribution data of the power semiconductor device, and use the synchronously recorded device surface temperature distribution and a pre-established temperature-velocity of sound relationship model to perform temperature compensation and correction on the preliminary stress distribution data to obtain a three-dimensional stress distribution diagram; A structure reconstruction module, which is used to perform frequency domain conversion on the three-dimensional stress distribution diagram to obtain frequency domain information, and perform spatial domain conversion and correction on the frequency domain information through an improved inverse Fourier transform algorithm to obtain a microscopic structure model of the sintering interface; A thermal analysis module, which is used to establish a three-dimensional geometric model including a chip, a sintering layer, and a heat dissipation substrate based on the microscopic structure model of the sintering interface, and perform time-domain finite element analysis according to the three-dimensional geometric model to obtain thermal stress evolution data of the power semiconductor device under different operating cycles; A quality assessment module, which is used to construct a multi-dimensional feature space by using the three-dimensional stress distribution map, the microscopic structure model of the sintering interface, and the thermal stress evolution data, and input the features of the multi-dimensional feature space into a preset discrimination model to obtain a quantitative assessment result of the sintering quality of the power semiconductor device.

[0012] The above-mentioned method and device for evaluating the encapsulation sintering of a power semiconductor device utilize high-frequency acoustic microscopy technology for non-destructive scanning and are corrected in combination with a temperature-sound velocity relationship model to achieve real-time monitoring of the sintering process and solve the problem of being unable to capture transient changes. Through frequency domain conversion and an improved inverse Fourier transform algorithm, the precise reconstruction of the microscopic structure of the sintering interface is realized, overcoming the limitation of the prior art in difficultly evaluating the microscopic structure. Based on the reconstructed microscopic structure, a detailed three-dimensional geometric model is established and time-domain finite element analysis is carried out to obtain comprehensive thermal stress evolution data, making up for the deficiency of surface information in traditional methods. The use of a multi-dimensional feature space and a preset discrimination model for quantitative evaluation realizes a comprehensive analysis of the sintering quality and overcomes the defect of lacking comprehensive quantitative evaluation ability. Through the organic combination of steps, this method significantly improves the accuracy and comprehensiveness of the encapsulation sintering evaluation.

[0013] Other features and advantages of the present invention will be described in the subsequent specification, and, in part, will be obvious from the specification, or will be understood by implementing the present invention. The objectives and other advantages of the present invention are realized and obtained by the structures specifically pointed out in the specification, the claims, and the drawings.

[0014] To make the above objectives, features, and advantages of the present invention more obvious and understandable, the following specifically gives preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. Description of the Drawings

[0015] Figure 1 Schematic diagram of the first embodiment of the method for evaluating the encapsulation sintering of a power semiconductor device in an embodiment of the present invention; Figure 2 Schematic diagram of an embodiment of the device for evaluating the encapsulation sintering of a power semiconductor device in an embodiment of the present invention. Detailed Embodiments

[0016] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0017] As used in the embodiments of the present invention, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes other steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products or devices.

[0018] For ease of understanding of this embodiment, first, a method for evaluating the packaging sintering of a power semiconductor device disclosed in the embodiments of the present invention will be introduced in detail. As Figure 1 shown, this method includes the following steps: 101. Use high-frequency acoustic microscopy technology to perform non-destructive scanning calculations on the power semiconductor device to obtain preliminary stress distribution data of the power semiconductor device, and use the synchronously recorded device surface temperature distribution and a pre-established temperature-sound velocity relationship model to perform temperature compensation correction on the preliminary stress distribution data to obtain a three-dimensional stress distribution map; In one embodiment of the present invention, the step of using high-frequency acoustic microscopy technology to perform non-destructive scanning calculations on the power semiconductor device to obtain preliminary stress distribution data of the power semiconductor device, and using the synchronously recorded device surface temperature distribution and a pre-established temperature-sound velocity relationship model to perform temperature compensation correction on the preliminary stress distribution data to obtain a three-dimensional stress distribution map includes: using high-frequency acoustic microscopy technology to perform high-frequency acoustic wave scanning on the power semiconductor device to obtain an original acoustic wave signal; performing time-domain analysis and frequency-domain transformation on the original acoustic wave signal to obtain acoustic wave propagation characteristic data; according to the acoustic wave propagation characteristic data, using an acoustic inversion algorithm to calculate and obtain preliminary stress distribution data, and collecting the temperature distribution data on the surface of the power semiconductor device; inputting the preliminary stress distribution data and the temperature distribution data into a pre-established temperature-sound velocity relationship model to perform temperature compensation calculation on the preliminary stress distribution data, and generating a three-dimensional stress distribution map according to the temperature compensation calculation result.

[0019] Specifically, when performing high-frequency acoustic wave scanning on a power semiconductor device using high-frequency acoustic microscopy technology, the device needs to be firmly placed in an acoustic coupling medium first to reduce the energy attenuation of the acoustic wave during propagation in the air. The probe moves point by point along the device surface according to a pre-set stepping strategy and sends high-frequency acoustic pulses into the device. The acoustic wave generates reflections and refractions at multiple interfaces such as the chip, bonding layer, and heat dissipation substrate. The echo signal is received by the probe and then transmitted to the digital acquisition system for storage in the order of the scanning point position and time. The high-frequency probe can provide a higher resolution, making it easier to detect subtle defects or microstructural inhomogeneities in the echo. To ensure spatial accuracy, the positioning platform and the probe movement are synchronized and linked, and each step distance is accurately recorded in the system. This method does not require cutting or destructive treatment of the device and can collect the original acoustic wave data in the fully packaged state, thus presenting the acoustic response of the multi-layer structure inside the device in a real environment. After the scanning is completed, the obtained original signal can be regarded as a set of time-domain waveform sets arranged in two-dimensional or three-dimensional coordinates, providing the basic input for subsequent time-domain analysis and frequency-domain transformation.

[0020] Specifically, after obtaining the original acoustic wave data, time-domain analysis and frequency-domain transformation need to be performed to extract more accurate material and interface information. First, high-frequency noise and low-frequency drift are removed through a filtering algorithm to keep the waveform baseline relatively stable. Subsequently, the echo signal corresponding to each scanning point is segmented on the time axis, and indicators such as peak amplitude, arrival delay, and envelope shape are extracted to locate the interface position and preliminarily determine its reflection intensity. On this basis, the fast Fourier transform is performed on the signal preprocessed in the time domain to generate the corresponding amplitude spectrum and phase spectrum. The amplitude spectrum can reflect the energy distribution and attenuation trend in different frequency bands, reflecting the impedance of the device material and the absorption characteristics of the interface; the phase spectrum indicates the propagation time delay and phase shift amount of the acoustic wave between layers. By comparing the amplitude and phase changes of each scanning point in different frequency bands, the material density difference or local defect distribution can be identified. After completing this series of operations, the system stores these characteristic parameters and their spatial coordinates in a multi-dimensional data matrix together, forming a comprehensive description of the acoustic wave propagation characteristics of the device and laying an analysis foundation for subsequent inversion calculation of the stress value.

[0021] Specifically, after obtaining the acoustic wave propagation characteristic data, an acoustic inversion algorithm is needed to estimate the stress distribution inside the device. This algorithm comprehensively uses parameters such as the material elastic modulus, acoustic impedance, and wave propagation velocity, compares the extracted amplitude spectrum and phase spectrum with the assumed initial stress field. If there is a large deviation between the theoretical echo characteristics and the measured signal, the difference is reduced by adjusting physical quantities such as the local elastic coefficient or density. After multiple iterations, when the simulated echo approaches the measurement result, the possible stress level at each scanning position can be inferred, and then a preliminary stress distribution is formed in the three-dimensional coordinate system. At the same time, in order to make the subsequent stress calculation closer to the actual working conditions of the device, the surface temperature data needs to be collected synchronously. An infrared thermal imaging system, a micro-thermocouple, or an embedded temperature sensor array can be used to obtain the temperature values of each scanning point area and pair them with the preliminary stress results output by the inversion algorithm for storage. In this way, in the subsequent temperature compensation stage, the sound velocity can be corrected according to the true temperature of each position, ensuring that the stress distribution obtained in an environment with a multi-layer structure and a large temperature gradient will not be ignored or misestimated.

[0022] Specifically, after both the preliminary stress distribution and the surface temperature data are ready, a temperature-sound velocity relationship model needs to be called to refine the correction of the stress values at each grid point. This model is pre-established through experimental or literature data and contains the sound velocity change curve or parameter table of the material in different temperature ranges. The program first retrieves the surface temperature value corresponding to each point in the preliminary stress distribution, then finds the sound velocity correction coefficient in the model according to this temperature, and then makes a differential adjustment to the stress calculation result of this point. This process can be divided into point-by-point or batch processing, but each sampling point will finally obtain an updated stress value according to its temperature state. As the surface temperature of the device increases, the sound velocity often decreases. Without compensation, it will cause a deviation in the estimation of local stress. After traversal correction, the system outputs the corrected stress field in the form of three-dimensional data and generates a visual stress distribution map. Different colors or gray levels in the map correspond to the magnitude of the stress value, which can identify the areas where stress is relatively concentrated in the device and show the overall distribution and local non-uniformity. This three-dimensional stress distribution map can more accurately reflect the true mechanical state of the package structure in a non-uniform temperature field.

[0023] 102. Perform a frequency domain transformation on the three-dimensional stress distribution map to obtain frequency domain information, and perform a spatial domain transformation and correction on the frequency domain information through an improved inverse Fourier transform algorithm to obtain a microstructural model of the sintering interface; In one embodiment of the present invention, the frequency-domain conversion of the three-dimensional stress distribution map to obtain frequency-domain information, and the spatial-domain conversion and correction of the frequency-domain information through an improved inverse Fourier transform algorithm to obtain the microscopic structure model of the sintering interface include: performing a three-dimensional fast Fourier transform on the three-dimensional stress distribution map data to obtain frequency-domain information, and constructing a multi-layer interface transfer function according to the structural characteristics of the power semiconductor device; performing a convolution operation on the frequency-domain information and the multi-layer interface transfer function to obtain corrected frequency-domain data; applying a preset inverse Fourier transform algorithm to the corrected frequency-domain data, and reconstructing the preliminary microscopic structure of the sintering interface according to the inverse Fourier transform result; and optimizing the preliminary microscopic structure using a morphological algorithm to obtain the microscopic structure model of the sintering interface.

[0024] Specifically, after obtaining the three-dimensional stress distribution map data, it is necessary to load it as a three-dimensional matrix or voxel data into a numerical processing environment for discrete frequency-domain analysis on all spatial coordinates. To achieve this goal, a three-dimensional fast Fourier transform is first performed on the stress values in the three dimensions of x, y, and z, mapping the stress information originally in the spatial domain to the frequency domain. This operation can display the periodic change characteristics in each direction and the distribution intensity of different frequency components inside the device. During the transformation process, appropriate numbers of grid points and interpolation methods should be set according to the spatial resolution and size of the original data to avoid spectral aliasing or over-sampling. The obtained multi-dimensional frequency-domain information contains two key parts, amplitude and phase, which can indicate the overall trend of stress variation with spatial frequency. Subsequently, according to the structural characteristics of the power semiconductor device, it is necessary to construct a multi-layer interface transfer function to characterize the different attenuation characteristics of different materials such as the chip, sintering layer, and heat dissipation substrate for the propagation of acoustic and mechanical waves. This function usually takes the form of a tensor or matrix, containing parameters such as the acoustic impedance, thickness, and elastic constants of each layer of material, and is used for subsequent targeted correction of the frequency-domain data to make the analysis process better reflect the real multi-layer interface coupling effect.

[0025] When performing convolution operations on the obtained frequency-domain information and the multi-layer interface transfer function, the frequency-domain information is regarded as the input signal, and the multi-layer interface transfer function is regarded as the system response. The corrected frequency-domain data is obtained by means of complex multiplication and summation. This process is usually carried out based on the FFT convolution acceleration algorithm to maintain acceptable computational efficiency in a large-scale three-dimensional data environment. The purpose of the convolution operation is to integrate the comprehensive influence of each layer structure on the stress wave propagation and correct the energy changes caused by interface reflection, absorption, and scattering at the frequency domain level. If there are many material layers or characteristics, it is necessary to first assign independent propagation factors or weighting coefficients to each layer in the transfer function, and then stack them in an orderly manner during convolution. This can enable each frequency component to match the correct attenuation or phase shift law and reduce spectral distortion. After processing, the corrected frequency-domain data retains the initial frequency structure in the original three-dimensional stress distribution map and incorporates the changes of the multi-layer interface coupling to each frequency component, forming a frequency-domain representation closer to the physical characteristics of the device.

[0026] After obtaining the corrected frequency-domain data, it is necessary to apply a preset inverse Fourier transform algorithm to reconstruct the preliminary microstructure of the sintering interface. Compared with the traditional inverse transform, this algorithm combines the material properties and spatial stratification characteristics of the power semiconductor device to perform additional phase or amplitude correction for each frequency band. When performing the inverse transform, the frequency-domain data is gradually projected back onto the three-dimensional coordinate grid, and the gap between the reconstruction result and the device structure information is evaluated. If it is found that the reconstructed morphology does not match the expected physical characteristics in some areas, the algorithm will schedule improvement strategies to compensate for specific frequency components or interface coefficients. The correction behavior during the iteration process can reduce the distortion caused by measurement noise or numerical discretization, making the generated spatial-domain data more credible. After the main iteration is completed, the preliminary sintering interface morphology will appear in the three-dimensional coordinates, including details such as porous media, particle bonding sites, or local stress concentration areas, providing spatial objects for the next stage of structural optimization.

[0027] After the initial microstructure appears in three-dimensional coordinates, morphological algorithms are needed to further modify and refine the structure to obtain a more accurate sintering interface microstructure model. Morphological algorithms usually include operations such as erosion, dilation, opening, and closing. These operations screen the neighborhood relationships of voxels in three-dimensional data to remove local noise or fill small holes. For porous materials such as silver sintered layers, customized morphological processing strategies can be adopted, focusing on preserving the connectivity of the pore network while correcting stray particles or unreasonable protrusions. After updating each voxel position, the processing engine re-evaluates its neighborhood to ensure the continuity and recognizability of the overall structure. After morphological optimization, the pseudo-connections and discrete blocks remaining in the microstructure are removed, and the true pore morphology and particle boundaries are presented relatively smoothly. The finally output sintering interface microstructure model can be used as input for subsequent analysis or simulation, and the material property labels of each voxel are attached in the data file.

[0028] Further, applying a preset inverse Fourier transform algorithm to the corrected frequency-domain data and reconstructing the initial microstructure of the sintering interface according to the inverse Fourier transform result includes: dividing the frequency bands and processing the noise of the corrected frequency-domain data to obtain optimized complete frequency-domain data; performing a three-dimensional inverse Fourier transform on the optimized complete frequency-domain data to obtain initial spatial-domain data, and constructing a point cloud model of the sintering interface using the spatial-domain data; applying the Markov random field algorithm to the point cloud model to reconstruct the continuous structure of the sintering interface through an iterative optimization process to obtain an initial microstructure model; using a morphological processing algorithm to optimize the initial microstructure model to obtain the initial microstructure of the sintering interface.

[0029] Specifically, when dividing the frequency bands and processing the noise of the corrected frequency-domain data, the three-dimensional complex matrix needs to be segmented along the frequency axis to distinguish the amplitude and phase distributions in the low-frequency band, medium-frequency band, and high-frequency band respectively. In the implementation process, first read the matrix 、 、 The value range of each direction is obtained, and the modulus value of each frequency point is judged according to the preset segmentation threshold, and the elements in different intervals are classified into corresponding frequency sub-subsets. In order to accurately remove scattered noise, it is necessary to apply threshold filtering or adaptive smoothing to the frequency points in the outlier positions, and regard the points with extremely high or low amplitudes and isolated ones as noise interference. If there are still many scattered point clouds in the high-frequency and low-frequency band regions, a band-pass strategy can be used for secondary screening to make most of the energy concentrated in the frequency band with more obvious structure. During this process, it is necessary to perform filtering operations on both amplitude and phase at the same time to avoid only removing the amplitude outliers but retaining meaningless phase information. After processing, the obtained frequency-domain data will be saved in a compact manner to ensure that both the amplitude energy distribution and the phase continuity are within a controllable range. If it is necessary to quantify the frequency band division and noise processing effect, a comprehensive evaluation function can be defined ; where represents the frequency-domain value after segmentation and denoising, is the original matrix before processing. The smaller the sum of squares of the difference between the two in the global sense, the lower the degree of damage to the useful signal when completing the frequency band division and noise filtering. In specific implementation, it is necessary to combine the characteristic frequency bands of the device sintering layer and the typical distribution of noise interference, and select different thresholds and filtering algorithms for different frequency bands to ensure that while retaining the main structural information, random noise can be excluded as much as possible. The finally obtained optimized complete frequency-domain data will be used as the input source for the subsequent three-dimensional inverse Fourier transform and stored in a unified format in memory for data interaction with other calculation modules. When performing the three-dimensional inverse Fourier transform on the optimized complete frequency-domain data, it is necessary to first load the corresponding amplitude and phase information in the program and configure the window length and interpolation strategy of the inverse transform according to the dimensions of the three-dimensional grid. By calculating the exponential kernel function for each frequency point and superimposing them in the spatial domain, the stress distribution characteristics corresponding to the multi-layer material can be reconstructed. In specific implementation, the exponential multiplication operation will be performed on each lattice point combination one by one, and the results will be summed up to the spatial coordinate to generate a preliminary three-dimensional complex value field. This field represents the mapping result of the original frequency-domain data corrected by convolution in the spatial domain. The real part can be understood as the stress amplitude distribution corrected based on the interface propagation characteristics, and the imaginary part contains phase information and local coherence. After the inverse transform, a scalar field can be defined according to the absolute value or the real part, and high-gradient regions or typical texture features can be found in this scalar field. In order to facilitate the subsequent identification of the sintering interface position, this scalar field needs to be parsed into a scatter point set or an isosurface set. The scatter point set is usually stored in the form of where Represents the stress value at this point. This structure can intuitively retain the association between three-dimensional coordinates and strength. Based on this scatter point set, a point cloud model of the sintering interface can be constructed, thereby converting the field information output by the algorithm into a more intuitive geometric form expression. The point cloud model can display the regions within a specific threshold or range and indicate clues of interface concavity, convexity, pores, or uneven bonding. If the noise processing and inverse transformation are both perfect enough, the distribution of this point cloud will highly coincide with the spatial structure of the true interface of the device, providing more refined support for subsequent algorithms. When applying the Markov random field algorithm to this point cloud model, it is necessary to perform neighborhood modeling on the attributes of all scatter points in the spatial domain to maintain consistency at both the local and global levels. Set a neighborhood function to describe the connection relationship between a scatter point and several surrounding points, and then make the scatter point attributes include the position coordinates and the stress value . The Markov random field aims at the lowest overall potential energy, where the potential energy term consists of two parts: pairwise potential energy and single-point potential energy, and can be expressed as ; where represents the difference between the scatter point itself and the prior distribution, then penalizes the distance or stress difference between neighboring points. If the two differ too much in coordinates or stress values, it will increase the contribution to the overall potential energy. In actual implementation, by iteratively updating the scatter point labels or attributes, the locally mutated regions are smoothed while retaining the segmented features of the large-scale structure to ensure the continuity of the final sintering interface and the compatibility of adjacent regions. The algorithm will calculate the new potential energy value and judge whether it converges in each iteration. If the stopping condition is met, it is considered that the point set in this spatial domain has reached the Markov equilibrium. The output result includes the recalibrated coordinates and stresses, forming a preliminary microstructure model. This model shows the interface topological distribution obtained based on the principle of optimal statistical energy and can indicate the orientation of the sintering interface in three-dimensional space and the bonding or segmentation conditions of adjacent regions.

[0030] When optimizing the preliminary microstructure model using morphological processing algorithms, it is necessary to combine the porous characteristics of the material and the real interface geometry, and incorporate operations such as erosion, dilation, opening, and closing into the three-dimensional topological environment. In specific implementation, the scatter point model can be transformed into three-dimensional grid or voxel data. A structural element of a certain scale is set within the grid, and the neighborhood is scanned to determine whether a certain voxel should be removed or filled. If virtual fragments are seen at high-density pores, dilation or closing operations are used to merge these voids, and effective filling is performed when the defect scale does not exceed the threshold. If excessive adhesion occurs in the surface area, erosion or opening operations are applied to break the redundant bridges and make the local contour of the interface clearer. After the morphological processing, the obtained three-dimensional voxel distribution can be converted back into a scatter point set or a meshed surface, and compared with the previous Markov random field optimization results to verify whether there are unreasonable protrusions or discontinuous transitions in the overall structure in space. This comprehensive processing method can eliminate the noise patches left by the iterative algorithm, retain the real interface stratification characteristics, and make both the interface geometry and physical properties relatively smooth and orderly.

[0031] 103. Based on the microstructure model of the sintering interface, a three-dimensional geometric model including a chip, a sintering layer, and a heat dissipation substrate is established, and time-domain finite element analysis is performed according to the three-dimensional geometric model to obtain the thermal stress evolution data of the power semiconductor device under different working cycles; In an embodiment of the present invention, the method of establishing a three-dimensional geometric model including a chip, a sintering layer, and a heat dissipation substrate based on the microstructure model of the sintering interface and performing time-domain finite element analysis according to the three-dimensional geometric model to obtain the thermal stress evolution data of the power semiconductor device under different working cycles includes: constructing a three-dimensional geometric model including a chip, a sintering layer, and a heat dissipation substrate according to the microstructure model of the sintering interface, and assigning material properties to each part of the three-dimensional geometric model and defining the working conditions of the power semiconductor device; establishing a heat source model according to the defined working conditions, and inputting the three-dimensional geometric model, material properties, and heat source model into finite element analysis software; performing nonlinear transient thermo-mechanical coupling analysis through the finite element analysis software, calculating the temperature distribution and stress distribution at different time points, and extracting the thermal stress data at key positions according to the temperature distribution and stress distribution at different time points to generate the thermal stress evolution data of the power semiconductor device under different working cycles.

[0032] Specifically, according to the microscopic structure model of the sintering interface, it is first necessary to independently model the chip, sintering layer, and heat dissipation substrate in a computer-aided design environment. This modeling process usually starts with importing the geometric features identified in the microscopic structure, converting the pore distribution, surface undulation, and interlayer thickness of the sintering interface into three-dimensional geometric entities. This operation can be carried out by loading the shape information of each part in the microscopic structure with the help of a specific point cloud or mesh file format. After loading, the chip, sintering layer, and heat dissipation substrate are respectively encapsulated to ensure that the geometric association of adjacent components can be maintained at the assembly level. To ensure data consistency, it is necessary to set the origin and orientation of each part in the same coordinate system so that the layers in the overall model are aligned and fitted. After completing the geometric construction, the corresponding material properties can be specified for each part. In the numerical analysis interface, the chip can be marked as a semiconductor silicon or silicon carbide material, the sintering layer can be marked as a silver sintered composite material, and the heat dissipation substrate can be marked as a copper or aluminum nitride substrate, etc. Each material property needs to include basic parameters such as density, elastic modulus, thermal conductivity, and coefficient of thermal expansion, so that the finite element solver can use the correct material equations to describe the thermo-mechanical behavior of different regions. After completing the material configuration, it is necessary to define the working conditions according to the actual operating environment of the device, including external heating and heat dissipation paths, packaging peripheral constraints, and the heat generation level generated during the chip operation. If the device is in a periodic switching mode or pulse power mode, the pulse duration, duty cycle, and cycle information can be set at this stage so that the finite element analysis can correctly reflect the boundary changes and load application processes of the device at different times. The definition of working conditions can also apply mechanical constraints to specific parts, such as setting a constant temperature at the contact surface between the heat dissipation substrate and the external cooling system, restricting the displacement or rotational degrees of freedom in the wire bonding area, etc., to facilitate maintaining the structural integrity of the model during the analysis. All material properties and working conditions are stored in a parametric manner to ensure that the device behavior under different application scenarios can be simulated by changing the corresponding parameters in the subsequent stage.

[0033] Specifically, according to the defined working conditions, when constructing the heat source model, it is necessary to consider the functional characteristics of the device and the heat distribution characteristics generated inside the chip. If the device performs power conversion at a specific frequency, it is necessary to obtain the power loss value of each area on the chip through measurement or design specifications, and estimate its heat generation per unit time in combination with its surface area or volume ratio. For the heat conduction path between the sintered layer and the heat dissipation substrate, it is necessary to mark the coordinate area consistent with the medium transmission direction in the model, and regard this area as an important channel for heat transfer. The heat source model should also include a description of transient thermal effects. If the chip switches alternately in the pulse working mode, it is necessary to use the time domain function to define a power function that evolves over time in the analysis software, so that it can quickly increase the heat source intensity during the on period and return to zero during the off period. After completing the heat source description, the three-dimensional geometric model, material properties and heat source model are imported into the finite element analysis software. The software usually requires the specification of a meshing strategy, which decomposes the entire geometry into several units through automatic or custom meshing, and appropriately encrypts the local density based on the device geometry characteristics and stress distribution gradient. In order to ensure the accuracy of the calculation results in high temperature gradients or areas of significant stress concentration, it is necessary to select unit types that can adapt to nonlinear effects and make special treatments on the mesh smoothness of the interface between the sintered layer and the heat dissipation substrate. After the meshing is completed, the analysis software will apply the previously set material model and heat source load to each unit to prepare for the subsequent time-domain finite element analysis. In the input stage, you can also add the radiation or convection heat dissipation coefficient of the contact surface with the environment, and set the contact thermal resistance or bonding characteristics in the chip-sintered layer-substrate path so that the simulation reflects the interface thermal conductivity during the actual assembly process.

[0034] Specifically, when performing non-linear transient thermo-mechanical coupling analysis using finite element analysis software, it is necessary to set the initial values of the temperature field and stress field of the system at the initial moment so that the numerical solution evolves from a steady state or a set temperature level. Subsequently, the software solves the heat conduction equation and the equations of elasticity at each discrete time step, and introduces the coupling effect into the total stiffness matrix or the total iteration process, so that the temperature change has a direct impact on material expansion and stress distribution. Since the material properties of the sintered layer and the chip change significantly with increasing temperature, a non-linear material model can be selected to update the material properties according to the current temperature at each time step, and the incremental stress-strain relationship is called in the numerical solver. After completing one round of thermo-mechanical iteration, the software outputs the temperature field and stress field at the current moment, and records the temperature values and stress values at key positions or selected cross-sections. In order to obtain the thermo-stress evolution data under different working cycles, it is necessary to perform multiple rounds of time step advancement on the system according to the set pulse duration or period. After each cycle, a sequence of temperature-stress varying with time will be obtained. The analysis software can store these time series data in the post-processing module and allows automatic extraction of the peak and average values of the specified parts during the statistical process. If it is necessary to focus on specific elements in the sintered layer or the heat dissipation substrate, query statements can be added in the post-processing interface or script commands to read the temperature and stress information at each time step and output them as curves or tables. In this way, the stress evolution law of the device at different time periods under periodic loads or pulse modes can be obtained, and the moments of stress concentration or the regions with the most serious cumulative fatigue can be identified, thereby revealing the thermo-mechanical coupling effect experienced by the sintered layer of the power semiconductor device in the actual working state at the numerical level.

[0035] Furthermore, the execution of non-linear transient thermo-mechanical coupling analysis by the finite element analysis software, calculation of the temperature distribution and stress distribution at different time points, and extraction of the thermo-stress data at key positions according to the temperature distribution and stress distribution at different time points, generating the thermo-stress evolution data of the power semiconductor device under different working cycles includes: setting a non-linear material model and thermo-mechanical coupling control equations in the finite element analysis software, setting time discretization parameters and solution control parameters, and setting periodic thermal loads and mechanical constraint conditions according to the working characteristics of the power semiconductor device; using the established thermo-mechanical coupling equations, based on the set periodic thermal loads and mechanical constraint conditions, performing heat conduction analysis and thermo-stress analysis at each discrete time point, and obtaining the temperature field distribution and stress field distribution through the solution process; according to the obtained temperature field distribution and stress field distribution, extracting the nodal temperatures and stress values at predefined key positions at each time step, and generating a continuous thermo-stress evolution curve based on the nodal temperatures and stress values through data interpolation and smoothing processing; using the Fourier analysis method to perform spectral decomposition on the thermo-stress evolution curve, identifying the main stress periods and amplitude characteristics, and obtaining the thermo-stress evolution data of the power semiconductor device under different working cycles.

[0036] Specifically, when setting up nonlinear material models and thermo-mechanical coupling control equations in finite element analysis software and specifying time discretization and solution control parameters, it is necessary to first import the three-dimensional geometric mesh and material properties obtained in the early stage so as to allocate physical quantities such as density, heat capacity, thermal conductivity, elastic modulus and thermal expansion coefficient at the unit level. Nonlinear material models often use elastic-plastic or temperature-dependent types, and incorporate thermoelasticity and potential plastic deformation into unit stress calculations. Since power semiconductor devices will have significant thermal stress gradients in the chip and sintering layer areas, the thermo-mechanical coupling equations need to include heat conduction terms and volume force terms, and activate the dynamic adjustment function of temperature to the material Young's modulus and yield limit in the model. When setting time discretization, an implicit integration scheme can be used to divide the entire loading process into several discrete time steps, and set the cycle duration and pause interval for pulse power or periodic heat loads. In order to adapt to possible temperature rise and stress mutations, it is necessary to open the Newton-Raphson iteration and convergence criterion adjustment functions in the solution control parameters, and ensure that the setting of mechanical constraints is consistent with the chip packaging method. If the chip support surface is fixed to the edge of the substrate or the heat sink, it is necessary to apply corresponding displacement boundary constraints in the model and define the forced convection or radiation heat transfer coefficient at the thermal boundary. The periodic heat load can be input to the top of the chip or a specific hot spot area through a time-varying function. Mechanical constraints can be applied to the contact pair between the sintered layer and the heat dissipation substrate to simulate the possible slip between the interfaces under high temperature conditions. After completing the above parameter and equation configuration, the software will automatically assemble the discretized equation group to lay a numerical foundation for the subsequent calculation of the coupling effect of heat diffusion and mechanical response.

[0037] Using the established thermal-mechanical coupling equations and based on the set periodic thermal loads and mechanical constraints, heat conduction analysis and thermal stress analysis need to be performed simultaneously at each discrete time point. Heat conduction analysis usually refers to the governing equations: ; in represents density, represents the specific heat capacity, represents the thermal conductivity that varies with temperature, represents the internal heat source term under the interaction of temperature and stress. The mechanical response part may use the thermoelastic stress-strain relationship through the equilibrium equation To define the overall mechanical equilibrium condition, Contains a stress tensor coupled with temperature. In each time step, the software first updates the material parameters with the current temperature field, and then solves the elastoplastic stress field at the sub-iteration level. If the convergence criterion is met, it enters the next time step; otherwise, it automatically adjusts the tangent stiffness according to the Newton iteration method. The periodic thermal load means that different powers are applied to the chip at different time periods, and the analyzer will accordingly change the local temperature field distribution in the model. If a time step is on the rising edge, the temperature rises rapidly and causes thermal expansion, thus forming a large shear stress at the interface between the sintered layer and the heat dissipation substrate; if it is on the falling edge, the local temperature begins to decrease and reverse contraction occurs, reflecting the fatigue effect brought by the thermal cycle. After the software completes the entire set of time steps, it will output the temperature field and stress field results for each time period and store them in a data file or a post-processing module for subsequent node extraction and interpolation processing.

[0038] According to the temperature field and stress field distributions obtained during the solution process, it is necessary to extract the node temperatures and stress values at predefined key positions in each time step, and convert the discrete data sequence into a continuous thermal stress evolution curve through interpolation and smoothing processing. The extraction process is usually completed by a post-processing script or a visualization interface. Specify several node or element centers as observation points, traverse the temperature values and principal stress values or shear stress values recorded in the time step, and then arrange them in chronological order in the same curve graph. If the discrete time steps are too sparse, cubic spline or Kriging interpolation methods can be selected to smooth the data between adjacent times to avoid obvious broken lines or jumps on the image. After the processing is completed, multiple comparison curves will be generated, reflecting the evolution process of the stress magnitudes at each key position under the application of periodic thermal loads. If you need to view the differences between different positions, multiple curves can be superimposed on the time axis to identify which regions have the most prominent thermal stress peaks and also observe whether there is a lag or phase shift in the stress within the same cycle. Some analysis software allows these curves to be directly output as numerical files for subsequent feature extraction or other algorithm use. Through the continuous thermal stress evolution curve, the dynamic effects of thermo-mechanical coupling on the overall and local regions of the device can be discovered, and the cumulative load distribution suffered by the material during multi-cycle operation can be evaluated.

[0039] When using the Fourier analysis method to perform spectral decomposition on this thermal stress evolution curve, it is necessary to first perform a sampling check on the curve and select an appropriate sampling frequency to perform discrete Fourier transform or fast Fourier transform on the stress time series of multiple cycles. In the operation, the time-domain data will be mapped to the frequency domain, and in the calculation formula: ; where, represents the amplitude value of the stress curve at time , represents the angular frequency, Denote the total number of sampling points. The output results will show the positions and amplitude sizes of the main harmonic peaks in the spectrogram. If the device is most severely thermally shocked at a specific period or harmonic, the corresponding peak will be significantly enhanced in the spectrum. This analysis can quantify the main frequency components and high-order harmonic intensities of the stress over time, and clarify how the amplitude characteristics change with the increase in the number of cycles. In a periodic load pattern, if the pulse width or duty cycle is fixed, the common spectral peak positions are strongly correlated with the pulse characteristics. Comparing the spectral results of multiple time periods or different node curves can reveal the differences in the main stress periods and components of different parts of the device, providing a directional basis for future fatigue life judgment or design improvement. Finally, the information on the main stress period, amplitude, and harmonic coefficient will be retained in the output file or report to construct the thermal stress evolution data of the power semiconductor device under different operating cycles.

[0040] 104. Use the three-dimensional stress distribution map, the microscopic structure model of the sintering interface, and the thermal stress evolution data to construct a multi-dimensional feature space, input the features of the multi-dimensional feature space into a preset discrimination model, and obtain a quantitative evaluation result of the sintering quality of the power semiconductor device.

[0041] In one embodiment of the present invention, the use of the three-dimensional stress distribution map, the microscopic structure model of the sintering interface, and the thermal stress evolution data to construct a multi-dimensional feature space, input the features of the multi-dimensional feature space into a preset discrimination model, and obtain a quantitative evaluation result of the sintering quality of the power semiconductor device includes: extracting statistical features, morphological analysis features, and time series analysis features from the three-dimensional stress distribution map, the microscopic structure model of the sintering interface, and the thermal stress evolution data respectively, and combining them to form a multi-dimensional feature vector; performing normalization processing on the multi-dimensional feature vector, constructing a standardized multi-dimensional feature space, and inputting the features of the multi-dimensional feature space into a pre-trained deep neural network discrimination model; obtaining a preliminary evaluation result of the sintering quality through the output layer of the deep neural network discrimination model, and combining with a predefined quality grade standard to convert the preliminary evaluation result into a quantitative sintering quality score.

[0042] Specifically, the three-dimensional stress distribution map usually stores local stress values in the form of grids or voxels. Statistical operations can be performed on the stress amplitude, stress gradient, stress concentration degree, etc. of each node or voxel, such as indicators like mean, variance, kurtosis, and skewness, to reflect the dispersion and concentration trend of local stress in the spatial distribution. The sintering interface microstructure model contains the pore morphology and interface connection conditions of the material, and geometric scale features need to be obtained from it through morphological analysis methods. For example, in a porous structure, the porosity, pore distribution uniformity, and pore connectivity can be calculated; in the particle arrangement area, the particle size, aspect ratio, and shape index can be quantitatively evaluated. Morphological analysis can combine information such as the flatness, depression depth, and critical thickness of each interlayer interface to identify potential defects or irregular areas in the feature set. The thermal stress evolution data contains the temperature field and stress field sequences at different time steps or cycles, and time series analysis features need to be derived from it. The mean square variation, extreme difference, and stress amplitude distribution occurring within the number of cycles can be used to describe the law of temperature and stress changing with time. If there are obvious peak-valley phenomena in the pulse or periodic load, the peak height, peak interval, and rising slope can be recorded, and the repeatability of multiple cycles can be evaluated. This method is beneficial for revealing the stress fatigue accumulation process. After combining the above statistical features, morphological analysis features, and time series analysis features, a multi-dimensional feature vector will be formed. Names and indexes can be assigned to each feature, and they can be arranged in the same data structure in the form of vectors or arrays, enabling subsequent algorithms to uniformly process different dimensional features of the same device sample. To avoid redundancy, a correlation screening or dimensionality reduction operation needs to be performed on highly correlated or redundant features to reduce the overfitting risk caused by the high-dimensional space.

[0043] Specifically, after the multi-dimensional feature vectors are generated, it is necessary to normalize the features from different sources and with different dimensions to avoid biases in network training caused by differences in the order of magnitude or units of the features. The normalization operation can adopt linear stretching, z-score standardization or wavelet transform methods to project each eigenvalue into the same numerical range or distribution. If some features are extremely discrete or have an obvious skewed distribution, logarithmic transformation or power transformation can be performed first, and then the standardization step can be executed to enhance the symmetry and usability of the overall feature distribution. After normalization, each feature in the sample is at an approximately unified scale. At this time, they can be combined into a standardized multi-dimensional feature space to form a matrix or tensor structure. The rows or columns of this structure indicate samples at different devices, different regions or different times, and the other dimension corresponds to the selected feature indicators. The pre-trained deep neural network discrimination model usually includes multiple hidden layers and non-linear activation units, and can automatically capture complex feature associations from high-dimensional data. To achieve this goal, it is necessary to first call the trained network weight and bias parameters, and input the normalized multi-dimensional feature space into the input layer of the network one by one or in batches. The network will perform linear and non-linear composite operations between the hidden layers, gradually refining more discriminative internal representations, and generating an output vector with one or several dimensions at the output layer. If the model goal is to distinguish different levels of sintering quality, the output layer can be the probabilities of multiple neurons corresponding to each level, or directly output a numerical value representing the confidence level of the goodness. The calculation process of the deep network will combine the learning experience on a large number of training samples in the early stage, perform weighted summation and hierarchical mapping on the input features, and complete non-linear transformation with the cooperation of the activation function. This can discover some hidden laws that are difficult to directly detect by the human eye on the basis of the standardized feature space, and enhance the sensitivity to sintering defects, local overstress and microstructural abnormalities.

[0044] Specifically, the output layer of the discriminant model will produce an original result related to the sintering quality, which may be a continuous value or multiple classification probabilities. If the output is a continuous value, it can be regarded as a score of the overall quality level; if the output is multiple class probabilities, the category corresponding to the maximum probability can be selected in post-processing as a preliminary evaluation. After obtaining this preliminary result, it is necessary to correspond or convert it to a more practical score value with the quality grade standard established in advance. Assuming that the quality grade standard is composed of intervals or thresholds, the grade of the device sintering quality can be determined according to the interval where the output value is located, or an interpolation or nonlinear mapping method can be used to assign it a more flexible score. If a more detailed evaluation is to be achieved, a multi-level mapping strategy can also be designed to compare the network output with multiple grade curves, find the corresponding position on each curve and make a comprehensive assessment, and finally generate a quantitative score. For example, the score can be divided into several intervals in the range of 0 to 100, and the high segment corresponds to the high-quality sintering state, while the low segment indicates the problem of poor interface bonding strength or excessive stress concentration. Unlike simple binary classification, this quantitative scoring can better reflect the differences between devices under different processes or test conditions, and facilitate fine-grained quality management in engineering practice. In actual implementation, it is necessary to compare the preliminary evaluation values ​​output by the model with the predefined standards, and complete this mapping step in the algorithm or database. Many systems will visualize the score together with other detection indicators, allowing users to view specific values ​​and grade judgments on the interface. If the score is too low, it is possible to further trace which features are closely related to the low score to confirm the location and degree of sintering defects. At this point, the entire deep neural network discrimination process can quantitatively describe the sintering state of the package based on three-dimensional stress distribution, microstructure and thermal stress evolution data, and output numerical evaluation results that are easy for operators to understand and make decisions.

[0045] In this embodiment, high-frequency acoustic microscopy technology is used for non-destructive scanning, and correction is performed in combination with the temperature-sound velocity relationship model to achieve real-time monitoring of the sintering process and solve the problem of being unable to capture transient changes. Through frequency domain conversion and improved inverse Fourier transform algorithm, accurate reconstruction of the microstructure of the sintering interface is achieved, overcoming the limitation that the prior art is difficult to evaluate the microstructure. Based on the reconstructed microstructure, a detailed three-dimensional geometric model is established and time-domain finite element analysis is performed to obtain comprehensive thermal stress evolution data, making up for the lack of surface information of traditional methods. Quantitative evaluation is performed using multi-dimensional feature space and preset discriminant models to achieve a comprehensive analysis of the sintering quality and overcome the lack of comprehensive quantitative evaluation capabilities. Through the organic combination of steps, this method significantly improves the accuracy and comprehensiveness of package sintering evaluation.

[0046] The above describes the method for evaluating the encapsulation sintering of a power semiconductor device in an embodiment of the present invention. Next, the apparatus for evaluating the encapsulation sintering of a power semiconductor device in an embodiment of the present invention will be described. Please refer to Figure 2 An embodiment of the apparatus for evaluating the encapsulation sintering of a power semiconductor device in an embodiment of the present invention includes: A stress monitoring module 201, configured to perform non-destructive scanning calculations on the power semiconductor device using high-frequency acoustic microscopy technology to obtain preliminary stress distribution data of the power semiconductor device, and use the synchronously recorded device surface temperature distribution and a pre-established temperature-sound velocity relationship model to perform temperature compensation and correction on the preliminary stress distribution data to obtain a three-dimensional stress distribution map; A structure reconstruction module 202, configured to perform frequency domain conversion on the three-dimensional stress distribution map to obtain frequency domain information, and perform spatial domain conversion and correction on the frequency domain information through an improved inverse Fourier transform algorithm to obtain a microscopic structure model of the sintering interface; A thermal analysis module 203, configured to establish a three-dimensional geometric model including a chip, a sintering layer, and a heat dissipation substrate based on the microscopic structure model of the sintering interface, and perform time-domain finite element analysis according to the three-dimensional geometric model to obtain thermal stress evolution data of the power semiconductor device under different operating cycles; A quality evaluation module 204, configured to construct a multi-dimensional feature space using the three-dimensional stress distribution map, the microscopic structure model of the sintering interface, and the thermal stress evolution data, and input the features of the multi-dimensional feature space into a preset discrimination model to obtain a quantitative evaluation result of the sintering quality of the power semiconductor device.

[0047] In an embodiment of the present invention, the apparatus for evaluating the encapsulation sintering of the power semiconductor device runs the above method for evaluating the encapsulation sintering of the power semiconductor device. The apparatus for evaluating the encapsulation sintering of the power semiconductor device uses high-frequency acoustic microscopy technology for non-destructive scanning and combines with a temperature-sound velocity relationship model for correction to achieve real-time monitoring of the sintering process and solve the problem of inability to capture transient changes. Through frequency domain conversion and an improved inverse Fourier transform algorithm, the accurate reconstruction of the microscopic structure of the sintering interface is realized, overcoming the limitation of the prior art in difficult evaluation of the microscopic structure. Based on the reconstructed microscopic structure, a detailed three-dimensional geometric model is established and time-domain finite element analysis is performed to obtain comprehensive thermal stress evolution data, making up for the deficiency of surface information in traditional methods. Using a multi-dimensional feature space and a preset discrimination model for quantitative evaluation realizes a comprehensive analysis of the sintering quality and overcomes the defect of lack of comprehensive quantitative evaluation ability. Through the organic combination of steps, this method significantly improves the accuracy and comprehensiveness of the encapsulation sintering evaluation.

[0048] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, or units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0049] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0050] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or equivalently replace some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for evaluating the encapsulation sintering of a power semiconductor device, characterized in that, The method for evaluating the encapsulation sintering of a power semiconductor device includes: Performing non-destructive scanning calculation on the power semiconductor device using high-frequency acoustic microscopy technology to obtain preliminary stress distribution data of the power semiconductor device, and using the synchronously recorded surface temperature distribution of the device and the pre-established temperature-sound velocity relationship model to perform temperature compensation correction on the preliminary stress distribution data to obtain a three-dimensional stress distribution map; Performing frequency domain conversion on the three-dimensional stress distribution map to obtain frequency domain information, and performing spatial domain conversion and correction on the frequency domain information through an improved inverse Fourier transform algorithm to obtain a microscopic structure model of the sintering interface; Based on the microscopic structure model of the sintering interface, establishing a three-dimensional geometric model including a chip, a sintering layer, and a heat dissipation substrate, and performing time-domain finite element analysis according to the three-dimensional geometric model to obtain thermal stress evolution data of the power semiconductor device under different working cycles; Using the three-dimensional stress distribution map, the microscopic structure model of the sintering interface, and the thermal stress evolution data to construct a multi-dimensional feature space, and inputting the features of the multi-dimensional feature space into a preset discrimination model to obtain a quantitative evaluation result of the sintering quality of the power semiconductor device.

2. The method for evaluating the encapsulation sintering of a power semiconductor device according to claim 1, wherein, The performing non-destructive scanning calculation on the power semiconductor device using high-frequency acoustic microscopy technology to obtain preliminary stress distribution data of the power semiconductor device, and using the synchronously recorded surface temperature distribution of the device and the pre-established temperature-sound velocity relationship model to perform temperature compensation correction on the preliminary stress distribution data to obtain a three-dimensional stress distribution map includes: Performing high-frequency acoustic wave scanning on the power semiconductor device using high-frequency acoustic microscopy technology to obtain an original acoustic wave signal; Performing time-domain analysis and frequency domain transformation on the original acoustic wave signal to obtain acoustic wave propagation characteristic data; According to the acoustic wave propagation characteristic data, using an acoustic inversion algorithm to calculate and obtain preliminary stress distribution data, and collecting the temperature distribution data on the surface of the power semiconductor device; Inputting the preliminary stress distribution data and the temperature distribution data into the pre-established temperature-sound velocity relationship model, performing temperature compensation calculation on the preliminary stress distribution data, and generating a three-dimensional stress distribution map according to the temperature compensation calculation result.

3. The method for evaluating the encapsulation sintering of a power semiconductor device according to claim 1, wherein The performing frequency domain conversion on the three-dimensional stress distribution map to obtain frequency domain information, and performing spatial domain conversion and correction on the frequency domain information through an improved inverse Fourier transform algorithm to obtain a microscopic structure model of the sintering interface includes: Performing three-dimensional fast Fourier transform on the three-dimensional stress distribution map data to obtain frequency domain information, and constructing a multi-layer interface transfer function according to the structural characteristics of the power semiconductor device; Performing convolution operation on the frequency domain information and the multi-layer interface transfer function to obtain corrected frequency domain data; Applying a preset inverse Fourier transform algorithm to the corrected frequency domain data, and reconstructing the preliminary microscopic structure of the sintering interface according to the inverse Fourier transform result; Using a morphological algorithm to optimize the preliminary microscopic structure to obtain a microscopic structure model of the sintering interface.

4. The method for evaluating the package sintering of a power semiconductor device according to claim 3, wherein The applying a preset inverse Fourier transform algorithm to the corrected frequency domain data, and reconstructing the preliminary microscopic structure of the sintering interface according to the inverse Fourier transform result includes: Perform frequency band division and noise processing on the corrected frequency domain data to obtain optimized complete frequency domain data; Perform three-dimensional inverse Fourier transform on the optimized complete frequency domain data to obtain preliminary spatial domain data, and use the spatial domain data to construct a point cloud model of the sintering interface; Apply the Markov random field algorithm to the point cloud model, and reconstruct the continuous structure of the sintering interface through an iterative optimization process to obtain a preliminary microstructure model; Optimize the preliminary microstructure model using a morphological processing algorithm to obtain the preliminary microstructure of the sintering interface.

5. The method for evaluating the package sintering of a power semiconductor device according to claim 1, wherein Based on the microstructure model of the sintering interface, establish a three-dimensional geometric model including a chip, a sintering layer, and a heat dissipation substrate, and perform time-domain finite element analysis according to the three-dimensional geometric model to obtain the thermal stress evolution data of the power semiconductor device under different working cycles, including: According to the microstructure model of the sintering interface, construct a three-dimensional geometric model including a chip, a sintering layer, and a heat dissipation substrate, and assign material properties to each part of the three-dimensional geometric model and define the working conditions of the power semiconductor device; According to the defined working conditions, establish a heat source model, and input the three-dimensional geometric model, material properties, and heat source model into finite element analysis software; Perform a nonlinear transient thermo-mechanical coupling analysis through the finite element analysis software, calculate the temperature distribution and stress distribution at different time points, and extract the thermal stress data at key positions according to the temperature distribution and stress distribution at different time points to generate the thermal stress evolution data of the power semiconductor device under different working cycles.

6. The evaluation method for the encapsulation sintering of the power semiconductor device according to claim 1, characterized in that, The nonlinear transient thermo-mechanical coupling analysis is performed through the finite element analysis software, the temperature distribution and stress distribution at different time points are calculated, and the thermal stress data at key positions are extracted according to the temperature distribution and stress distribution at different time points to generate the thermal stress evolution data of the power semiconductor device under different working cycles, including: Set a nonlinear material model and a thermo-mechanical coupling control equation in the finite element analysis software, set time discretization parameters and solution control parameters, and set periodic thermal loads and mechanical constraint conditions according to the working characteristics of the power semiconductor device; Use the established thermo-mechanical coupling equations, based on the set periodic thermal loads and mechanical constraint conditions, perform heat conduction analysis and thermal stress analysis for each discrete time point, and obtain the temperature field distribution and stress field distribution through the solution process; According to the obtained temperature field distribution and stress field distribution, extract the node temperature and stress values at predefined key positions at each time step, and generate a continuous thermal stress evolution curve based on the node temperature and stress values through data interpolation and smoothing processing; Use the Fourier analysis method to perform spectral decomposition on the thermal stress evolution curve, identify the main stress periods and amplitude characteristics, and obtain the thermal stress evolution data of the power semiconductor device under different working cycles.

7. The method for evaluating the encapsulation sintering of a power semiconductor device according to claim 1, characterized in that Using the three-dimensional stress distribution diagram, the microstructure model of the sintering interface, and the thermal stress evolution data, construct a multi-dimensional feature space, and input the features of the multi-dimensional feature space into a preset discrimination model to obtain a quantitative evaluation result of the sintering quality of the power semiconductor device, including: Extract statistical features, morphological analysis features, and time series analysis features from the three-dimensional stress distribution diagram, the microscopic structure model of the sintering interface, and the thermal stress evolution data respectively, and combine them to form a multi-dimensional feature vector; Normalize the multi-dimensional feature vector, construct a standardized multi-dimensional feature space, and input the features of the multi-dimensional feature space into a pre-trained deep neural network discrimination model; Obtain a preliminary evaluation result of the sintering quality through the output layer of the deep neural network discrimination model, and combine it with a predefined quality grade standard to convert the preliminary evaluation result into a quantitative sintering quality score.

8. An encapsulation sintering evaluation device for a power semiconductor device, characterized in that, The packaging sintering evaluation device for the power semiconductor device includes: A stress monitoring module, which is used to perform non-destructive scanning calculation on the power semiconductor device by using high-frequency acoustic microscopy technology to obtain preliminary stress distribution data of the power semiconductor device, and use the synchronously recorded device surface temperature distribution and a pre-established temperature-velocity of sound relationship model to perform temperature compensation correction on the preliminary stress distribution data to obtain a three-dimensional stress distribution diagram; A structure reconstruction module, which is used to perform frequency domain conversion on the three-dimensional stress distribution diagram to obtain frequency domain information, and perform spatial domain conversion and correction on the frequency domain information through an improved inverse Fourier transform algorithm to obtain a microscopic structure model of the sintering interface; A thermal analysis module, which is used to establish a three-dimensional geometric model including a chip, a sintering layer, and a heat dissipation substrate based on the microscopic structure model of the sintering interface, and perform time-domain finite element analysis according to the three-dimensional geometric model to obtain thermal stress evolution data of the power semiconductor device under different working cycles; A quality evaluation module, which is used to construct a multi-dimensional feature space by using the three-dimensional stress distribution diagram, the microscopic structure model of the sintering interface, and the thermal stress evolution data, input the features of the multi-dimensional feature space into a preset discrimination model, and obtain a quantitative evaluation result of the sintering quality of the power semiconductor device.

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