Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same, including: providing a stacked wafer, wherein each layer of wafers in the stacked wafers includes a stacked semiconductor substrate and an isolation layer; forming a groove in a dicing path of the stacked wafer, forming an insulating layer and a conductive structure embedded in the insulating layer in the groove, wherein the conductive structure extends from the topmost wafer in the stacked wafers to the bottommost wafer in the stacked wafers along the thickness direction of the stacked wafers; cutting the stacked wafers, wherein the static electricity generated by cutting each layer of the wafers is conducted away through the conductive structure. The present invention increases a conductive channel through a conductive structure, conducts away the static charge of the top wafer and the middle wafer, reduces white noise, and avoids breakdown of the static electricity ring on the wafer.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] There is a wafer cutting process in the back-end of the wafer, and the wafer cutting process includes, for example, wafer dicing (dividing into chips) or wafer trimming process. The wafer includes a semiconductor substrate and an isolation layer located on the semiconductor substrate. During the cutting process, a large amount of electrostatic charge will be generated due to the friction between the cutting tool and the semiconductor substrate (silicon wafer). Generally, the machine will have a channel to conduct away the charge, and the charge will be conducted away through the contact between the semiconductor substrate and the chuck that fixes the wafer. For more than two stacked wafers, each wafer includes a semiconductor substrate and an isolation layer located on the semiconductor substrate. The isolation layer is non-conductive, which causes a large amount of charge to remain in the topmost or middle layer of the wafer that does not contact the chuck. The charge generated by friction during the cutting process of the stacked wafers causes white noise problems and may even break down the electrostatic ring on the wafer. Summary of the invention

[0003] The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which increases a conductive channel, conducts away the static charge of a top wafer and an intermediate wafer, reduces white noise, and avoids breakdown of the static ring on the wafer.

[0004] The present invention provides a method for manufacturing a semiconductor device, comprising:

[0005] Providing a stacked wafer, wherein each layer of wafer in the stacked wafer comprises a stacked semiconductor substrate and an isolation layer;

[0006] Forming a groove in a scribe line of the stacked wafer, forming an insulating layer and a conductive structure embedded in the insulating layer in the groove, wherein the conductive structure extends from a topmost wafer in the stacked wafer to a bottommost wafer along a thickness direction of the stacked wafer;

[0007] The stacked wafers are cut, and static electricity generated by cutting each layer of the wafers is conducted away through the conductive structure.

[0008] Further, the scribing lanes include a plurality of first scribing lanes extending along a first direction and a plurality of second scribing lanes extending along a second direction, and the first direction is perpendicular to the second direction;

[0009] The conductive structure includes a first conductive strip distributed along the first direction within the first dicing lane and a plurality of first extension portions extending from the first conductive strip at intervals, wherein the first extension portions are distributed along the second direction; the first conductive strip and the plurality of first extension portions extend from the topmost wafer in the stacked wafer to the bottommost wafer along the thickness direction of the stacked wafer.

[0010] Furthermore, the conductive structure also includes a second conductive strip distributed along the second direction within the second dicing street and a plurality of second extension portions extending from the second conductive strip at intervals, and the second extension portions are distributed along the first direction; the second conductive strip and the plurality of second extension portions extend from the topmost wafer in the stacked wafer to the bottommost wafer along the thickness direction of the stacked wafer.

[0011] Furthermore, when the stacked wafers are cut in the first dicing lane, the first actual cutting area covers a plurality of the first extensions, and static electricity generated by cutting each layer of the wafers is transferred from the plurality of the first extensions to the first conductive strips and conducted away.

[0012] Furthermore, the material of the conductive structure includes at least one of aluminum, copper and tungsten.

[0013] Further, forming a conductive structure embedded in the insulating layer in the groove includes:

[0014] forming a groove, wherein the groove is formed in the insulating layer by a photolithography process;

[0015] forming a conductive structure, the conductive structure filling the groove and covering the surface of the stacked wafer;

[0016] A chemical mechanical polishing process is performed to remove the conductive structure located on the surface of the stacked wafer.

[0017] The present invention also provides a semiconductor device, comprising:

[0018] A stacked wafer, wherein each layer of the stacked wafer comprises a stacked semiconductor substrate and an isolation layer;

[0019] A groove is formed in the dicing lane of the stacked wafer, an insulating layer and a conductive structure embedded in the insulating layer are formed in the groove, and the conductive structure extends from the topmost wafer in the stacked wafer to the bottommost wafer along the thickness direction of the stacked wafer.

[0020] Further, the scribing lanes include a plurality of first scribing lanes extending along a first direction and a plurality of second scribing lanes extending along a second direction, and the first direction is perpendicular to the second direction;

[0021] The conductive structure includes a first conductive strip distributed along the first direction in the first scribe line and a plurality of first extension portions extending from the first conductive strip at intervals; and a second conductive strip distributed along the second direction in the second scribe line and a plurality of second extension portions extending from the second conductive strip at intervals.

[0022] The present invention provides another method for manufacturing a semiconductor device, comprising:

[0023] Providing a stacked wafer, wherein each layer of wafer in the stacked wafer comprises a stacked semiconductor substrate and an isolation layer;

[0024] Pasting a conductive tape on the edge of the stacked wafers, wherein the conductive tape extends from the topmost wafer in the stacked wafers to the bottommost wafer along the thickness direction of the stacked wafers;

[0025] The stacked wafers are cut, and static electricity generated by cutting each layer of the wafers is conducted away through the conductive tape.

[0026] Furthermore, the conductive tape includes a conductive metal and an adhesive layer located on the surface of the conductive metal.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The present invention provides a semiconductor device and a method for manufacturing the same, including: providing a stacked wafer, wherein each layer of wafers in the stacked wafers includes a stacked semiconductor substrate and an isolation layer; forming a groove in a dicing path of the stacked wafer, forming an insulating layer and a conductive structure embedded in the insulating layer in the groove, wherein the conductive structure extends from the topmost wafer in the stacked wafers to the bottommost wafer in the stacked wafers along the thickness direction of the stacked wafers; cutting the stacked wafers, wherein the static electricity generated by cutting each layer of the wafers is conducted away through the conductive structure. The present invention increases a conductive channel through a conductive structure, conducts away the static charge of the top wafer and the middle wafer, reduces white noise, and avoids breakdown of the static electricity ring on the wafer.

[0029] The present invention provides another method for manufacturing a semiconductor device, comprising: providing a stacked wafer, wherein each layer of wafers in the stacked wafers comprises a stacked semiconductor substrate and an isolation layer; pasting a conductive tape on the edge of the stacked wafer, wherein the conductive tape extends from the topmost wafer in the stacked wafers to the bottommost wafer along the thickness direction of the stacked wafers; and cutting the stacked wafers, wherein the static electricity generated by cutting each layer of the wafers is conducted away through the conductive tape. The present invention increases a conductive channel by using the conductive tape to conduct away the static charge of the top wafer and the middle wafer, thereby reducing white noise and avoiding breakdown of the static electricity ring on the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The figure is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0031] Figure 2 FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0032] Figure 3FIG. 1 is a top view of a semiconductor device dicing area according to an embodiment of the present invention.

[0033] Figure 4 FIG. 4 is a schematic diagram of cutting a semiconductor device according to an embodiment of the present invention.

[0034] Figure 5 FIG. 4 is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present invention.

[0035] The reference numerals are as follows:

[0036] C-chuck; 10-stacked wafer; 11a, 12a, 1Na-semiconductor substrate; 11b, 12b, 1Nb-isolation layer; 20-conductive tape; 30-second actual cutting area; 40-insulating layer; 50-conductive structure; 51-first conductive strip; 52-first extension; 53-second conductive strip; 54-second extension; X-first direction; Y-second direction; V-groove; S1-first dicing lane; S2-second dicing lane. DETAILED DESCRIPTION

[0037] Based on the above research, an embodiment of the present invention provides a semiconductor device and a method for manufacturing the same. The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the drawings are all in a very simplified form and use an inaccurate scale, which is only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0038] For ease of description, some embodiments of the present application may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "below" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first", "second", etc. below are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate.

[0039] The embodiment of the present invention provides a method for manufacturing a semiconductor device, such as Figure 1 As shown, including:

[0040] Step S1, providing a stacked wafer, wherein each layer of wafer in the stacked wafer includes a stacked semiconductor substrate and an isolation layer;

[0041] Step S2, forming a groove in the dicing lane of the stacked wafer, forming an insulating layer and a conductive structure embedded in the insulating layer in the groove, wherein the conductive structure extends from the topmost wafer in the stacked wafer to the bottommost wafer along the thickness direction of the stacked wafer;

[0042] Step S3, cutting the stacked wafers, and conducting (releasing) the static electricity generated by cutting each layer of the wafers through the conductive structure.

[0043] Combine the following Figures 2 to 4 The steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention are introduced.

[0044] like Figure 2 As shown, a stacked wafer 10 is provided, each layer of wafer in the stacked wafer 10 includes a stacked semiconductor substrate and an isolation layer, and the stacked wafer has at least two layers of wafers. Exemplarily, the stacked wafer 10 includes a bottom wafer (first layer wafer), a second layer wafer to a top wafer (Nth layer wafer). The bottom wafer includes a semiconductor substrate 11a and an isolation layer 11b located on the semiconductor substrate 11a; the second layer wafer includes a semiconductor substrate 12a and an isolation layer 12b located on the semiconductor substrate 12a; the top wafer includes a semiconductor substrate 1Na and an isolation layer 1Nb located on the semiconductor substrate 1Na.

[0045] A groove V is formed in the dicing street of the stacked wafer 10. Specifically, a patterned photoresist layer (not shown) is formed on the surface of the stacked wafer 10, an opening corresponding to the groove V is formed in the patterned photoresist layer, and the stacked wafer 10 is etched using the patterned photoresist layer as a mask to form the groove V in the dicing street of the stacked wafer 10.

[0046] An insulating layer 40 is formed in the trench V. Specifically, the insulating layer 40 may be formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. The insulating layer 40 may be made of a high dielectric constant material such as silicon nitride (SiN), silicon dioxide (SiO2), hafnium oxide (HfO), zirconium oxide (ZrO), aluminum oxide (AlO), or lanthanum oxide (LaO).

[0047] Next, a groove is formed in the insulating layer 40 by a photolithography process, and a conductive structure 50 is filled in the groove. Specifically, the conductive structure 50 fills the groove and covers the surface of the stacked wafer 10; a chemical mechanical polishing process is performed to remove the conductive structure located on the surface of the stacked wafer 10. The material of the conductive structure 50 is, for example, at least one of aluminum, copper and tungsten. The conductive structure 50 extends from the topmost wafer in the stacked wafer 10 to the bottommost wafer along the thickness direction of the stacked wafer 10.

[0048] like Figure 3As shown, the scribe lanes include a plurality of first scribe lanes S1 extending along a first direction X and a plurality of second scribe lanes S2 extending along a second direction Y, wherein the first direction X is perpendicular to the second direction Y. The conductive structure 50 includes a first conductive strip 51 distributed along the first direction X in the first scribe lane S1 and a plurality of first extensions 52 distributed at intervals extending from the first conductive strip 51, wherein the first extensions 52 are distributed, for example, along the second direction Y; the first conductive strip 51 and the plurality of first extensions 52 extend from the topmost wafer in the stacked wafer 10 to the bottommost wafer in the stacked wafer 10 along the thickness direction of the stacked wafer 10.

[0049] The conductive structure 50 further includes a second conductive strip 53 distributed along the second direction Y in the second dicing street S2 and a plurality of second extensions 54 extending from the second conductive strip 53 and distributed at intervals. The second extensions 54 are distributed, for example, along the first direction X. The second conductive strip 53 and the plurality of second extensions 54 extend from the topmost wafer in the stacked wafer 10 to the bottommost wafer in the stacked wafer 10 along the thickness direction of the stacked wafer 10. Figure 4 As shown, when the stacked wafers 10 are cut in the second dicing street S2, the second actual cutting area 30 covers the plurality of second extensions 54, and the static electricity generated by cutting each layer of wafers is transferred from the plurality of second extensions 54 to the second conductive strips 53. The second actual cutting area 30 is located in the second dicing street S2, and the width of the second actual cutting area 30 is less than or equal to the width of the second dicing street S2.

[0050] Similarly, when the stacked wafers 10 are cut in the first dicing lane S1, the first actual cutting area (not shown) covers the first extensions 52, and the static electricity generated by cutting each layer of wafers is transferred from the first extensions 52 to the first conductive strips 51. The first actual cutting area is located in the first dicing lane S1, and the width of the first actual cutting area is less than or equal to the width of the first dicing lane S1.

[0051] During the wafer cutting process, the stacked wafer 10 is fixed on the chuck C. The static electricity generated by cutting the stacked wafer 10 is finally conducted to the chuck C through the conductive structure 50. The chuck C is, for example, grounded to conduct the static electricity away.

[0052] In this embodiment, a conductive structure 50 is added inside the dicing lane to realize metal connection between the upper and lower layers of the stacked wafers 10 to increase the conductive channel and conduct away the static charge generated by each layer of the wafer during the cutting process.

[0053] The present invention also provides a method for manufacturing a semiconductor device according to another embodiment. Figure 5 As shown, including:

[0054] Providing a stacked wafer 10, wherein each layer of wafers in the stacked wafer 10 includes a stacked semiconductor substrate and an isolation layer;

[0055] A conductive tape 20 is attached to the edge of the stacked wafer 10, and the conductive tape 20 extends from the topmost wafer in the stacked wafer 10 to the bottommost wafer along the thickness direction of the stacked wafer 10;

[0056] The stacked wafers 10 are cut, and static electricity generated by cutting each layer of the wafers is conducted away through the conductive tape 20 .

[0057] Exemplarily, the conductive tape 20 includes a conductive metal and an adhesive layer (not shown) located on the surface of the conductive metal. The conductive metal includes a substrate, the material of the substrate is, for example, aluminum foil, the material of the adhesive layer is, for example, conductive acrylic glue, a conductive cloth is provided at the bottom of the substrate, the substrate is bonded to the conductive cloth, and the flexibility of the conductive tape 20 is improved by providing the conductive cloth. The conductive metal and the adhesive layer constitute a conductor, and the conductive tape 20 can be electrically overlapped with the stacked wafer 10 in an adhesive manner to establish a conductive channel to conduct static electricity. The conductive tape 20 combines the conductive shielding performance of the conductive cloth and the soft and compliant characteristics of the tape, and is also thin and durable.

[0058] During the wafer cutting process, the stacked wafer 10 is fixed on the chuck C, and the static electricity generated by cutting each layer of wafer is transferred to the conductive tape 20 through the semiconductor substrate of each layer. The static electricity on the conductive tape 20 and the static electricity generated by cutting the bottom wafer are finally conducted to the chuck C, and the chuck C is grounded to conduct away the static electricity. In another example, the conductive tape 20 is grounded, and the static electricity generated by cutting each layer of wafer is transferred to the conductive tape 20 through the semiconductor substrate of each layer. Since the conductive tape 20 is grounded, the static electricity is conducted away. In this embodiment, after the wafer process is completed, the conductive tape 20 is pasted on the edge of the stacked wafer 10 to conduct away the static electricity generated by each layer of wafer during the cutting process; a conductive channel is added to conduct away the static electricity of the top wafer and the middle wafer, thereby reducing white noise.

[0059] In summary, the present invention provides a semiconductor device and a method for manufacturing the same, including: providing a stacked wafer, wherein each layer of wafers in the stacked wafers includes a stacked semiconductor substrate and an isolation layer; forming a groove in a dicing path of the stacked wafer, forming an insulating layer and a conductive structure embedded in the insulating layer in the groove, wherein the conductive structure extends from the topmost wafer in the stacked wafers to the bottommost wafer along the thickness direction of the stacked wafers; cutting the stacked wafers, and conducting away the static electricity generated by cutting each layer of wafers through the conductive structure. The present invention increases a conductive channel through a conductive structure, conducts away the static charge of the top wafer and the middle wafer, reduces white noise, and avoids breakdown of the static electricity ring on the wafer.

[0060] The present invention provides another method for manufacturing a semiconductor device, comprising: providing a stacked wafer, wherein each layer of wafers in the stacked wafers comprises a stacked semiconductor substrate and an isolation layer; pasting a conductive tape on the edge of the stacked wafer, wherein the conductive tape extends from the topmost wafer in the stacked wafers to the bottommost wafer along the thickness direction of the stacked wafers; and cutting the stacked wafers, wherein the static electricity generated by cutting each layer of wafers is conducted away through the conductive tape. The present invention increases a conductive channel through the conductive tape, conducts away the static charge of the top wafer and the middle wafer, reduces white noise, and avoids breakdown of the static electricity ring on the wafer.

[0061] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0062] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a stacked wafer, wherein each layer of wafer in the stacked wafer comprises a stacked semiconductor substrate and an isolation layer; Forming a groove in a scribe line of the stacked wafer, forming an insulating layer and a conductive structure embedded in the insulating layer in the groove, wherein the conductive structure extends from a topmost wafer in the stacked wafer to a bottommost wafer along a thickness direction of the stacked wafer; Cutting the stacked wafers, and conducting static electricity generated by cutting each layer of the wafers through the conductive structure; The scribing lanes include a plurality of first scribing lanes extending along a first direction and a plurality of second scribing lanes extending along a second direction, and the first direction is perpendicular to the second direction; The conductive structure includes a first conductive strip distributed along the first direction within the first dicing lane and a plurality of first extension portions extending from the first conductive strip at intervals, wherein the first extension portions are distributed along the second direction; the first conductive strip and the plurality of first extension portions extend from the topmost wafer in the stacked wafer to the bottommost wafer along the thickness direction of the stacked wafer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The conductive structure also includes a second conductive strip distributed along the second direction within the second dicing lane and a plurality of second extension portions extending from the second conductive strip at intervals, wherein the second extension portions are distributed along the first direction; the second conductive strip and the plurality of second extension portions extend from the topmost wafer in the stacked wafer to the bottommost wafer along the thickness direction of the stacked wafer.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: When the stacked wafers are cut in the first dicing lane, the first actual cutting area covers a plurality of the first extensions, and static electricity generated by cutting each layer of the wafers is transferred from the plurality of the first extensions to the first conductive strips and conducted away.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the conductive structure includes at least one of aluminum, copper and tungsten.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: Forming a conductive structure embedded in the insulating layer in the trench includes: forming a groove, wherein the groove is formed in the insulating layer by a photolithography process; forming a conductive structure, the conductive structure filling the groove and covering the surface of the stacked wafer; A chemical mechanical polishing process is performed to remove the conductive structure located on the surface of the stacked wafer.

6. A semiconductor device, formed by the manufacturing method according to any one of claims 1 to 5, characterized in that: include: A stacked wafer, wherein each layer of the stacked wafer comprises a stacked semiconductor substrate and an isolation layer; A groove is formed in the dicing lane of the stacked wafer, an insulating layer and a conductive structure embedded in the insulating layer are formed in the groove, and the conductive structure extends from the topmost wafer in the stacked wafer to the bottommost wafer along the thickness direction of the stacked wafer; The scribing lanes include a plurality of first scribing lanes extending along a first direction and a plurality of second scribing lanes extending along a second direction, and the first direction is perpendicular to the second direction; The conductive structure includes a first conductive strip distributed along the first direction in the first scribe line and a plurality of first extension portions extending from the first conductive strip and distributed at intervals.

7. The semiconductor device according to claim 6, wherein: The conductive structure further includes a second conductive strip distributed along the second direction in the second scribe line and a plurality of second extension portions extending from the second conductive strip and distributed at intervals.

Images