Semiconductor element with copper-manganese liner and method of making same

Abstract

The present disclosure provides a semiconductor device having a copper-manganese liner and a method of fabricating the semiconductor device. The semiconductor device has a first well region and a second well region disposed in a semiconductor substrate. The semiconductor device also has a first dielectric layer disposed on the semiconductor substrate and covering the first well region and the second well region, and a gate structure disposed on the first dielectric layer and between the first well region and the second well region. The semiconductor device further has a conductive structure disposed on the first well region and separated from the first well region by a portion of the first dielectric layer. The conductive structure has a barrier layer and a conductive plug disposed on the barrier layer, and the barrier layer includes copper-manganese. The first well region, the conductive structure, and the portion of the first dielectric layer form a reverse fuse structure.

Description

[0001] Cross-references

[0002] This application claims priority and benefits to U.S. formal application No. 17 / 232,992, filed April 16, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor device and a method for fabricating the same. In particular, it relates to a semiconductor device having a copper-manganese substrate and a method for fabricating the same. Background Technology

[0004] Semiconductor components are indispensable for many modern applications. With advancements in electronic technology, semiconductor components have become increasingly smaller, while simultaneously offering superior functionality and incorporating a greater number of integrated circuits. Due to the miniaturization of semiconductor components, different forms and sizes of semiconductor components realizing different functions are integrated and packaged into a single module. Furthermore, numerous manufacturing steps are performed on the integration of various types of semiconductor devices.

[0005] However, the fabrication and integration of these semiconductor devices involve many complex steps and operations. Integration within these semiconductor devices becomes increasingly complex. This increased complexity in the fabrication and integration of these semiconductor devices can lead to several defects, such as voids formed in the conductive structure, which are difficult to fill due to high aspect ratio openings. Therefore, there is a need for continuous improvement of the fabrication processes for these semiconductor devices to address these defects.

[0006] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0007] One embodiment of this disclosure provides a semiconductor device. The semiconductor device has a first well region and a second well region disposed in a semiconductor substrate. The semiconductor device also has a first dielectric layer disposed on the semiconductor substrate and covering the first well region and the second well region; and a gate structure disposed on the first dielectric layer and between the first well region and the second well region. The semiconductor device further has a conductive structure disposed on the first well region and separated from the first well region by a portion of the first dielectric layer. The conductive structure includes a barrier layer and a conductive plug disposed on the barrier layer, and the barrier layer comprises copper-manganese. The first well region, the conductive structure, and the portion of the first dielectric layer form an antifuse structure.

[0008] In one embodiment, the conductive plug of the conductive structure comprises copper. In one embodiment, the barrier layer covers a lower surface of the conductive plug and each sidewall. In one embodiment, the semiconductor device further includes a gate conductive plug disposed on the gate structure, wherein the conductive plug of the conductive structure and the gate conductive plug comprise different materials.

[0009] In one embodiment, the semiconductor device further includes a second dielectric layer disposed on the first dielectric layer, wherein the gate structure, the conductive structure, and the gate conductive plug are disposed in the second dielectric layer, and wherein the first dielectric layer and the second dielectric layer comprise different materials. In one embodiment, the semiconductor device further includes a deep well region disposed in the semiconductor substrate, wherein the first well region and the second well region are disposed in the deep well region. In one embodiment, the first well region and the second well region have a first conductivity type, and the deep well region has a second conductivity type, the second conductivity type being the opposite of the first conductivity type.

[0010] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a first well region and a second well region in a semiconductor substrate; forming a first dielectric layer on the semiconductor substrate and covering the first well region and the second well region; forming a gate structure on the first dielectric layer and between the first well region and the second well region; and forming a conductive structure on the first well region and separated from the first well region by a portion of the first dielectric layer, wherein the conductive structure has a barrier layer and a conductive plug, the conductive plug being disposed on the barrier layer, and the barrier layer comprising copper and manganese, wherein the first well region, the conductive structure, and the portion of the first dielectric layer form an antifuse structure.

[0011] In one embodiment, the conductive structure comprises copper, and the barrier layer covers the lower surface of the conductive plug and each sidewall.

[0012] In one embodiment, the method for fabricating the semiconductor element further includes forming a gate conductive plug on the gate structure, wherein the conductive plug of the conductive structure and the gate conductive plug contain different materials.

[0013] In one embodiment, the method for fabricating the semiconductor element further includes forming a second dielectric layer on the first dielectric layer, wherein the gate structure, the conductive structure, and the gate conductive plug are disposed in the second dielectric layer, and wherein the first dielectric layer and the second dielectric layer comprise different materials.

[0014] In one embodiment, the method for fabricating the semiconductor element further includes forming a deep well region in the semiconductor substrate, wherein the first well region and the second well region are disposed in the deep well region.

[0015] In one embodiment, the first well region and the second well region have a first conductivity type, and the deep well region has a second conductivity type, which is the opposite of the first conductivity type.

[0016] In one embodiment, the method for fabricating the semiconductor element further includes forming a third dielectric layer on the second dielectric layer and forming a plurality of conductive layers in the third dielectric layer.

[0017] This disclosure provides some embodiments of a semiconductor device and its fabrication method. In some embodiments, the semiconductor device has a conductive structure (e.g., an electrode or a conductive plug) and a copper-manganese substrate or barrier layer. The conductive structure is disposed in a dielectric layer, and the copper-manganese substrate or barrier layer separates the conductive structure from the dielectric layer. In some embodiments, the conductive structure comprises copper, and the copper-manganese substrate or barrier layer is configured to reduce or avoid the formation of multiple voids in the conductive structure, thereby reducing contact resistance and improving the electromigration reliability of the conductive structure. Therefore, device performance can be improved.

[0018] One embodiment of this disclosure provides a semiconductor device. The semiconductor device has a first electrode and a second electrode disposed in a first dielectric layer. The semiconductor device also has a first pad separating the first electrode from the first dielectric layer. The semiconductor device further has a fuse chain disposed in the first dielectric layer. The fuse chain is disposed between the first electrode and the second electrode and is electrically connected to the first electrode and the second electrode, and wherein the fuse chain and the first pad comprise copper-manganese.

[0019] In one embodiment, the first electrode and the second electrode comprise copper. In another embodiment, the semiconductor device further includes a second pad separating the second electrode from the first dielectric layer, wherein the second pad comprises copper-manganese. In one embodiment, the first pad, the second pad, and the fuse chain are connected to form a continuous structure. In one embodiment, an upper surface of the first pad and an upper surface of the first electrode are coplanar.

[0020] In one embodiment, the semiconductor device further includes a second dielectric layer disposed on the first dielectric layer; and a plurality of conductive contacts disposed in the second dielectric layer, wherein a first group of the plurality of conductive contacts is electrically connected to the first electrode, and a second group of the plurality of conductive contacts is electrically connected to the second electrode. In one embodiment, the semiconductor device further includes a patterned mask disposed between the first dielectric layer and the second dielectric layer, wherein an upper surface of the fused chain and an upper surface of the patterned mask are coplanar.

[0021] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming an open-hole structure in a first dielectric layer. The open-hole structure has a first portion, a second portion, and a third portion, the third portion being disposed between the first portion and the second portion and physically connecting the first portion and the second portion. The method also includes forming a pad material to line the first portion and the second portion of the open-hole structure and completely fill the third portion of the open-hole structure. The pad material comprises copper-manganese. The method further includes, after the pad material is formed, filling the first portion and the second portion of the open-hole structure with a conductive material; and performing a planarization process on the pad material and the conductive material.

[0022] In one embodiment, the first portion of the aperture structure has a first width, the second portion of the aperture structure has a second width, and the third portion of the aperture structure has a third width, the second width and the third width being parallel to each other, and wherein both the first width and the second width are greater than the third width. In one embodiment, forming the aperture structure in the first dielectric layer includes using a patterned mask as an etching mask, and wherein the planarization process is performed until the patterned mask is exposed. In one embodiment, the conductive material comprises copper.

[0023] In one embodiment, after the planarization process is performed, a remaining portion of the padding material in the third part of the opening structure is configured as a fusible link, a remaining portion of the conductive material in the first part of the opening structure is configured as a first electrode, and a remaining portion of the conductive material in the second part of the opening structure is configured as a second electrode, wherein the first electrode, the second electrode, and the fusible link form a fusible structure. In one embodiment, the fabrication method further includes forming a second dielectric layer on the fusible structure; and forming a plurality of conductive contacts to pass through the second dielectric layer, wherein a first group of the plurality of conductive contacts is electrically connected to the first electrode, and a second group of the plurality of conductive contacts is electrically connected to the second electrode.

[0024] This disclosure provides some embodiments of a semiconductor device and its fabrication method. In some embodiments, the semiconductor device has a conductive structure (e.g., an electrode or a conductive plug) and a copper-manganese substrate or barrier layer. The conductive structure is disposed in a dielectric layer, and the copper-manganese substrate or barrier layer separates the conductive structure from the dielectric layer. In some embodiments, the conductive structure comprises copper, and the copper-manganese substrate or barrier layer is configured to reduce or prevent the formation of multiple voids in the conductive structure, thereby reducing contact resistance and improving the electromigration reliability of the conductive structure. Therefore, device performance can be improved.

[0025] The technical features and advantages of this disclosure have been broadly summarized above, thus enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0026] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0027] Figure 1 This is a top view schematic diagram illustrating semiconductor elements of some embodiments of this disclosure.

[0028] Figure 2 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 1 A semiconductor element with cross-section A-A'.

[0029] Figure 3 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 1 Semiconductor element with cross section B-B'.

[0030] Figure 4 This is a cross-sectional schematic diagram illustrating semiconductor elements according to some embodiments of the present disclosure.

[0031] Figure 5 This is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure.

[0032] Figure 6 This is a flowchart illustrating methods for fabricating semiconductor elements according to some other embodiments of this disclosure.

[0033] Figure 7 This is a top view schematic diagram illustrating an intermediate stage in the formation of an opening structure in a first dielectric layer during the formation of a semiconductor device, according to some embodiments of the present disclosure.

[0034] Figure 8 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure in the formation along... Figure 7 The intermediate stage of a semiconductor device is shown by the cross-section A-A'.

[0035] Figure 9 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure in the formation along... Figure 7 The intermediate stage of a semiconductor device is represented by the cross-section B-B'.

[0036] Figure 10 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 8 During the formation of semiconductor elements with the same cross-section, a pad material is formed in the intermediate stage of the open structure.

[0037] Figure 11 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 9 During the formation of semiconductor elements with the same cross-section, a pad material is formed in the intermediate stage of the open structure.

[0038] Figure 12 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 10 During the formation of semiconductor elements with the same cross-section, an intermediate stage is achieved by filling the open-hole structure with a conductive material.

[0039] Figure 13 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 11 During the formation of semiconductor elements with the same cross-section, an intermediate stage is achieved by filling the open-hole structure with a conductive material.

[0040] Figure 14This is a top view schematic diagram illustrating an intermediate stage of a planarization process performed during the formation of a semiconductor device, according to some embodiments of this disclosure.

[0041] Figure 15 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure in the formation along... Figure 14 The intermediate stage of a semiconductor device is shown by the cross-section A-A'.

[0042] Figure 16 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure in the formation along... Figure 14 The intermediate stage of a semiconductor device is represented by the cross-section B-B'.

[0043] Figure 17 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a first dielectric layer on a semiconductor substrate during the formation of a semiconductor element, according to some other embodiments of this disclosure.

[0044] Figure 18 This is a cross-sectional schematic diagram illustrating some other embodiments of the present disclosure of the intermediate stages of forming a gate structure on a first dielectric layer and forming a plurality of well regions in a semiconductor substrate during the formation of a semiconductor device.

[0045] Figure 19 This is a cross-sectional schematic diagram illustrating an intermediate stage during the formation of a second dielectric layer on a first dielectric layer and the formation of an opening in the second dielectric layer in some other embodiments of this disclosure.

[0046] Figure 20 This is a cross-sectional schematic diagram illustrating an intermediate stage in which a barrier material and a conductive material are sequentially formed during the formation of a semiconductor element in an opening, according to some other embodiments of this disclosure.

[0047] Figure 21 This is a cross-sectional schematic diagram illustrating an intermediate stage in the planarization of barrier and conductive materials during the formation of a semiconductor device, as described in some other embodiments of this disclosure.

[0048] Figure 22 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a gate conductive plug on a gate structure during the formation of a semiconductor device, according to some other embodiments of this disclosure.

[0049] Explanation of reference numerals in the attached figures:

[0050] 10: Preparation method

[0051] 100: Semiconductor components

[0052] 103: First dielectric layer

[0053] 105: Patterned Masking

[0054] 110: Opening structure

[0055] 110a: Part One

[0056] 110b: Part Two

[0057] 110c: Part 3

[0058] 120: Opening structure

[0059] 120a: Part One

[0060] 120b: Part Two

[0061] 120c: Part 3

[0062] 123: Padding material

[0063] 125a: First gasket

[0064] 125b: Second pad

[0065] 125c: Fuse Chain

[0066] 133: Conductive materials

[0067] 135a: First electrode

[0068] 135b: Second electrode

[0069] 141: Second dielectric layer

[0070] 143: Conductive contact point

[0071] 200: Semiconductor components

[0072] 201: Semiconductor substrate

[0073] 203: Insulation Structure

[0074] 205: Deep Well Area

[0075] 207: First dielectric layer

[0076] 207': Part

[0077] 209: Gate dielectric layer

[0078] 211: Gate electrode layer

[0079] 213: Gate Structure

[0080] 215: Gate spacer

[0081] 217: First Well Area

[0082] 219: Second Well Area

[0083] 221: Second dielectric layer

[0084] 223: Patterned Masking

[0085] 230: Opening

[0086] 240: Opening

[0087] 243: Barrier Materials

[0088] 245: Barrier Layer

[0089] 253: Conductive materials

[0090] 255: Conductive embolism

[0091] 257: Conductive Structure

[0092] 263: Patterned Masking

[0093] 270: Opening

[0094] 280: Opening

[0095] 283: Gate Conductive Plug

[0096] 291: Third dielectric layer

[0097] 293: Conductive layer

[0098] 295: Conductive layer

[0099] 30: Preparation method

[0100] 300: Anti-fuse structure

[0101] S11: Steps

[0102] S13: Steps

[0103] S15: Steps

[0104] S17: Steps

[0105] S19: Steps

[0106] S21: Steps

[0107] S23: Steps

[0108] S31: Steps

[0109] S33: Steps

[0110] S35: Steps

[0111] S37: Steps

[0112] S39: Steps

[0113] S41: Steps

[0114] S43: Steps

[0115] T1: Upper surface

[0116] T2: Upper surface

[0117] T3: Upper surface

[0118] T4: Upper surface

[0119] W1: Width

[0120] W2: Width

[0121] W3: Width Detailed Implementation

[0122] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0123] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatial relative terms are intended to encompass different orientations of the element in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0124] Figure 1 This is a top view schematic diagram illustrating a semiconductor element 100 according to some embodiments of the present disclosure. Figure 2 and Figure 3 These are cross-sectional schematic diagrams illustrating some embodiments of this disclosure along... Figure 1 The semiconductor elements are shown along cross-sections A-A' and B-B'. In some embodiments, the semiconductor element 100 is a fuse structure. Figures 1 to 3As shown, the semiconductor device 100 has a first dielectric layer 103; a patterned mask 105 disposed on the first dielectric layer 103; and a second dielectric layer 141 disposed on the patterned mask 105. It should be understood that, for the sake of simplicity, the figures are as follows... Figure 2 and Figure 3 The second dielectric layer 141 shown is not displayed. Figure 1 In the top view.

[0125] Furthermore, the semiconductor element 100 has a first electrode 135a, a second electrode 135b, a first pad 125a, a second pad 125b, and a fuse chain 125c, with the fuse chain 125c disposed in the first dielectric layer 103. In some embodiments, according to certain examples, the lower portions of the first electrode 135a, the second electrode 135b, the first pad 125a, the second pad 125b, and the fuse chain 125c are embedded in the first dielectric layer 103, and the upper portions of the first electrode 135a, the second electrode 135b, the first pad 125a, the second pad 125b, and the fuse chain 125c are embedded in a patterned mask 105.

[0126] In some embodiments, the first electrode 135a and the second electrode 135b are separated, and a fuse chain 125c is disposed between the first electrode 135a and the second electrode 135b and electrically connected to the first electrode 135a and the second electrode 135b. In some embodiments, the first electrode 135a is surrounded by a first pad 125a, and the second electrode 135b is surrounded by a second pad 125b. In some embodiments, the sidewalls and lower surface of the first electrode 135a are covered by the first pad 125a, and the sidewalls and lower surface of the second electrode 135b are covered by the second pad 125b. In other words, the first electrode 135a is separated from the first dielectric layer 103 and the patterned mask 105 by the first pad 125a, and the second electrode 135b is separated from the first dielectric layer 103 and the patterned mask 105 by the second pad 125b.

[0127] It should be understood that the first gasket 125a, the second gasket 125b, and the fused chain 125c are solidly connected to form a continuous structure without interfaces therebetween. (Indications are missing from the original text.) Figure 1The dashed lines representing the boundaries of the first pad 125a, the second pad 125b, and the fuse chain 125c are for clarity in this disclosure. There is no obvious interface between the first pad 125a, the second pad 125b, and the fuse chain 125c. In some embodiments, the first pad 125a, the second pad 125b, and the fuse chain 125c are manufactured using the same process and using the same materials. In some embodiments, for example, the first pad 125a, the second pad 125b, and the fuse chain 125c comprise copper-manganese, and the first electrode and the second electrode comprise copper.

[0128] Please refer to the following: Figures 1 to 3 The semiconductor element 100 also has a plurality of conductive contacts 143 disposed in the second dielectric layer 141. In some embodiments, a first group of the conductive contacts 143 is disposed on and electrically connected to the first electrode 135a, while a second group of the conductive contacts 143 is disposed on and electrically connected to the second electrode 135b. Although in Figure 1 Only three conductive contact points 143 are shown on each of the first electrode 135a and the second electrode 135b, but any number of conductive contact points 143 on the first electrode 135a and the second electrode 135b can be provided.

[0129] Figure 4 This is a cross-sectional schematic diagram illustrating a semiconductor element 200 according to some embodiments of the present disclosure. In some embodiments, the semiconductor element 200 has an antifuse structure 300, which will be described in detail later.

[0130] like Figure 4 As shown, the semiconductor device 200 has a semiconductor substrate 201; a plurality of insulating structures 203 disposed in the semiconductor substrate 201; a deep well region 205 disposed in the semiconductor substrate 201 and between the insulating structures 203; and a first well region 217 and a second well region 219 disposed in the deep well region 205. In some embodiments, the first well region 217 and the second well region 219 have a first conductivity type, and the deep well region 205 has a second conductivity type, which is the opposite of the first conductivity type. For example, the deep well region 205 is lightly doped with a p-type dopant, while the first well region 217 and the second well region 219 are heavily doped with an n-type dopant.

[0131] Furthermore, in some embodiments, the semiconductor element 200 has a first dielectric layer 207 disposed on the semiconductor substrate 201 and covering the first well region 217 and the second well region 219; a gate structure 213 and a conductive structure 257 disposed on the first dielectric layer 207; and a gate conductive plug 283 disposed on the gate structure 213. In some embodiments, the gate structure 213 is disposed between the first well region 217 and the second well region 219, while the conductive structure 257 is disposed on the first well region 217. It should be understood that the conductive structure 257 is separated from the first well region 217 by a portion of the first dielectric layer 207.

[0132] In some embodiments, the gate structure 213 has a gate dielectric layer 209 and a gate electrode layer 211, with the gate electrode layer 211 disposed on the gate dielectric layer 209. In some embodiments, a plurality of gate spacers 215 are disposed on opposite sidewalls of the gate structure 213. Furthermore, the conductive structure 257 has a barrier layer 245 and a conductive plug 255, with the conductive plug 255 disposed on the barrier layer 245. In some embodiments, the barrier layer 245 covers a lower surface of the conductive plug 255 and each sidewall. In some embodiments, for example, the barrier layer 245 comprises copper-manganese, and the conductive plug 255 comprises copper.

[0133] Please refer to the following: Figure 4 The semiconductor device 200 further includes a second dielectric layer 221 disposed on the first dielectric layer 207; a third dielectric layer 291 disposed on the second dielectric layer 221; and conductive layers 293 and 295 disposed in the third dielectric layer 291. In some embodiments, a gate structure 213, a conductive structure 257, and a gate conductive plug 283 are disposed in the second dielectric layer 221. In some embodiments, the conductive layer 293 is disposed on and electrically connected to the conductive structure 257, while the conductive layer 295 is disposed on the gate structure 213 and electrically connected to the gate structure 213 via the gate conductive plug 283.

[0134] In some embodiments, the first dielectric layer 207 has a portion 207' sandwiched between the conductive structure 257 and the first well region 217. It should be understood that the first well region 217, the conductive structure 257, and this portion 207' of the first dielectric layer 207 together form the antifuse structure 300. The conductive structure 257 can be considered as the upper electrode of the antifuse structure 300, while the first well region 217 can be considered as the lower electrode of the antifuse structure 300.

[0135] Figure 5This is a flowchart illustrating a method 10 for fabricating a semiconductor element (e.g., semiconductor element 100) according to some embodiments of the present disclosure. The fabrication method 10 includes steps S11, S13, S15, S17, S19, and S21. Figure 6 This is a flowchart illustrating a method 30 for fabricating a semiconductor element (e.g., semiconductor element 200) according to some other embodiments of this disclosure, wherein the fabrication method 30 includes steps S31, S33, S35, S37, S39, S41, and S43. Figure 5 Steps S11 to S21 and Figure 6 Steps S31 to S43 are described in detail with reference to the following figures.

[0136] Figure 7 This is a top view schematic diagram illustrating an intermediate stage in the formation of an opening structure 120 in a first dielectric layer 103 during the formation of a semiconductor element 100, according to some embodiments of the present disclosure. Figure 8 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure in the formation along... Figure 7 The intermediate stage of a semiconductor device is shown in the cross-section A-A'. Figure 9 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure in the formation along... Figure 7 The intermediate stage of a semiconductor device, as shown in the cross-section B-B'. For example... Figures 7 to 9 As shown, a first dielectric layer 103 is provided, and a patterned mask 105 having an opening structure 110 is formed on the first dielectric layer 103.

[0137] In some embodiments, the first dielectric layer 103 comprises silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or other dielectric materials. The first dielectric layer 103 may be formed on a semiconductor substrate (not shown), such as an interlayer dielectric (ILD) layer or an interlayer metal dielectric (IMD) layer in a portion of a semiconductor chip. Furthermore, the aperture structure 110 in the patterned mask 105 has a first portion 110a, a second portion 110b, and a third portion 110c, with the third portion 110c disposed between and connected to the first portion 110a and the second portion 110b.

[0138] like Figures 7 to 9 As shown, according to some embodiments, an etching process is performed on the first dielectric layer 103 using a patterned mask as an etching mask to form an opening structure 120 in the first dielectric layer 120. The corresponding steps are shown in... Figure 5 Step S11 in method 10 shown. In some embodiments, the etching process includes a wet etching process, a dry etching process, or a combination thereof, and the aperture structure 110 is transformed from the patterned mask 105 to the first dielectric layer 103 in order to form the aperture structure 120.

[0139] In some embodiments, the aperture structure 120 does not penetrate the first dielectric layer 103. Similar to the pattern of the aperture structure 110 in the patterned mask 105, the aperture structure 120 has a first portion 120a, a second portion 120b, and a third portion 120c, wherein the third portion 120c is disposed between and connected to the first portion 120a and the second portion 120b. In some embodiments, the first portion 110a of the aperture structure 110 and the first portion 120a of the aperture structure 120 have a width W1 (see reference). Figure 8 The third part 110c of the opening structure 110 and the third part 120c of the opening structure 120 have a width W2 (see reference). Figure 9 ), and the width W1 is greater than the width W2.

[0140] Since the contours of the second portion 110b of the opening structure 110 and the second portion 120b of the opening structure 120 are similar to those of the first portion 110a of the opening structure 110 and the first portion 120a of the opening structure 120, cross-sectional views along the second portions 110b and 120b are not shown. In some embodiments, the second portion 110b of the opening structure 110 and the second portion 120b of the opening structure 120 have a width (not shown), which is approximately the same as... Figure 8 The width W1 in the middle. Therefore, the width of the second part 110b and 120b is also greater than the width W2 of the third part 110c and 120c. It should be understood that widths W1, W2 and W3 are parallel to each other.

[0141] Figure 10 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 8 During the formation of a semiconductor element 100 with the same cross section (i.e., cross section A-A'), a pad material 123 is formed in the intermediate stage of the aperture structure 110. Figure 11 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 9 During the formation of a semiconductor element 100 with the same cross-section (i.e., cross-section B-B'), a pad material 123 is formed in the intermediate stage of the aperture structure 120. For example... Figure 10 and Figure 11 As shown, the padding material 123 is conformally deposited in the opening structures 110 and 120, and on the upper surface of the patterned mask 105. The corresponding steps are shown in... Figure 5 Step S13 in method 10 shown.

[0142] The first portions 110a and 120a and the second portions 110b and 120b of the opening structures 110 and 120 have a width greater than the width of the third portions 110c and 120c of the opening structures 110 and 120. Therefore, the third portions 110c and 120c are completely filled with the padding material 123, while the first portions 110a and 120a and the second portions 110b and 120b are partially filled with the padding material 123. In some embodiments, the sidewalls of the first portions 110a and 110b, and the lower surfaces and sidewalls of the first portions 120a and 120b are lined with the padding material 123. In some embodiments, the padding material 123 comprises copper manganese, and its fabrication technique includes a deposition process, such as a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, or a combination thereof.

[0143] Figure 12 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 10 During the formation of a semiconductor element 100 with the same cross-section (i.e., cross-section A-A'), a conductive material 133 is used to fill the intermediate stage of the opening structure 110. Figure 13 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 11 During the formation of a semiconductor element 100 with the same cross-section (i.e., cross-section A-A'), a conductive material 133 is used to fill the intermediate stage of the open structure.

[0144] like Figure 12 and Figure 13 As shown, conductive material 133 is formed in the aperture structures 110 and 120 and on the upper surface of the patterned mask 105. The corresponding steps are shown in... Figure 5 Step S15 of method 10 shown. In some embodiments, the conductive material 133 comprises copper, and its fabrication technique includes a deposition process, such as a CVD process, an ALD process, a PVD process, a sputtering process, a plating process, or a combination thereof. It should be understood that, according to some embodiments, the remaining first portions 110a, 120a and the remaining second portions 110b, 120b of the opening structures 110, 120 are completely filled with the conductive material 133.

[0145] Figure 14 This is a top view schematic diagram illustrating an intermediate stage of a planarization process performed during the formation of a semiconductor element 100, according to some embodiments of this disclosure. Figure 15 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure in the formation along... Figure 14 The intermediate stage of a semiconductor device is shown in the cross-section A-A'. Figure 16 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure in the formation along... Figure 14The intermediate stage of a semiconductor device, as shown in the cross-section B-B'. For example... Figures 14 to 16 As shown, a planarization process is performed on the pad material 123 and the conductive material 133 until the patterned mask 105 is exposed. The corresponding steps are shown in... Figure 5 Step S17 in method 10 shown.

[0146] The planarization process may include a chemical mechanical polishing (CMP) process. In some embodiments, the planarization process removes excess portions of pad material 123 and conductive material 133 outside the opening structure 110 in the patterned mask 105 and outside the opening structure 120 in the first dielectric layer 103. As a result, a remaining portion of pad material 123 in the first portions 110a and 120a of the opening structures 110 and 120 is configured as a first pad 125a, a remaining portion of pad material 123 in the second portions 110b and 120b of the opening structures 110 and 120 is configured as a second pad 125b, and a remaining portion of pad material 123 in the third portions 110c and 120c of the opening structures 110 and 120 is configured as a fused chain 125c.

[0147] Furthermore, after the planarization process is performed, a remaining portion of the conductive material 133 in the first portions 110a and 120a of the opening structures 110 and 120 is configured as a first electrode 135a, and a remaining portion of the conductive material 133 in the second portions 110b and 120b of the opening structures 110 and 120 is configured as a second electrode 135b. For example... Figure 15 and Figure 16 As shown, the patterned mask 105 has an upper surface T1, the first electrode 135a has an upper surface T2, the first pad 125a has an upper surface T3, and the fused chain 125c has an upper surface T4. In some embodiments, the upper surfaces T1, T2, T3, and T4 are substantially coplanar. In this disclosure, the term "substantially" means preferably at least 90%, more preferably 95%, even more preferably 98%, and most preferably 99%.

[0148] Please refer to Figures 1 to 3 According to some embodiments, after the planarization process, a second dielectric layer 141 is formed on the patterned mask 105. The corresponding steps are shown in... Figure 5 Step S19 in method 10 shown. The second dielectric layer 141 may comprise silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or other dielectric materials, and its fabrication technique may include a deposition process, such as a CVD process, an ALD process, a PVD process, a spin coating process, or a combination thereof.

[0149] like Figures 1 to 3As shown, according to some embodiments, after the second dielectric layer 141 is formed, a plurality of conductive contact points 143 are formed to pass through the second dielectric layer 141 and thereby contact the first electrode 135a and the second electrode 135b. The corresponding steps are shown in... Figure 5 Step S21 in method 10 shown. In some embodiments, the conductive contact points 143 comprise a conductive material, such as tungsten, aluminum, titanium, tantalum, gold, silver, copper, or a combination thereof.

[0150] In some embodiments, the fabrication technique for the conductive contacts 143 includes forming a plurality of openings (not shown) in the second dielectric layer 141 to expose the upper surfaces of the first dielectric electrode 135a and the second electrode 135b; and filling the openings with a conductive material. The fabrication technique for the openings may include an etching process using a patterned mask as an etching mask, and the fabrication technique for the conductive material may include a deposition process, such as a CVD process or an ALD process. A planarization process, such as chemical mechanical polishing, may then be performed to remove any excess material from the upper surfaces of the second dielectric layer 141.

[0151] After the conductive contact points 143 are formed, a semiconductor device 100 is obtained. In this embodiment, the first pad 125a and the second pad 125b comprise copper-manganese, and the first electrode 135a and the second electrode 135b comprise copper. These copper-manganese layers (i.e., the first pad 125a and the second pad 125b) can reduce or prevent the formation of multiple voids in the first electrode 135a and the second electrode 135b, thereby reducing contact resistance and improving the electromigration reliability of the first electrode 135a and the second electrode 135b. Therefore, device performance can be improved. Furthermore, since the fabrication techniques for the fuse chain 125c, the first pad 125a, and the second pad 125b can include the use of the same processes and the same materials, process costs can be reduced.

[0152] Figures 17 to 22 This is a cross-sectional schematic diagram illustrating various intermediate stages during the formation of the semiconductor element 200 in some other embodiments of this disclosure. For example... Figure 17 As shown, a semiconductor substrate 201 is provided. The semiconductor substrate 201 may be a semiconductor wafer, such as a silicon wafer.

[0153] Additionally, the semiconductor substrate 201 may comprise elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and gallium arsenide phosphide (GaInAsP).

[0154] In some embodiments, the semiconductor substrate 201 includes an epitaxial layer. For example, the semiconductor substrate 201 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 201 is a semiconductor-on-insulator (SOI) substrate, which may include a substrate, a buried oxide layer, and a semiconductor layer, wherein the buried oxide layer is located on the substrate, the semiconductor layer is located on the buried oxide layer, and the SOI substrate is, for example, a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The SOI substrate can be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0155] Please refer to the following: Figure 17According to some embodiments, the insulating structures 203 are formed in the semiconductor substrate 201 to define a plurality of active regions, and the insulating structures 203 are shallow trench isolation (STI) structures. Furthermore, the insulating structures 203 may comprise silicon oxide, silicon nitride, silicon oxynitride, or other applicable dielectric materials, and the fabrication techniques for the insulating structures 203 may include forming a patterned mask (not shown) on the semiconductor substrate 201; etching the semiconductor substrate 201 using the patterned mask as an etch mask to form a plurality of openings (not shown); depositing a dielectric material in the openings and on the semiconductor substrate 201; and planarizing the dielectric material until the semiconductor substrate 201 is exposed.

[0156] Furthermore, in some embodiments, the deep well region 205 is formed within the active regions defined by the insulating structures 203. In some embodiments, the fabrication technique of the deep well region 205 includes one or more ion implantation processes, and multiple P-type dopants or multiple N-type dopants may be implanted in the semiconductor substrate 201 to form the deep well region 205. The implantation of P-type or N-type dopants depends on the conductivity type of the semiconductor element 200; P-type dopants include, for example, boron, gallium, or indium, while N-type dopants include, for example, phosphorus or arsenic.

[0157] Please refer to the following: Figure 17 According to some embodiments, a first dielectric layer 207 is formed on a semiconductor substrate 201 and covers the insulating structures 203 and the deep well region 205. In some embodiments, the first dielectric layer 207 may comprise silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or other dielectric materials, and its fabrication technique includes a deposition process, such as a CVD process, an ALD process, a PVD process, a spin coating process, or a combination thereof.

[0158] Next, as Figure 18 As shown, according to some embodiments, a gate structure 213 having a gate dielectric layer 209 and a gate electrode layer 211 is formed on a first dielectric layer 207, and a plurality of gate spacers are formed on opposite sidewalls of the gate structure 213. The corresponding steps are shown in... Figure 6 Step S33 in method 30 shown. In some embodiments, the gate dielectric layer 209 comprises silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, a dielectric material having a high dielectric constant (high-k), or a combination thereof, and the gate electrode layer 211 comprises polysilicon, a metal material (e.g., aluminum, copper, tungsten, titanium, tantalum), a metal silicide material, or a combination thereof.

[0159] In some embodiments, the fabrication technique for the gate structure 213 includes sequentially forming a gate dielectric material (not shown) and a gate electrode material (not shown) on a first dielectric layer 207 through multiple deposition processes. The deposition processes may include CVD, ALD, PVD, sputtering, electroplating, or combinations thereof. Then, an etching process is performed on the gate dielectric material and the gate electrode material using a patterned mask (not shown) as an etching mask. The etching process may include a wet etching process, a dry etching process, or a combination thereof. The patterned mask may be removed after the gate structure 213 has been formed.

[0160] In some embodiments, the gate spacers 215 comprise silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, other applicable dielectric materials, or combinations thereof. In some embodiments, the fabrication technique for the gate spacers 215 includes conformally depositing a spacer material (not shown) on the upper surface and sidewalls of the gate structure 213 and on the upper surface of the first dielectric layer 207. The deposition process may include a CVD process, a PVD process, an ALD process, a spin coating process, or other applicable processes. The spacer material is then etched using an anisotropic etching process, which vertically removes the same amount of spacer material at all locations, leaving the gate spacers 215 on the sidewalls of the gate structure 213. In some embodiments, the etching process is a dry etching process.

[0161] Furthermore, after the gate spacers 215 are formed, a first well region 217 and a second well region 219 are formed in the semiconductor substrate 201. In some embodiments, the first well region 217 and the second well region 219 are formed in the deep well region 205 and on opposite sides of the gate structure 213. The corresponding steps are shown in... Figure 6 Step S35 in method 30 shown. In some embodiments, the fabrication techniques for the first well region 217 and the second well region 219 include an ion implantation process using the gate structure 213 and the gate spacers 215 as an implantation mask.

[0162] Some dopants used to form the first well region 217 and the second well region 219 are similar to or the same as the dopants used to form the deep well region 205, and their detailed description will not be repeated herein. In some embodiments, the conductivity type of the dopants in the first well region 217 is the same as that of the dopants in the second well region 219, while the conductivity type of the dopants in the first well region 217 is opposite to that of the dopants in the deep well region 205. Furthermore, the implantation dose in the first well region 217 and the second well region 219 may be greater than the implantation dose in the deep well region 205.

[0163] Next, as Figure 19As shown, according to some embodiments, a second dielectric layer 221 is formed on the first dielectric layer 207 and covers the gate structure 213 and the gate spacers 215. The corresponding steps are shown in... Figure 6 Step S37 of method 30 is shown. The second dielectric layer 221 may comprise silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or other dielectric materials, and its fabrication technique includes a deposition process, such as a CVD process, an ALD process, a PVD process, a spin coating process, or a combination thereof. In some embodiments, the second dielectric layer 221 and the first dielectric layer 207 comprise different materials.

[0164] Please refer to the following: Figure 19 According to some embodiments, a patterned mask 223 having an opening 230 is formed on a second dielectric layer 221, and an etching process is performed on the second dielectric layer 221 using the patterned mask 223 as an etching mask to transfer the opening 230 from the patterned mask 223 to the second dielectric layer 221, thereby obtaining an opening 240 exposing the first dielectric layer 207. In some embodiments, the openings 230 and 240 are formed on a first well region 217. In some embodiments, the etching process includes a wet etching process, a dry etching process, or a combination thereof.

[0165] like Figure 20 As shown, according to some embodiments, after the opening 240 is formed in the second dielectric layer 221, a barrier material 243 and a conductive material 253 are sequentially formed in the openings 230 and 240 and on the upper surface of the patterned mask 223. In some embodiments, the conductive material 253 is separated from the first dielectric layer 207, the second dielectric layer 221, and the patterned mask 223 by the barrier material 243.

[0166] In some embodiments, the barrier material 243 comprises copper and manganese, and its fabrication technique includes a deposition process, such as a CVD process, an ALD process, a PVD process, or a combination thereof. In some embodiments, the conductive material 253 comprises copper, and its fabrication technique includes a deposition process, such as a CVD process, an ALD process, a PVD process, a sputtering process, a plating process, or a combination thereof.

[0167] Next, as Figure 21 As shown, according to some embodiments, a planarization process, such as a CMP process, is performed on the patterned mask 223, the barrier material 243, and the conductive material 253 to remove any excess material on the upper surface of the second dielectric layer 221 in order to obtain a conductive structure 257 having conductive plugs 255 and a barrier layer 245. The corresponding steps are shown in... Figure 6 Step S39 in method 30 shown.

[0168] Please refer to the following: Figure 21 According to some embodiments, a patterned mask 263 having an opening 270 is formed on a second dielectric layer 221, and an etching process is performed on the second dielectric layer 221 by using the patterned mask 263 as an etching mask to transition the opening 270 from the patterned mask 263 to the second dielectric layer 221, thereby obtaining an opening 280 exposing the gate structure 213. In some embodiments, a portion of the gate electrode layer 211 is exposed through the opening 280. In some embodiments, the etching process includes a wet etching process, a dry etching process, or a combination thereof.

[0169] like Figure 22 As shown, according to some embodiments, after the opening 280 on the gate structure 213 is formed, a gate conductive plug 283 is formed to fill the opening 280. The corresponding steps are shown in... Figure 6 Step S41 of method 30 is shown. In some embodiments, the gate conductive plug 283 comprises a conductive material, such as tungsten, aluminum, titanium, tantalum, gold, silver, copper, or a combination thereof. The fabrication technique of the gate conductive plug 283 may include a deposition process (e.g., CVD, ALD, or PVD) and a subsequent planarization process (e.g., CMP).

[0170] Please refer back to this page. Figure 4 According to some embodiments, a third dielectric layer 291 is formed on the second dielectric layer 221, and conductive layers 293 and 295 are formed in the third dielectric layer 291. The corresponding steps are shown in... Figure 6 Step S43 in method 30 shown. Some materials and processes used to form the third dielectric layer 291 are similar to or the same as those used to form the second dielectric layer 221, and their detailed description will not be repeated herein.

[0171] In some embodiments, conductive layer 293 is formed on and electrically connected to conductive structure 257, and conductive layer 295 is formed on and electrically connected to gate conductive plug 283. In some embodiments, conductive layers 293 and 295 comprise a conductive material, such as tungsten, aluminum, titanium, tantalum, gold, silver, copper, or a combination thereof. The fabrication technique of conductive layers 293 and 295 may include forming a plurality of openings (not shown) in the third dielectric layer 291 using a patterned mask as an etching mask; forming a conductive material in the openings and on the third dielectric layer 291; and performing a planarization process (e.g., CMP) to remove any excess material on the upper surface of the third dielectric layer 291.

[0172] After the conductive layers 293 and 295 are formed, a semiconductor device 200 with an antifuse structure 300 is obtained. In this embodiment, the barrier layer 245 comprises copper-manganese, and the conductive plug 255 comprises copper. These copper-manganese substrates (i.e., barrier layer 245) can reduce or prevent the formation of multiple voids in the conductive plug 255, thereby reducing contact resistance and improving the electromigration reliability of the conductive plug 255. Therefore, device performance can be improved.

[0173] This disclosure provides some embodiments of semiconductor devices 100, 200, and methods for fabricating the same. In some embodiments, copper-manganese substrates (e.g., first pads 125a and second pads 125b in semiconductor device 100, and conductive plugs 255 in semiconductor device 200) surrounding copper conductive structures (e.g., first electrodes 135a and 135b in semiconductor device 100, and conductive plugs 255 in semiconductor device 200) can reduce or prevent the formation of multiple voids in the conductive structures, thereby reducing contact resistance and improving the electromigration reliability of the conductive structures. Therefore, device performance can be improved.

[0174] One embodiment of this disclosure provides a semiconductor device. The semiconductor device has a first well region and a second well region disposed in a semiconductor substrate. The semiconductor device also has a first dielectric layer disposed on the semiconductor substrate and covering the first well region and the second well region; and a gate structure disposed on the first dielectric layer and between the first well region and the second well region. The semiconductor device further has a conductive structure disposed on the first well region and separated from the first well region by a portion of the first dielectric layer. The conductive structure includes a barrier layer and a conductive plug disposed on the barrier layer, and the barrier layer comprises copper-manganese. The first well region, the conductive structure, and the portion of the first dielectric layer form an antifuse structure.

[0175] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a first well region and a second well region in a semiconductor substrate; forming a first dielectric layer on the semiconductor substrate and covering the first well region and the second well region; forming a gate structure on the first dielectric layer and between the first well region and the second well region; and forming a conductive structure on the first well region and separated from the first well region by a portion of the first dielectric layer, wherein the conductive structure has a barrier layer and a conductive plug, the conductive plug being disposed on the barrier layer, and the barrier layer comprising copper and manganese, wherein the first well region, the conductive structure, and the portion of the first dielectric layer form an antifuse structure.

[0176] Some embodiments provided in this disclosure have advantageous features. By forming a copper-manganese liner around the conductive structure, the formation of multiple voids in the conductive structure can be reduced or avoided, thereby reducing contact resistance and improving the electromigration reliability of the conductive structure. Therefore, device performance can be improved.

[0177] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0178] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: A first well region and a second well region are disposed in a semiconductor substrate; A first dielectric layer is disposed on the semiconductor substrate and covers the first well region and the second well region; A gate structure is disposed on the first dielectric layer and between the first well region and the second well region, wherein the gate structure includes a gate dielectric layer and a gate electrode layer, the gate dielectric layer being disposed on the first dielectric layer and the gate electrode layer being disposed on the gate dielectric layer; and A conductive structure is disposed on the first well region and separated from the first well region by a portion of the first dielectric layer, wherein the conductive structure includes a barrier layer and a conductive plug, the conductive plug is disposed on the barrier layer, and the barrier layer comprises copper manganese. The first well region, the conductive structure, and this portion of the first dielectric layer form an antifuse structure.

2. The semiconductor device of claim 1, wherein the conductive plug of the conductive structure comprises copper.

3. The semiconductor device of claim 1, wherein the barrier layer covers a lower surface of the conductive plug and each sidewall.

4. The semiconductor device of claim 1 further includes a gate conductive plug disposed on the gate structure, wherein the conductive plug of the conductive structure and the gate conductive plug comprise different materials.

5. The semiconductor device of claim 4, further comprising a second dielectric layer disposed on the first dielectric layer, wherein the gate structure, the conductive structure, and the gate conductive plug are disposed in the second dielectric layer, and wherein the first dielectric layer and the second dielectric layer comprise different materials.

6. The semiconductor device of claim 1 further includes a deep well region disposed in the semiconductor substrate, wherein the first well region and the second well region are disposed in the deep well region.

7. The semiconductor device of claim 6, wherein the first well region and the second well region have a first conductivity type, and the deep well region has a second conductivity type, the second conductivity type being the opposite of the first conductivity type.

8. A method for fabricating a semiconductor element, comprising: A first well region and a second well region are formed in a semiconductor substrate; A first dielectric layer is formed on the semiconductor substrate and covers the first well region and the second well region; A gate structure is formed on the first dielectric layer and between the first well region and the second well region; and A conductive structure is formed on the first well region and separated from the first well region by a portion of the first dielectric layer, wherein the conductive structure has a barrier layer and a conductive plug, the conductive plug being disposed on the barrier layer, and the barrier layer comprising copper manganese. The first well region, the conductive structure, and this portion of the first dielectric layer form an antifuse structure; as well as The gate structure is formed on the first dielectric layer and between the first well region and the second well region, including: A gate dielectric material and a gate electrode material are sequentially formed on the first dielectric layer; A patterned mask is used as an etching mask to perform an etching process on the gate dielectric material and the gate electrode material to form a gate dielectric layer and a gate electrode layer; and Remove the patterned mask.

9. The method for fabricating a semiconductor element as claimed in claim 8, wherein the conductive plug of the conductive structure comprises copper.

10. The method for fabricating a semiconductor element as claimed in claim 8, wherein the barrier layer covers a lower surface of the conductive plug and each sidewall.

11. The method for fabricating a semiconductor element as claimed in claim 8, further comprising forming a gate conductive plug on the gate structure, wherein the conductive plug of the conductive structure and the gate conductive plug comprise different materials.

12. The method for fabricating a semiconductor device as claimed in claim 11, further comprising forming a second dielectric layer on the first dielectric layer, wherein the gate structure, the conductive structure, and the gate conductive plug are disposed in the second dielectric layer, and wherein the first dielectric layer and the second dielectric layer comprise different materials.

13. The method for fabricating a semiconductor element as claimed in claim 8, further comprising forming a deep well region in the semiconductor substrate, wherein the first well region and the second well region are disposed in the deep well region.

14. The method for fabricating a semiconductor element as claimed in claim 13, wherein the first well region and the second well region have a first conductivity type, and the deep well region has a second conductivity type, the second conductivity type being the opposite of the first conductivity type.

15. The method for fabricating a semiconductor device as described in claim 12, further comprising: A third dielectric layer is formed on the second dielectric layer; as well as Multiple conductive layers are formed in this third dielectric layer.

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