Semiconductor element and method for producing the same

Abstract

The present disclosure provides a semiconductor device having air gaps between wrap-around gate transistors and a method of fabricating the same. The semiconductor device has a first gate stack and a second gate stack disposed on a semiconductor substrate. At least one of the first gate stack and the second gate stack has a plurality of gate layers, and an air gap is between the first gate stack and the second gate stack. The semiconductor device also has a first gate structure and a second gate structure disposed on the first gate stack and the second gate stack, respectively, and a first dielectric layer surrounding lower sidewalls of the first gate structure and lower sidewalls of the second gate structure. A width of the first gate structure is greater than a width of the first plug.

Description

Technical Field

[0001] This application claims priority and benefits from U.S. formal application No. 17 / 234,328, filed April 19, 2021, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for fabricating the same. More particularly, it relates to a semiconductor device having an air gap between gate-all-around transistors and a method for fabricating the same. Background Technology

[0003] Semiconductor components are indispensable for many modern applications. With advancements in electronic technology, semiconductor components have become increasingly smaller, while simultaneously offering superior functionality and incorporating a larger number of integrated circuits. Due to the miniaturization of semiconductor components, different types and sizes of semiconductor components realizing different functions are integrated and packaged into a single module. Furthermore, numerous manufacturing steps are performed on the integration of various types of semiconductor devices.

[0004] However, the fabrication and integration of semiconductor devices involve many complex steps and operations. Integration within these devices becomes increasingly complex. This increased complexity in fabrication and integration can lead to several defects, such as poor electrical interconnection due to misalignment between multiple upper and lower conductive features. Therefore, there is a need for continuous improvement of the semiconductor device fabrication process to address these defects and enhance its performance.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a first gate stack and a second gate stack disposed on a semiconductor substrate. One of the first gate stack and the second gate stack includes a plurality of gate layers, and an air gap exists between the first gate stack and the second gate stack. The semiconductor device also includes a first gate structure and a second gate structure disposed on the first gate stack and the second gate stack, respectively; and a first dielectric layer surrounding each lower sidewall of the first gate structure and each lower sidewall of the second gate structure. The semiconductor device further includes a first landing pad disposed on an upper surface and each upper sidewall of the first gate structure; and a first plug disposed on the first landing pad and electrically connected to the first gate structure. A width of the first gate structure is greater than a width of the first plug. Furthermore, the semiconductor device includes a second dielectric layer disposed on the first dielectric layer. The first landing pad and the first plug are surrounded by the second dielectric layer.

[0007] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a first lower plug and a second lower plug disposed on a semiconductor substrate. The semiconductor device also includes a first landing pad disposed on an upper surface and upper sidewalls of the first lower plug; and a first upper plug disposed on the first landing pad and electrically connected to the first lower plug. The width of the first lower plug is greater than the width of the first upper plug. The semiconductor device further includes a dielectric layer disposed on the semiconductor substrate. The first lower plug, the second lower plug, the first landing pad, and the first upper plug are disposed in the dielectric layer, and the dielectric layer includes an air gap disposed between the first lower plug and the second lower plug.

[0008] One embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a first gate stack and a second gate stack on a semiconductor substrate. One of the first gate stack and the second gate stack includes a plurality of gate layers, and an air gap exists between the first gate stack and the second gate stack. The method also includes forming a first gate structure and a second gate structure on the first gate stack and the second gate stack, respectively; and forming a first dielectric layer surrounding the first gate structure and the second gate structure. An upper surface and upper sidewalls of the first gate structure and an upper surface and upper sidewalls of the second gate structure protrude from the first dielectric layer. The method further includes performing a thermal processing step to form a first landing pad on the upper surface and upper sidewalls of the first gate structure, and to form a second landing pad on the upper surface and upper sidewalls of the second gate structure. Furthermore, the method includes forming a second dielectric layer to cover the first landing pad and the second landing pad; and forming a first plug in the second dielectric layer and on the first landing pad. The width of the first gate structure is greater than the width of the first plug.

[0009] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a first lower plug and a second lower plug on a semiconductor substrate; and forming a first dielectric layer surrounding the first lower plug and the second lower plug. An upper surface and upper sidewalls of the first lower plug and an upper surface and upper sidewalls of the second lower plug protrude from the first dielectric layer. The method also includes performing a heat treatment process to form a first landing pad on the upper surface and upper sidewalls of the first lower plug, and to form a second landing pad on the upper surface and upper sidewalls of the second lower plug; and after the heat treatment process, removing the first dielectric layer to form an opening between the first lower plug and the second lower plug. The preparation method further includes depositing a second dielectric layer in the opening and on the first and second landing pads to form an air gap in the opening and surrounded by the second dielectric layer; and forming a first upper plug in the second dielectric layer and on the first landing pad. The width of the first lower plug is greater than the width of the first upper plug.

[0010] This disclosure provides some embodiments of a semiconductor device and a method for fabricating the same. In some embodiments, the semiconductor device has a plurality of lower plugs disposed on a semiconductor substrate (or, when the semiconductor device is a gate-all-around (GAA) transistor, a plurality of gate structures disposed on a plurality of gate stacks); a landing pad disposed on an upper surface and upper sidewalls of one of the lower plugs; and an upper plug disposed on the landing pad. The landing pad provides an increased landing area for the upper plug to land on. Therefore, multiple misalignment problems between the upper plug and the lower plugs can be avoided or reduced. In some embodiments, an air gap is formed below the landing pad and between the lower plugs (or, when the semiconductor device is a GAA transistor, between the gate stacks). Therefore, parasitic capacitance between the lower plugs (or the gate stacks) can be reduced. Therefore, the yield of the semiconductor device can be improved, and the overall device performance can be improved.

[0011] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or designs of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0012] When referring to the embodiments and claims in conjunction with the drawings, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0013] Figure 1 This is a cross-sectional schematic diagram illustrating semiconductor elements according to some embodiments of the present disclosure.

[0014] Figure 2 This is a cross-sectional schematic diagram illustrating semiconductor elements of some embodiments of the present disclosure.

[0015] Figure 3 This is a cross-sectional schematic diagram illustrating semiconductor elements of some embodiments of the present disclosure.

[0016] Figure 4 This is a cross-sectional schematic diagram illustrating semiconductor elements of some embodiments of the present disclosure.

[0017] Figure 5 This is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure.

[0018] Figure 6This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of multiple lower emboli during semiconductor device formation, according to some embodiments of the present disclosure.

[0019] Figure 7 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure in which a first dielectric layer is formed during the formation of a semiconductor element to surround the intermediate stage of the lower plug.

[0020] Figure 8 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure in which multiple landing pads are formed during the intermediate stage of the lower embolism during the formation of semiconductor elements.

[0021] Figure 9 This is a top view schematic diagram illustrating an intermediate stage during the formation of a semiconductor device in some embodiments of the present disclosure, where a first dielectric layer is removed.

[0022] Figure 10 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure where a second dielectric layer is deposited during the formation of a semiconductor element to create an air gap in the intermediate stage between the lower plugs.

[0023] Figure 11 This is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure.

[0024] Figure 12 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of multiple gate structures on multiple gate stacks during the formation of a semiconductor device, according to some embodiments of the present disclosure.

[0025] Figure 13 This is a cross-sectional schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure during the formation of a first dielectric layer to surround the gate structure.

[0026] Figure 14 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of multiple landing pads on the gate structure during the formation of a semiconductor element, according to some embodiments of the present disclosure.

[0027] Figure 15 This is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure.

[0028] Figure 16 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure of a stage in which a sacrificial dielectric layer is formed during the formation of a semiconductor device and the sacrificial layer has a plurality of openings exposing a semiconductor substrate.

[0029] Figure 17 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of multiple barrier layers and multiple lower plugs in the opening during the formation of a semiconductor device, according to some embodiments of the present disclosure.

[0030] Figure 18 This is a cross-sectional schematic diagram illustrating an intermediate stage in the removal of the sacrificial dielectric layer during the formation of a semiconductor device, according to some embodiments of the present disclosure.

[0031] Figure 19 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure in which a first dielectric layer is formed during the formation of a semiconductor device to surround the intermediate stage between the lower plug and the barrier layer.

[0032] Figure 20 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure of the intermediate stage during semiconductor element formation, in which multiple landing pads are formed on the lower embolism and the barrier layer.

[0033] Figure 21 This is a cross-sectional schematic diagram illustrating an intermediate stage in the removal of the first dielectric layer during the formation of a semiconductor device according to some embodiments of the present disclosure.

[0034] Figure 22 This is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure.

[0035] Figure 23 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure where a second dielectric layer is deposited during the formation of a semiconductor element to create an air gap in the intermediate stage between the lower plugs.

[0036] Figure 24 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure where a sacrificial dielectric layer is formed during the formation of a semiconductor device, and the sacrificial dielectric layer has an intermediate stage in which multiple openings are exposed to expose multiple gate stacks.

[0037] Figure 25 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of multiple barrier layers and multiple lower plugs in the opening during the formation of a semiconductor device, according to some embodiments of the present disclosure.

[0038] Figure 26 This is a cross-sectional schematic diagram illustrating an intermediate stage in the removal of the sacrificial dielectric layer during the formation of a semiconductor device, according to some embodiments of the present disclosure.

[0039] Figure 27 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure in which a first dielectric layer is formed during the formation of a semiconductor device to surround the intermediate stage between the gate structure and the barrier layer.

[0040] Figure 28 This is a cross-sectional schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure during the formation of a plurality of landing pads on the gate structure and the barrier layer.

[0041] The reference numerals in the attached figures are explained as follows:

[0042] 30: Preparation method

[0043] 50: Preparation method

[0044] 70: Preparation method

[0045] 100: Semiconductor components

[0046] 101: Semiconductor substrate

[0047] 133: Lower embolization

[0048] 133LS: Lower sidewall

[0049] 133T: Upper surface

[0050] 133US: Upper sidewall

[0051] 135: Dielectric layer

[0052] 137: Landing pad

[0053] 140: Opening

[0054] 143: Dielectric layer

[0055] 150: Air gap

[0056] 150T: Surface

[0057] 153: Upper embolization

[0058] 200: Semiconductor components

[0059] 201: Semiconductor substrate

[0060] 203: Gate layer

[0061] 205a: Gate stack

[0062] 205b: Gate Stack

[0063] 207: Internal insulation structure

[0064] 209: Internal spacer

[0065] 211: External insulation structure

[0066] 213: Semiconductor Materials

[0067] 220: Air gap

[0068] 233: Gate structure

[0069] 233LS: Lower sidewall

[0070] 233T: Upper surface

[0071] 233US: Upper sidewall

[0072] 235: Dielectric layer

[0073] 237: Landing mat

[0074] 243: Dielectric layer

[0075] 253: Embolism

[0076] 300: Semiconductor components

[0077] 301: Semiconductor substrate

[0078] 323: Sacrificial Dielectric Layer

[0079] 330: Opening

[0080] 331: Barrier Layer

[0081] 331LS: Lower sidewall

[0082] 331T: Upper surface

[0083] 331US: Upper sidewall

[0084] 333: Subcutaneous embolization

[0085] 333LS: Lower sidewall

[0086] 333T: Upper surface

[0087] 333US: Upper sidewall

[0088] 335: Dielectric layer

[0089] 337: Landing mat

[0090] 337a: Internal

[0091] 337b: External

[0092] 340: Opening

[0093] 343: Dielectric layer

[0094] 350: Air gap

[0095] 353: Upper embolization

[0096] 400: Semiconductor Components

[0097] 401: Semiconductor substrate

[0098] 403: Gate layer

[0099] 405a: Gate Stack

[0100] 405b: Gate Stack

[0101] 407: Internal insulation structure

[0102] 411: External insulation structure

[0103] 413: Semiconductor Materials

[0104] 420: Air gap

[0105] 431: Barrier Layer

[0106] 433: Gate structure

[0107] 435: Dielectric layer

[0108] 437: Landing mat

[0109] 437a: Internal

[0110] 437b: external

[0111] 443: Dielectric layer

[0112] 453: Embolism

[0113] D1: Distance

[0114] D2: Distance

[0115] D3: Distance

[0116] D4: Distance

[0117] D5: Distance

[0118] D6: Distance

[0119] D7: Distance

[0120] D8: Distance

[0121] S11: Steps

[0122] S13: Steps

[0123] S15: Steps

[0124] S17: Steps

[0125] S19: Steps

[0126] S21: Steps

[0127] S31: Steps

[0128] S33: Steps

[0129] S35: Steps

[0130] S37: Steps

[0131] S39: Steps

[0132] S41: Steps

[0133] S51: Steps

[0134] S53: Steps

[0135] S55: Steps

[0136] S57: Steps

[0137] S59: Steps

[0138] S61: Steps

[0139] S63: Steps

[0140] S65: Steps

[0141] S67: Steps

[0142] W1: Width

[0143] W2: Width

[0144] W3: Width

[0145] W4: Width

[0146] W5: Width

[0147] W6: Width

[0148] W7: Width

[0149] W8: Width

[0150] W9: Width

[0151] W10: Width Detailed Implementation

[0152] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0153] Furthermore, for ease of explanation, this document may use spatial relative terms such as "beneath," "below," "lower," "above," and "upper" to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0154] Figure 1 This is a cross-sectional schematic diagram illustrating a semiconductor element 100 according to some embodiments of the present disclosure. In some embodiments, the semiconductor element 100 includes a semiconductor substrate 101; a plurality of lower plugs 133 disposed on the semiconductor substrate 101; a plurality of landing pads 137 disposed on the lower plugs 133; and a plurality of upper plugs 153 disposed on the landing pads 137. In some embodiments, the upper plugs 153 are electrically connected to the lower plugs 133 via the landing pads 137. Furthermore, the semiconductor element 100 includes a dielectric layer 143 (also represented as an interlayer metal dielectric (IMD) layer) disposed on the semiconductor substrate 101.

[0155] In some embodiments, the lower embolism 133, the landing pad 137, and the upper embolism 153 are disposed within a dielectric layer 143. In other words, the lower embolism 133, the landing pad 137, and the upper embolism 153 are surrounded by the dielectric layer 143. Furthermore, the dielectric layer 143 includes an air gap 150 disposed between adjacent lower embolisms 133. In some embodiments, the air gap 150 is surrounded by the dielectric layer 143. Additionally, it should be understood that in some embodiments, the landing pad 137 is disposed on each upper surface and each upper sidewall of the lower embolism 133. In some embodiments, each upper surface and each upper sidewall of the lower embolism 133 is covered by and in direct contact with the landing pad 137.

[0156] Figure 2 This is a cross-sectional schematic diagram illustrating a semiconductor element 200 according to some embodiments of the present disclosure. In some embodiments, the semiconductor element 200 includes a semiconductor substrate 201 that has been patterned to form a plurality of gate stacks 205a, 205b. At least one of the gate stacks 205a, 205b has a plurality of interleaved stacked semiconductor layers (semiconductor substrate 201) and a gate layer 203.

[0157] In some embodiments, the semiconductor element 200 also includes an inner insulating structure 207 disposed between the gate stacks 205a and 205b; and a plurality of outer insulating structures 211 disposed on each side of the gate stacks 205a and 205b, opposite to each sidewall of the inner insulating structure 207. In some embodiments, the semiconductor element 200 further includes a semiconductor material 213 disposed on the inner insulating structure 207 and the outer insulating structures 211, and the portion of the semiconductor material 213 between the gate stacks 205a and 205b includes an air gap 220. In some embodiments, the air gap 220 is surrounded by the semiconductor material 213.

[0158] In some embodiments, the upper surface of the semiconductor material 213 is substantially flush with the upper surface of the semiconductor substrate 201 (e.g., the upper surfaces of the gate stacks 205a, 205b). In this disclosure, the term "substantially" means preferably 90%, more preferably 95%, even more preferably 98%, and most preferably 99%. Furthermore, the semiconductor element 200 also includes a plurality of internal spacers 209 stacked between the semiconductor layers (semiconductor substrate 201) of the gate stacks 205a, 205b, and adjacent to opposite sides of the gate layers 203.

[0159] Please refer to the following: Figure 2 According to some embodiments, the semiconductor element 200 includes a plurality of gate structures 233 disposed on at least one of the gate stacks 205a, 205b; and a dielectric layer 235 (also referred to as an IMD layer) disposed on the gate stacks 205a, 205b and the semiconductor material 213, and surrounding the gate structures 233. It should be understood that the upper portions of each of the gate structures 233 protrude from the dielectric layer 235. In some embodiments, the upper surfaces and upper sidewalls of each of the gate structures 233 protrude from (or are not covered by) the dielectric layer 235.

[0160] In some embodiments, the semiconductor element 200 includes a plurality of landing pads 237 disposed on the gate structure 233; and a plurality of plugs 253 (also referred to as a plurality of upper plugs) disposed on the landing pads 237. In some embodiments, the plugs 253 are electrically connected to the gate structure 233 via the landing pads 237. Furthermore, the semiconductor element 200 includes a dielectric layer 243 (also referred to as an IMD layer) disposed on the dielectric layer 235. In some embodiments, the gate structure 233, the landing pads 237, and the plugs 253 are disposed within the dielectric layer 243. In other words, the gate structure 233, the landing pads 237, and the plugs 253 are surrounded by the dielectric layer 243.

[0161] Figure 3This is a cross-sectional schematic diagram illustrating a semiconductor element 300 according to some embodiments of the present disclosure. In some embodiments, the semiconductor element 300 includes a semiconductor substrate 301; a plurality of lower plugs 333 and a plurality of barrier layers 331 disposed on the semiconductor substrate 301; a plurality of landing pads 337 disposed on the lower plugs 333 and the barrier layers 331; and a plurality of upper plugs 353 disposed on the landing pads 337. In some embodiments, the upper plugs 353 are electrically connected to the lower plugs 333 via the landing pads 337. Furthermore, the semiconductor element 300 includes a dielectric layer 343 (also referred to as an IMD layer) disposed on the semiconductor substrate 301.

[0162] In some embodiments, the lower embolism 333 is disposed on the barrier layer 331, and extends at least one of the barrier layer 331 to surround the corresponding lower embolism 333. In other words, the barrier layer 331 covers each lower surface and each sidewall of the lower embolism 333. Furthermore, at least one of the landing pads 337 includes a plurality of outer surfaces 337b and an inner surface 337a, with the inner surface 337a disposed between the outer surfaces 337b. It should be understood that each inner surface 337a of the landing pad 337 is disposed on the lower embolism 333, and each outer surface 337b of the landing pad 337 is disposed on the barrier layer 331. In some embodiments, the inner surface 337a directly contacts each upper surface of the embolism 333, and the outer surface 337b directly contacts each upper surface and each upper sidewall of the barrier layer 331.

[0163] In some embodiments, the lower embolism 333, the landing pad 337, and the upper embolism 353 are disposed within a dielectric layer 343. In other words, the lower embolism 333, the landing pad 337, and the upper embolism 353 are surrounded by a dielectric layer 343. Furthermore, the dielectric layer 343 includes an air gap 353 disposed between adjacent lower embolisms 333 (e.g., adjacent barrier layers 331). In some embodiments, the air gap 350 is surrounded by the dielectric layer 343. In some embodiments, the upper embolism 353 is separated from the outer surface 337b of the landing pad 337 by a portion of the dielectric layer 343. However, in some embodiments, the upper embolism 353 directly contacts the outer surface 337b of the landing pad 337.

[0164] Figure 4 This is a cross-sectional schematic diagram illustrating a semiconductor element 400 according to some embodiments of the present disclosure. Similar to... Figure 2 Semiconductor element 200, semiconductor element 400 includes a semiconductor substrate 401, which has been patterned to form a plurality of gate stacks 405a, 405b. At least one of the gate stacks 405a, 405b has a plurality of interleaved stacked semiconductor layers (semiconductor substrate 401) and a gate layer 403.

[0165] In some embodiments, the semiconductor element 400 also includes an inner insulating structure 407 disposed between the gate stacks 405a and 405b; and a plurality of outer insulating structures 411 disposed on each side of the gate stacks 405a and 405b, opposite to each side of the inner insulating structure 407. In some embodiments, the semiconductor element 400 further includes a semiconductor material 413 disposed on the inner insulating structure 407 and the outer insulating structures 411, and the portion of the semiconductor material 413 between the gate stacks 405a and 405b includes an air gap 420. In some embodiments, the air gap 420 is surrounded by the semiconductor material 413.

[0166] In some embodiments, the upper surface of the semiconductor material 413 is substantially flush with the upper surface of the semiconductor substrate 401 (e.g., the upper surfaces of the gate stacks 405a, 405b). Furthermore, the semiconductor element 400 also includes a plurality of internal spacers 409 stacked between the semiconductor layers (semiconductor substrate 401) of the gate stacks 405a, 405b and adjacent to the opposite side of the gate layer 403.

[0167] Please refer to the following: Figure 4 According to some embodiments, a semiconductor device 400 includes a plurality of gate structures 433 and a plurality of barrier layers 431 disposed on at least one of the gate stacks 405a, 405b; and a dielectric layer 435 (also referred to as an IMD layer) disposed on the gate stacks 405a, 405b and the semiconductor material 413 and surrounding the gate structures 433. In some embodiments, the gate structures 433 are disposed on the barrier layers 431, and at least one of the barrier layers 431 extends to surround the corresponding gate structure 433. In other words, the barrier layers 431 cover each lower surface and each sidewall of the gate structures 433. Furthermore, it should be understood that each upper portion of the gate structures 433 and each barrier layer 431 protrudes from the dielectric layer 435. In some embodiments, each upper surface and each upper sidewall of the gate structures 433 and each upper surface and each upper sidewall of the barrier layers 431 protrude from the dielectric layer 435 (or are not covered).

[0168] In some embodiments, the semiconductor element 400 includes a plurality of landing pads 437 disposed on the gate structure 433 and a plurality of barrier layers 431; and a plurality of plugs 453 (also represented as a plurality of upper plugs) disposed on the landing pads 437. In some embodiments, the plugs 453 are electrically connected to the gate structure 433 via the landing pads 437. In some embodiments, at least one of the landing pads 437 includes a plurality of outer surfaces 437b and an inner surface 437a, with the inner surface 437a disposed between the outer surfaces 437b. It should be understood that each inner surface 437a of the landing pad 437 is disposed on the gate structure 433, and each outer surface 437b of the landing pad 437 is disposed on the barrier layer 431. In some embodiments, the inner surface 437a directly contacts the upper surface of the gate structure 433, and the outer surface 437b directly contacts each upper surface and each upper sidewall of the barrier layer 431.

[0169] Furthermore, the semiconductor element 400 includes a dielectric layer 443 (also referred to as an IMD layer) disposed on the dielectric layer 435. In some embodiments, the gate structure 433, the landing pad 437, and the plug 453 are disposed within the dielectric layer 443. In other words, the gate structure 433, the landing pad 437, and the plug 453 are surrounded by the dielectric layer 443. In some embodiments, the plug 543 is separated from the outer surface 437b of the landing pad 437 by a portion of the dielectric layer 443. However, in some embodiments, the plug 453 directly contacts the outer surface 437b of the landing pad 437.

[0170] Figure 5 This is a flowchart illustrating semiconductor elements (e.g., according to some embodiments of this disclosure) Figure 1 The method 10 for preparing a semiconductor element 100 includes steps S11, S13, S15, S17, S19 and S21. Figure 5 Steps S11 to S21 are explained in detail with reference to the following diagrams.

[0171] Figures 6 to 10 This is a cross-sectional view illustrating the intermediate processes during the formation of semiconductor device 100. For example... Figure 6As shown, the semiconductor substrate 101 may be part of an integrated circuit (IC) chip, which includes various passive and active electronic components, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), side-diffused MOS (LSMOS) transistors, high-voltage transistors, high-frequency transistors, fin field-effect transistors (FinFETs), other suitable IC components, or combinations thereof.

[0172] Depending on the IC manufacturing stage, the semiconductor substrate 101 may include various material layers (e.g., dielectric layers, semiconductor layers, and / or conductive layers) configured to form IC features (e.g., doped regions, insulating features, gate features, source / drain features, interconnect features, other features, or combinations thereof). For clarity, the semiconductor substrate 101 has been simplified. It should be understood that additional features may be added to the semiconductor substrate 101, and in other embodiments, some features as described below may be replaced, modified, or removed.

[0173] like Figure 6 As shown, according to some embodiments, the lower plug 133 is formed on the semiconductor substrate 101. The corresponding steps are described in the following... Figure 5 Step S11 of the fabrication method 10 shown. In some embodiments, the lower plug 133 comprises a conductive material, such as copper. In some embodiments, at least one of the lower plugs 133 has a lower width W1 and an upper width W2, wherein the lower width W1 is greater than the upper width W2. In some embodiments, there is a distance D1 between the upper portions of adjacent lower plugs 133. In some embodiments, the lower plug 133 has a tapered profile that tapers gradually from the semiconductor substrate 101.

[0174] Next, as Figure 7 As shown, according to some embodiments, a dielectric layer 135 is formed to surround the lower portions of the lower plugs 133 and expose the upper portions of the lower plugs 133. The corresponding steps are described in... Figure 5Step S13 of the fabrication method 10 shown. In some embodiments, the dielectric layer 135 comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or the like. The fabrication technique of the dielectric layer 135 may include depositing a dielectric material (not shown) on the semiconductor substrate 101 and the lower plug 133 by a deposition process, such as a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a physical vapor deposition (PVD) process; and removing the upper portion of the dielectric layer 135 by a chemical mechanical polishing (CMP) process or an etch-back process.

[0175] After the upper portion of dielectric layer 135 is removed, the upper portions of each of the lower plugs 133 protrude from dielectric layer 135. In some embodiments, according to certain examples, the upper surfaces 133T and upper sidewalls 133US of each of the lower plugs 133 protrude and are exposed, while the lower sidewalls 133LS of each of the lower plugs 133 are covered by dielectric layer 135.

[0176] Next, as Figure 8 As shown, according to some embodiments, a heat treatment process is performed to form a plurality of landing pads 137 on each of the upper surfaces 133T and upper sidewalls 133US of the lower plug 133. The corresponding steps are described in... Figure 5 Step S15 of the preparation method 10 shown. In some embodiments, during a heat treatment process, a silicon-containing gas is used to selectively form the landing pad 137 on the exposed upper surface 133T and the exposed upper sidewall 133US of the lower embolism 133. In some embodiments, the landing pad 137 comprises copper germanide (Cu3Ge). Because the landing pad 137 provides an increased landing area for the upper embolism subsequently formed thereon, misalignment problems between the subsequently formed upper embolism and the lower embolism 133 can be avoided or reduced.

[0177] like Figure 9 As shown, according to some embodiments, after the landing pad 137 is formed, the dielectric layer 135 is removed to form an opening 140 between adjacent lower plugs 137. The corresponding steps are described in the following... Figure 5 Step S17 of the preparation method 10 shown. In some embodiments, the dielectric layer 135 is removed by a stripping process (e.g., a wet stripping process) and / or an ashing process (e.g., a plasma ashing process). Once the dielectric layer 135 is removed, the lower sidewalls 133LS of the lower plug 133 are exposed.

[0178] Next, as Figure 10 As shown, according to some embodiments, dielectric layer 143 is deposited on Figure 9 Structurally, and due to an overhang effect, an air gap 150 is formed in an opening 140 between adjacent lower plugs 133. In some embodiments, a dielectric layer 143 is deposited on the semiconductor substrate 101, the lower plugs 133, and the landing pad 137, and the opening 140 (see reference) Figure 9 The dielectric layer 143 is partially filled. The corresponding steps are explained in the following... Figure 5 Step S19 of the preparation method 10 shown. In some embodiments, the exposed lower sidewall 133LS of the lower plug 133 is covered by a dielectric layer 143.

[0179] Furthermore, in some embodiments, an air gap 150 is formed beneath the landing pad 137 and surrounded by a dielectric layer 143. In some embodiments, the upper surfaces 133T of the lower plugs 133 are higher than the uppermost surface 150T of the air gap 150. Some materials and processes used to form the dielectric layer 143 are similar to or the same as those used to form the dielectric layer 135, and will not be described in detail again herein. Because of the air gap 150 between the lower plugs 133, parasitic capacitance between the lower plugs 133 can be reduced.

[0180] Please refer back to this page. Figure 1 According to some embodiments, after the dielectric layer 143 is formed, a plurality of upper plugs 153 are formed in the dielectric layer 143 and on the landing pad 137. The corresponding steps are described in... Figure 5 Step S21 in the preparation method 10 shown. In some embodiments, the upper plug 153 comprises a conductive material, such as copper, tungsten, aluminum, titanium, tantalum, gold, silver, or a combination thereof.

[0181] Furthermore, the fabrication technique for the upper plug 153 may include etching the dielectric layer 143 to form a plurality of openings (not shown) to expose the corresponding landing pads 137; depositing a conductive material (not shown) in the openings and on the dielectric layer 143; and planarizing the conductive material so that the remaining upper surfaces of the conductive material (e.g., the upper plug 153) are substantially flush with the upper surface of the dielectric layer 143. After the upper plug 153 is formed, a semiconductor element 100 is obtained. Please refer to... Figure 1 and Figure 6 At least one of the widths W1 and W2 of the lower plug 133 is greater than the width W3 of the upper plug 153, and the distance D2 between adjacent upper plugs 153 is greater than the distance between adjacent lower plugs 133.

[0182] Figure 11This is a flowchart illustrating semiconductor elements (e.g., according to some embodiments of this disclosure) Figure 2 The method 30 for preparing a semiconductor element 200 includes steps S31, S33, S35, S37, S39 and S41. Figure 11 Steps S31 to S41 are explained in detail with reference to the following diagrams.

[0183] Figures 12 to 14 This is a cross-sectional view illustrating the intermediate processes during the formation of semiconductor device 200. For example... Figure 12 As shown, according to some embodiments, a patterned semiconductor substrate 201 is used to form gate stacks 205a and 205b, and the gate structure 233 is formed on the gate stacks 205a and 205b.

[0184] The semiconductor substrate 201 may be a semiconductor wafer, such as a silicon wafer. Additionally, the semiconductor substrate 201 may comprise elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and gallium arsenide phosphide (GaInAsP).

[0185] In some embodiments, the semiconductor substrate 201 includes an epitaxial layer. For example, the semiconductor substrate 201 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 201 is a semiconductor-on-insulator (SOI) substrate, which may include a substrate, a buried oxide layer, and a semiconductor layer, wherein the buried oxide layer is located on the substrate, the semiconductor layer is located on the buried oxide layer, and the SOI substrate is, for example, a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The SOI substrate can be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and / or other applicable methods.

[0186] The semiconductor layers (semiconductor substrate 201) and the gate layers 203 are stacked alternately in gate stacks 205a and 205b, and a plurality of internal spacers 209 are formed on opposite sides of the gate layers 203 and sandwiched between the semiconductor layers (semiconductor substrate 201) in the gate stacks 205a and 205b. In some embodiments, the internal spacers 209 comprise silicon oxide, silicon nitride, or other applicable dielectric materials. The fabrication technique of the internal spacers 209 may include recessing the gate layers 203 laterally to form a plurality of air gaps between the semiconductor layers (semiconductor substrate 201) of the gate stacks 205a and 205b; depositing a dielectric material in the air gaps; and removing excess portions of the dielectric material outside the air gaps.

[0187] Some of the materials and processes used to form the inner insulating structure 207 and the outer insulating structure 211 are similar to those used to form the inner spacer 209, and their detailed description will not be repeated herein. Furthermore, due to the high aspect ratio of the aperture between the gate stacks 205a and 205b, semiconductor material 213 is formed on the inner insulating structure 207 and the outer insulating structure 211, and an air gap 220 is formed on the inner insulating structure 207. In some embodiments, the air gap 220 is surrounded by semiconductor material 213.

[0188] Semiconductor material 213 can be any suitable material, including, but not limited to, silicon (Si) or silicon germanium (SiGe). The fabrication technique for semiconductor material 213 may include a deposition process, such as a CVD process, an ALD process, or a PVD process. The fabrication technique for semiconductor material 213 may include a deposition process followed by a planarization process (e.g., a CMP process). After semiconductor material 213 is formed, the gate structure 233 is formed on the gate stacks 205a and 205b. The corresponding steps are described in the following... Figure 11 Steps S31 and S33 in the preparation method 30 shown.

[0189] In some embodiments, the gate structure 233 comprises a conductive material, such as copper. In some embodiments, at least one of the gate structures 233 has a width W4. In some embodiments, there is a distance D3 between the upper portions of adjacent gate structures 233. It should be understood that the parasitic capacitance between the gate stacks 205a and 205b can be reduced due to the air gap 220 between the gate stacks 205a and 205b.

[0190] Next, as Figure 13 As shown, according to some embodiments, a dielectric layer 235 is formed to surround and expose the upper portions of the gate structure 233. The corresponding steps are described in... Figure 11 Step S35 of the fabrication method 30 shown. In some embodiments, the dielectric layer 235 comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon oxynitride, silicon oxynitride, or the like. The fabrication technique of the dielectric layer 235 may include depositing a dielectric material (not shown) on the semiconductor material 213, the gate stacks 205a, 205b, and the gate structure 233 by a deposition process, such as a CVD process, an ALD process, or a PVD process; and removing the upper portion of the dielectric layer 235 by a CMP process or an etch-back process.

[0191] After the upper portion of dielectric layer 235 is removed, the upper portions of the gate structures 233 protrude from dielectric layer 235. In some embodiments, according to certain examples, the upper surfaces 233T and upper sidewalls 233US of the gate structures 233 protrude and are exposed, while the lower sidewalls 233LS of the gate structures 233 are covered by dielectric layer 235.

[0192] Next, as Figure 14 As shown, according to some embodiments, a heat treatment process is performed to form a plurality of landing pads 237 on each of the upper surfaces 233T and upper sidewalls 233US of the gate structure 233. The corresponding steps are described in... Figure 11Step S37 of the fabrication method 30 shown. In some embodiments, during a heat treatment process, a silicon-containing gas is used to selectively form the landing pad 237 on the exposed upper surface 233T and the exposed upper sidewall 233US of the gate structure 233. In some embodiments, the landing pad 237 comprises copper germanide (Cu3Ge). Because the landing pad 237 provides an increased landing area for the upper plug subsequently formed thereon, misalignment problems between the subsequently formed plug and the gate structure 233 can be avoided or reduced.

[0193] Please refer back to this page. Figure 2 According to some embodiments, a dielectric layer 243 is formed on a dielectric layer 235 and covers the landing pad 237, and the plug 253 is formed in the dielectric layer 243 and on the landing pad 237. The corresponding steps are described in... Figure 11 Steps S39 and S41 of the preparation method 30 shown. Some materials and processes used to form dielectric layer 243 are similar to or the same as those used to form dielectric layer 235, and their detailed description will not be repeated herein. In some embodiments, the plug 253 comprises a conductive material, such as copper, tungsten, aluminum, titanium, tantalum, gold, silver, or a combination thereof.

[0194] Furthermore, the fabrication technique for the plug 253 may include etching the dielectric layer 243 to form multiple openings (not shown) to expose the corresponding landing pads 237; depositing a conductive material (not shown) in the openings and on the dielectric layer 243; and planarizing the conductive material so that the remaining conductive material (e.g., the plug 253) is substantially flush with the upper surface of the dielectric layer 243. After the plug 253 is formed, a semiconductor element 200 is obtained. Please refer to... Figure 2 and Figure 12 The width W4 of the gate structure 233 is greater than the width W5 of the plug 253, and the distance D4 between adjacent plugs 253 is greater than the distance D3 between adjacent gate stacks 205a and 205b.

[0195] Figure 15 This is a flowchart illustrating semiconductor elements (e.g., according to some embodiments of this disclosure) Figure 3 The method 50 for preparing a semiconductor element 300 includes steps S51, S53, S55, S57, S59, S61, S63, S65 and S67. Figure 15 Steps S51 to S67 are explained in detail with reference to the following diagrams.

[0196] Figures 16 to 22 This is a cross-sectional view illustrating the intermediate processes during the formation of semiconductor device 300. For example... Figure 16As shown, according to some embodiments, a sacrificial dielectric layer 323 having a plurality of openings 330 is formed on a semiconductor substrate 301. In some embodiments, the semiconductor substrate 301 is partially exposed by at least one of the openings 330. The corresponding steps are described in the following... Figure 15 Step S51 in the preparation method 50 shown.

[0197] Semiconductor substrate 301 may be similar to semiconductor substrate 101 as described above, and will not be described again herein. Sacrificial dielectric layer 323 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon oxynitride, silicon oxynitride, or the like. In some embodiments, the fabrication technique for sacrificial dielectric layer 323 includes depositing a dielectric material (not shown) on semiconductor substrate 301; and etching the dielectric material using an anisotropic etching process to form the opening 330, such that the opening 330 has a tapered profile that gradually tapers away from semiconductor substrate 301.

[0198] In some other embodiments, the fabrication technique of the sacrificial dielectric layer 323 includes forming a plurality of sacrificial patterns (not shown) on a semiconductor substrate 301; forming a sacrificial dielectric material (not shown) to surround the sacrificial patterns; planarizing the sacrificial dielectric material so that the upper surface of the remaining sacrificial dielectric material (e.g., the sacrificial dielectric layer 323) is substantially flush with each upper surface of the sacrificial patterns; and removing the sacrificial patterns.

[0199] Next, the barrier layer 331 is formed to line the lower surface and sidewalls of the opening 330, and the lower plug 333 is formed on and surrounded by the barrier layer 331. The corresponding steps are described in the following... Figure 15 Steps S53 and S55 of the fabrication method 50 are shown. In some embodiments, the barrier layer 331 comprises a titanium-containing material, such as titanium or titanium nitride, and the lower plug 333 comprises copper. The fabrication techniques of the barrier layer 331 and the lower plug 333 may include multiple deposition processes, such as CVD, ALD, PVD, sputtering, or plating. After the deposition process, a planarization process (e.g., a CMP process) may be performed to make the upper surfaces of the barrier layer 331 and the upper surfaces of the lower plug 333 substantially flush with the upper surface of the sacrificial dielectric layer 323.

[0200] In some embodiments, at least one of the lower plugs 333 and the corresponding barrier layer 331 share a lower width W6 and an upper width W7, with the lower width W6 being greater than the upper width W7. That is, according to some embodiments, at least one of the lower plugs 333 and the corresponding barrier layer 331 share a tapered profile that tapers gradually from the direction away from the semiconductor substrate 101. Since the thickness of the barrier layer 331 is too small relative to the thickness of the lower plugs 333, the lower width of at least one of the lower plugs 333 can be approximately the same as the width W6, and the upper width of at least one of the lower plugs 333 can be approximately the same as the width W7. In other words, each lower width of the lower plugs 333 is greater than each upper width of the lower plugs 333, and at least one of the lower plugs 333 has a tapered profile that tapers gradually from the direction away from the semiconductor substrate 101.

[0201] Furthermore, in some embodiments, there is a distance D5 between the upper portions of adjacent barrier layers 331. Since the thickness of the barrier layers 331 is too small compared to the thickness of the lower plugs 333, the distance between adjacent lower plugs 333 is approximately the same as the distance D5.

[0202] like Figure 18 As shown, according to some embodiments, after the barrier layer 331 and the lower plug 333 are formed, the sacrificial dielectric layer 323 is removed. The corresponding steps are described in... Figure 15 Step S57 in the fabrication method 50 shown. In some embodiments, the sacrificial dielectric layer 323 is removed by a stripping process (e.g., a wet stripping process) and / or an ashing process (e.g., a plasma ashing process).

[0203] Next, as Figure 19 As shown, according to some embodiments, a dielectric layer 335 is formed to surround the lower portions of the lower plug 333 and the barrier layer 331, and the upper portions of the lower plug 333 and the barrier layer 331 are exposed. The corresponding steps are described in the following... Figure 15 Step S59 of the fabrication method 50 shown. Some materials and processes used to form the dielectric layer 335 are similar to or the same as those used to form the sacrificial dielectric layer 323, and their detailed descriptions will not be repeated here. The fabrication technique of the dielectric layer 335 includes depositing a dielectric material (not shown) on the semiconductor substrate 301, the lower plug 333, and the barrier layer 331 by a deposition process, such as a CVD process, an ALD process, or a PVD process; and removing the upper portion of the dielectric layer 335 by a CMP process or an etch-back process.

[0204] After the upper portion of dielectric layer 335 is removed, the upper portions of the lower plugs 333 and the upper portions of barrier layer 331 protrude from dielectric layer 335. In some embodiments, according to certain examples, the upper surfaces 333T and upper sidewalls 333US of the lower plugs 333 and the upper sidewalls 331US of barrier layer 331 protrude (and / or are exposed), while the lower sidewalls 333LS of the lower plugs 333 and the lower sidewalls 331LS of barrier layer 331 are covered by dielectric layer 335.

[0205] In some embodiments, the formation of dielectric layer 335 is omitted. In these examples, the sacrificial dielectric layer 323 is partially removed so that the lower portion of the remaining sacrificial dielectric layer 323 covers the lower sidewalls 331LS of the barrier layer 331 and the lower sidewalls 333LS of the lower plug 333.

[0206] Then, as Figure 20 As shown, according to some embodiments, a heat treatment process is performed to form the landing pad 337 on each of the upper surfaces 333T and upper sidewalls 333US of the lower embolism 333 and on each of the upper surfaces 331T and upper sidewalls 331US of the barrier layer 331. The corresponding steps are described in... Figure 15 Step S61 in the preparation method 50 shown. In some embodiments, at least one of the landing pads 337 includes a plurality of outer surfaces 337b and inner surfaces 337a, with the inner surfaces 337a disposed between the outer surfaces 337b.

[0207] In some embodiments, during a heat treatment process, a silicon-containing gas is used to selectively form the interiors 337a of the landing pad 337 on the exposed upper surface 333T of the lower embolism 333, and together form the exteriors 337b of the landing pad 337 on the exposed upper surface 331T and the upper sidewall 331US of the barrier layer 331. In some embodiments, the interiors 337a and the exteriors 337b comprise different materials, but their simultaneous fabrication technique includes a heat treatment process. In some embodiments, the interiors 337a comprise tungsten silicide, while the exteriors 337b comprise titanium silicide. Because the landing pad 337 provides an increased landing area for the upper embolism subsequently formed thereon, misalignment problems between the subsequently formed upper and lower embolism 333 can be avoided or reduced.

[0208] like Figure 21 As shown, after the landing pad 337 is formed, the dielectric layer 335 is removed to form an opening 340 between adjacent lower plugs 337 (or between adjacent barrier layers 331 surrounding the lower plugs 337). The corresponding steps are described in... Figure 15Step S63 of the fabrication method 50 shown. In some embodiments, the sacrificial dielectric layer 335 is removed by a stripping process (e.g., a wet stripping process) and / or an ashing process (e.g., a plasma ashing process). Once the dielectric layer 335 is removed, the lower sidewalls 331LS of the barrier layer 331 are exposed.

[0209] Next, as Figure 22 As shown, according to some embodiments, dielectric layer 343 is deposited on Figure 21 Structurally, and due to an overhang effect, an air gap 350 is formed in an opening 340 between adjacent lower plugs 333 (or between adjacent barrier layers 311). In some embodiments, a dielectric layer 343 is deposited on the semiconductor substrate 301, the lower plugs 333, the barrier layers 331, and the landing pad 337, and the opening 340 (see reference) Figure 21 The dielectric layer 343 partially fills the area. The corresponding steps are explained in the following... Figure 15 Step S65 of the fabrication method 50 shown. In some embodiments, the exposed lower sidewall 331LS of the barrier layer 331 is covered by a dielectric layer 343.

[0210] Furthermore, in some embodiments, an air gap 350 is formed beneath the landing pad 337 and is surrounded by a dielectric layer 343. In some embodiments, the upper surfaces 333T of the lower plugs 333 are higher than the uppermost surface of the air gap 350. Some materials and processes used to form the dielectric layer 343 are similar to or the same as those used to form the dielectric layer 335, and their detailed descriptions will not be repeated herein. Because of the air gap 350 between the lower plugs 333, the parasitic capacitance between the lower plugs 333 can be reduced.

[0211] Please refer to Figure 3 According to some embodiments, after the dielectric layer 343 is formed, the upper plug 353 is formed in the dielectric layer 343 and on the landing pad 337. The corresponding steps are described in... Figure 15 Step S67 of the preparation method 50 shown. In some embodiments, the upper plug 353 comprises a conductive material, such as copper, tungsten, aluminum, titanium, tantalum, gold, silver, or a combination thereof.

[0212] Furthermore, the fabrication technique for the upper plug 353 may include etching the dielectric layer 343 to form multiple openings (not shown) to expose the corresponding landing pads 337; depositing a conductive material (not shown) in the openings and on the dielectric layer 343; and planarizing the conductive material so that the remaining upper surfaces of the conductive material (e.g., the upper plug 353) are substantially flush with the upper surface of the dielectric layer 343. After the upper surfaces 353 are formed, a semiconductor element 300 is obtained. Please refer to... Figure 3 and Figure 17 The widths W6 and W7, at least one of which is greater than the width W8, and the distance from D6 is greater than the distance from D5.

[0213] Figure 23 This is a flowchart illustrating semiconductor elements (e.g., according to some embodiments of this disclosure) Figure 4 The semiconductor device 400) is prepared by a method 70, and the preparation method 70 includes steps S71, S73, S75, S77, S79, S81, S83, S85 and S87. Figure 23 Steps S71 to S87 are explained in detail with reference to the following diagrams.

[0214] Figures 24 to 28 This is a cross-sectional view illustrating the intermediate processes during the formation of semiconductor device 400. For example... Figure 24 As shown, the semiconductor substrate 401, gate stacks 405a and 405b, gate layer 403, internal spacer 409, internal insulating structure 407, external insulating structure 411, and semiconductor material 413 can be similar to the semiconductor substrate 201, gate stacks 205a and 205b, gate layer 203, internal spacer 209, internal insulating structure 207, external insulating structure 211, and semiconductor material 213 of the semiconductor element 200, and their descriptions will not be repeated in the text.

[0215] Furthermore, in some embodiments, an air gap 420 is formed on the inner insulating structure 407 due to the high aspect ratio of the aperture between the gate stacks 405a and 405b. In some embodiments, the air gap 420 is surrounded by a semiconductor material 413. It should be understood that the presence of the air gap 420 between the gate stacks 405a and 405b reduces the parasitic capacitance between them.

[0216] like Figure 24 As shown, according to some embodiments, a sacrificial dielectric layer 423 having a plurality of openings 430 is formed on the semiconductor material 413 and the gate stacks 405a, 405b. In some embodiments, at least one of the gate stacks 405a, 405b is partially exposed by a corresponding opening 430. The corresponding steps are described in the following... Figure 23Steps S71 and S73 in the preparation method 70 shown.

[0217] The sacrificial dielectric layer 423 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon oxynitride, silicon oxynitride, or the like. In some embodiments, the fabrication technique of the sacrificial dielectric layer 423 includes depositing a dielectric material (not shown) on the semiconductor material 413 and the gate stacks 405a, 405b; and etching the dielectric material to form the opening 430. In some other embodiments, the fabrication technique of the sacrificial dielectric layer 423 includes forming a plurality of sacrificial patterns (not shown) on the semiconductor material 413 and the gate stacks 405a, 405b; forming a sacrificial dielectric material (not shown) around the sacrificial patterns; planarizing the sacrificial dielectric material so that the upper surface of the remaining sacrificial dielectric material (e.g., sacrificial dielectric layer 323) is substantially flush with the upper surfaces of the sacrificial patterns; and removing the sacrificial patterns.

[0218] Next, the barrier layer 431 is formed to line the lower surface and sidewalls of the opening 430, and the gate structure 433 is formed on and surrounded by the barrier layer 431. The corresponding steps are described in the following... Figure 23 Steps S75 and S77 of the fabrication method 70 are shown. In some embodiments, the barrier layer 431 comprises a titanium-containing material, such as titanium or titanium nitride, and the gate structure 433 comprises copper. The fabrication techniques of the barrier layer 431 and the gate structure 433 may include multiple deposition processes, such as CVD, ALD, PVD, sputtering, or plating. After the deposition process, a planarization process (e.g., a CMP process) may be performed to make the upper surfaces of the barrier layer 331 and the upper surfaces of the gate structure 433 substantially flush with the upper surface of the sacrificial dielectric layer 423.

[0219] In some embodiments, at least one of the gate structures 433 and the corresponding barrier layer 431 together have a width W9. Since the thickness of the barrier layer 431 is too small compared to the thickness of the gate structure 433, the width of at least one of the gate structures 433 may be approximately the same as the width W9. Furthermore, in some embodiments, there is a distance D7 between the upper portions of adjacent barrier layers 431. Since the thickness of the barrier layer 431 is too small compared to the thickness of the gate structure 433, the distance between adjacent gate structures 433 is approximately the same as the distance D7.

[0220] like Figure 26 As shown, according to some embodiments, the sacrificial dielectric layer 423 is removed after the barrier layer 431 and the gate structure 433 are formed. The corresponding steps are described in... Figure 23Step S79 in the preparation method 70 shown. In some embodiments, the sacrificial dielectric layer 423 is removed by a stripping process (e.g., a wet stripping process) and / or an ashing process (e.g., a plasma ashing process).

[0221] Next, as Figure 27 As shown, according to some embodiments, a dielectric layer 435 is formed to surround the lower portions of the gate structure 433 and the barrier layer 431 and expose the upper portions of the gate structure 433 and the barrier layer 431. The corresponding steps are described in the following... Figure 23 Step S81 of the fabrication method 70 shown. Some materials and processes used to form the dielectric layer 435 are similar to or the same as those used to form the sacrificial dielectric layer 423, and their detailed descriptions will not be repeated herein. The fabrication technique for the dielectric layer 435 includes depositing a dielectric material (not shown) on the semiconductor material 413 and the gate stacks 405a, 405b, on the gate structure 433 and the barrier layer 431 by a deposition process, such as a CVD process, an ALD process, or a PVD process; and removing the top portion of the dielectric layer 435 by a CMP process or an etch-back process.

[0222] After the upper portion of dielectric layer 435 is removed, the upper portions of the gate structure 433 and the upper portions of the barrier layer 431 protrude from dielectric layer 435. In some embodiments, according to certain examples, the upper surfaces 433T and upper sidewalls 433US of the gate structure 433 and the upper surfaces 431T and upper sidewalls 431US of the barrier layer 431 protrude (and / or are exposed), while the lower sidewalls 433LS of the gate structure 433 and the lower sidewalls 431LS of the barrier layer 431 are covered by dielectric layer 435.

[0223] In some embodiments, the formation of dielectric layer 435 is omitted. In these examples, the sacrificial dielectric layer 423 is partially removed so that the upper portion of the sacrificial dielectric layer 423 remains to cover the lower sidewalls 431LS of the barrier layer 431 and the lower sidewalls 433LS of the gate structure 433.

[0224] Then, as Figure 28 As shown, according to some embodiments, a heat treatment process is performed to form the landing pad 437 on each of the upper surfaces 433T and upper sidewalls 433US of the gate structure 433, and on each of the upper surfaces 431T and upper sidewalls 431US of the barrier layer 431. The corresponding steps are described in... Figure 23Step S83 in the preparation method 70 shown. In some embodiments, at least one of the landing pads 437 includes a plurality of outer surfaces 437b and an inner surface 437a, with the inner surface 437a disposed between the outer surfaces 437b.

[0225] In some embodiments, during a heat treatment process, a silicon-containing gas is used to selectively form the interiors 437a of the landing pad 437 on the exposed upper surface 433T of the gate structure 433, and together form the exteriors 437b of the landing pad 437 on the exposed upper surface 431T and the upper sidewall 431US of the barrier layer 431. In some embodiments, the interiors 437a and the exteriors 437b comprise different materials, but their simultaneous fabrication technique includes a heat treatment process. In some embodiments, the interiors 437a comprise tungsten silicide, while the exteriors 437b comprise titanium silicide. Because the landing pad 437 provides an increased landing area for the upper embolism subsequently formed thereon, misalignment problems between the subsequently formed upper and lower emboli 433 can be avoided or reduced.

[0226] Please refer back to this page. Figure 4 According to some embodiments, a dielectric layer 443 is formed on a dielectric layer 435 and covers the landing pad 437, while the plug 453 is formed in the dielectric layer 443 and on the landing pad 437. The corresponding steps are described in... Figure 23 Steps S85 and S87 of the preparation method 70 shown. Some materials and processes used to form dielectric layer 443 are similar to or the same as those used to form dielectric layer 435, and their detailed descriptions will not be repeated herein. In some embodiments, the plug 453 comprises a conductive material, such as copper, tungsten, aluminum, titanium, tantalum, gold, silver, or a combination thereof.

[0227] Furthermore, the fabrication technique for the plug 453 may include etching the dielectric layer 443 to form multiple openings (not shown) to expose the corresponding landing pads 437; depositing a conductive material (not shown) in the openings and on the dielectric layer 443; and planarizing the conductive material so that the remaining upper surfaces of the conductive material (e.g., the plug 453) are substantially flush with the upper surface of the dielectric layer 443. After the plug 453 is formed, a semiconductor element 400 is obtained. Please refer to... Figure 4 and Figure 25 Width W9 is greater than width W10, while distance D8 is greater than distance D7.

[0228] This disclosure provides several embodiments of semiconductor elements 100, 200, 300, 400 and methods for their fabrication. In some embodiments, at least one of the semiconductor elements 100, 200, 300, and 400 includes a plurality of conductive features (e.g., the lower plug 133 of semiconductor element 100, the gate structure 233 of semiconductor element 200, the lower plug 333 of semiconductor element 300, and the gate structure 433 of semiconductor element 400); a plurality of landing pads (e.g., the landing pad 137 of semiconductor element 100, the landing pad 237 of semiconductor element 200, the landing pad 337 of semiconductor element 300, and the landing pad 437 of semiconductor element 400) disposed on each upper surface and each upper sidewall of the conductive features; and a plurality of upper plugs (e.g., the upper plug 153 of semiconductor element 100, the plug 253 of semiconductor element 200, the lower plug 353 of semiconductor element 300, and the plug 453 of semiconductor element 400) disposed on the landing pads. The landing pad provides multiple increased landing areas for the upper embolus to land on. Therefore, multiple misalignment problems between the upper embolus and the conductive features can be avoided or reduced, and contact resistance can be reduced.

[0229] Furthermore, multiple air gaps are formed under the landing pad and between the conductive features (or between the gate stacks under the conductive features). For example, air gap 150 of semiconductor element 100 is formed between the lower plugs 133, air gap 220 of semiconductor element 200 is formed between gate stacks 205a and 205b, air gap 350 of semiconductor element 300 is formed between the lower plugs 333, and air gap 420 of semiconductor element 400 is formed between gate stacks 405a and 405b. Therefore, parasitic capacitance between the conductive features or the gate stacks can be reduced. Therefore, the yield of semiconductor elements 100, 200, 300, and 400 can be improved, and the overall device performance can be improved.

[0230] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a first lower plug and a second lower plug disposed on a semiconductor substrate. The semiconductor device also includes a first landing pad disposed on an upper surface and upper sidewalls of the first lower plug; and a first upper plug disposed on the first landing pad and electrically connected to the first lower plug. The width of the first lower plug is greater than the width of the first upper plug. The semiconductor device further includes a dielectric layer disposed on the semiconductor substrate. The first lower plug, the second lower plug, the first landing pad, and the first upper plug are disposed within the dielectric layer, and the dielectric layer includes an air gap disposed between the first lower plug and the second lower plug.

[0231] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a first gate stack and a second gate stack disposed on a semiconductor substrate. One of the first gate stack and the second gate stack includes a plurality of gate layers, and an air gap is provided between the first gate stack and the second gate stack. The semiconductor device also includes a first gate structure and a second gate structure disposed on the first gate stack and the second gate stack, respectively; and a first dielectric layer surrounding each lower sidewall of the first gate structure and each lower sidewall of the second gate structure. The semiconductor device further includes a first landing pad disposed on an upper surface and each upper sidewall of the first gate structure; and a first plug disposed on the first landing pad and electrically connected to the first gate structure. A width of the first gate structure is greater than a width of the first plug. Furthermore, the semiconductor device includes a second dielectric layer disposed on the first dielectric layer. The first landing pad and the first plug are surrounded by the second dielectric layer.

[0232] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a first lower plug and a second lower plug on a semiconductor substrate; and forming a first dielectric layer surrounding the first lower plug and the second lower plug. An upper surface and upper sidewalls of the first lower plug and an upper surface and upper sidewalls of the second lower plug protrude from the first dielectric layer. The method also includes performing a heat treatment process to form a first landing pad on the upper surface and upper sidewalls of the first lower plug, and to form a second landing pad on the upper surface and upper sidewalls of the second lower plug; and after the heat treatment process, removing the first dielectric layer to form an opening between the first lower plug and the second lower plug. The preparation method further includes depositing a second dielectric layer in the opening and on the first and second landing pads to form an air gap in the opening and surrounded by the second dielectric layer; and forming a first upper plug in the second dielectric layer and on the first landing pad. The width of the first lower plug is greater than the width of the first upper plug.

[0233] One embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a first gate stack and a second gate stack on a semiconductor substrate. One of the first gate stack and the second gate stack includes a plurality of gate layers, and an air gap exists between the first gate stack and the second gate stack. The method also includes forming a first gate structure and a second gate structure on the first gate stack and the second gate stack, respectively; and forming a first dielectric layer surrounding the first gate structure and the second gate structure. An upper surface and upper sidewalls of the first gate structure and an upper surface and upper sidewalls of the second gate structure protrude from the first dielectric layer. The method further includes performing a thermal processing step to form a first landing pad on the upper surface and upper sidewalls of the first gate structure, and to form a second landing pad on the upper surface and upper sidewalls of the second gate structure. Furthermore, the method includes forming a second dielectric layer to cover the first landing pad and the second landing pad; and forming a first plug in the second dielectric layer and on the first landing pad. The width of the first gate structure is greater than the width of the first plug.

[0234] The embodiments described in this disclosure have several advantageous features. By forming a landing pad between a lower plug and an upper plug (or a gate structure and a plug in the gate structure), multiple misalignment problems can be avoided or reduced, thus reducing contact resistance. Furthermore, by forming an air gap under the landing pad and between adjacent lower plugs (or between adjacent gate stacks), parasitic capacitance can be reduced. Therefore, the yield of the semiconductor device can be improved, and the overall device performance can be enhanced.

[0235] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0236] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor device, comprising: a first gate stack and a second gate stack disposed on a semiconductor substrate, wherein one of the first gate stack and the second gate stack comprises a plurality of gate layers, and wherein the first gate stack and the second gate stack have an air gap therebetween; a first gate structure and a second gate structure disposed on the first gate stack and the second gate stack, respectively; a first dielectric layer surrounding lower sidewalls of the first gate structure and lower sidewalls of the second gate structure; a first landing pad disposed on an upper surface and upper sidewalls of the first gate structure; a first plug disposed on the first landing pad and electrically connected to the first gate structure, wherein a width of the first gate structure is greater than a width of the first plug; a second dielectric layer disposed on the first dielectric layer, wherein the first landing pad and the first plug are surrounded by the second dielectric layer; and a first barrier layer covering a lower surface, lower sidewalls, and upper sidewalls of the first gate structure, wherein the first barrier layer is interposed between the first landing pad and the first gate structure.

2. The semiconductor device of claim 1, further comprising: a second landing pad disposed on an upper surface and upper sidewalls of the second gate structure; and a second plug disposed on the second landing pad and electrically connected to the second gate structure, wherein a distance between the first plug and the second plug is greater than a distance between the first gate stack and the second gate stack.

3. The semiconductor device of claim 1, wherein the first landing pad directly contacts the first dielectric layer.

4. The semiconductor device of claim 1, further comprising a semiconductor material disposed between the first gate stack and the second gate stack, wherein the air gap is surrounded by the semiconductor material.

5. The semiconductor device of claim 1, wherein the first landing pad comprises germanium copper.

6. The semiconductor device of claim 1, wherein the first landing pad comprises: an inner portion covering the upper surface of the first gate structure; and a plurality of outer portions covering upper surfaces and upper sidewalls of the first barrier layer, wherein the inner portion and the outer portions comprise different materials.

7. The semiconductor device of claim 6, wherein upper surfaces of the outer portions of the first landing pad are higher than an upper surface of the inner portion of the first landing pad.

8. The semiconductor device of claim 6, wherein the inner portion of the first landing pad comprises tungsten silicide, and the outer portions of the first landing pad comprise titanium silicide.

9. A method of fabricating a semiconductor device, comprising: forming a first gate stack and a second gate stack on a semiconductor substrate, wherein one of the first gate stack and the second gate stack comprises a plurality of gate layers, and wherein the first gate stack and the second gate stack have an air gap therebetween; forming a first gate structure and a second gate structure on the first gate stack and the second gate stack, respectively; ​ ​ forming a first dielectric layer to surround the first gate structure and the second gate structure, wherein an upper surface and respective sidewalls of the first gate structure and an upper surface and respective sidewalls of the second gate structure protrude from the first dielectric layer; performing a thermal treatment process to form a first landing pad on the upper surface and the sidewalls of the first gate structure and to form a second landing pad on the upper surface and the sidewalls of the second gate structure; forming a second dielectric layer to cover the first landing pad and the second landing pad; forming a first plug in the second dielectric layer and on the first landing pad, wherein a width of the first gate structure is greater than a width of the first plug; forming a sacrificial dielectric layer having a first opening and a second opening on the second gate stack and the second gate stack; forming a first barrier layer and a second barrier layer to line the first opening and the second opening, respectively; forming the first gate structure and the second gate structure on the first barrier layer and the second barrier layer, respectively; and after forming the first gate structure and the second gate structure, removing the sacrificial dielectric layer.

10. The method of claim 9, further comprising forming a second plug in the second dielectric layer and on the second landing pad, wherein a distance between the first plug and the second plug is greater than a distance between the first gate stack and the second gate stack.

11. The method of claim 9, wherein a silicon-containing gas is used during the thermal treatment process.

12. The method of claim 9, wherein the first landing pad comprises: a first inner portion covering the upper surface of the first gate structure; and a plurality of outer portions covering the upper surface and the sidewalls of the first barrier layer, wherein an upper surface of each of the outer portions is higher than an upper surface of the inner portion, wherein the inner portion and the outer portions are formed simultaneously by the thermal treatment process. ​

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