Semiconductor interconnect structure with vertically offset bonding surface and associated systems and methods

Abstract

Disclosed herein are semiconductor interconnect structures having vertically offset bonding surfaces and associated systems and methods. In one embodiment, a semiconductor device includes: a semiconductor substrate at least partially covered by a first dielectric material having an upper surface; and an interconnect structure extending from the semiconductor substrate. The interconnect structure may include: a plurality of conductive elements; and a continuous region of a first insulating material at least partially between the plurality of conductive elements. The plurality of conductive elements and the continuous region may have coplanar end surfaces. The interconnect structure may further include a peripheral structure at least partially surrounding the plurality of conductive elements and the continuous region. The peripheral structure may have an uppermost surface that may be vertically offset from the upper surface of the first dielectric material and / or the coplanar end surface.

Description

Technical Field

[0001] The present technology relates generally to semiconductor devices, and more particularly to semiconductor devices having interconnect structures with vertically offset bonding surfaces configured to have improved bonding characteristics. Background Art

[0002] Packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted on a substrate and encased in a protective covering. The semiconductor die may include functional features such as memory cells, processor circuitry, and imager devices, as well as bond pads electrically connected to the functional features. The bond pads may be electrically connected to terminals on the outside of the protective covering to allow the semiconductor die to be connected to higher-level circuitry.

[0003] One method used to bond individual semiconductor devices to form a semiconductor package is hybrid bonding. During a typical hybrid bonding process, oxide-oxide bonds are formed between corresponding oxide bonding regions. The high temperature and strength of the oxide-oxide bonds can cause compression, which promotes the formation of metal-metal bonds between corresponding metal bonding regions. However, it can be difficult to align the oxide and metal bonding regions of the first device with the corresponding oxide and metal bonding regions of the second device. Often, these corresponding bonding regions may be misaligned, which can render the semiconductor package inoperable. Summary of the Invention

[0004] In one aspect, the present disclosure provides a semiconductor device comprising: a semiconductor substrate; a dielectric layer formed on the substrate, the dielectric layer having an upper surface; and an interconnect structure disposed in the dielectric layer, the interconnect structure comprising: a plurality of conductive elements electrically coupled to a circuit system in the semiconductor substrate, the plurality of conductive elements having coplanar end surfaces, a continuous region of a first insulating material at least partially between the plurality of conductive elements, the region having an uppermost surface coplanar with the end surfaces, and a peripheral structure of a second insulating material surrounding the plurality of conductive elements and the region of the first insulating material, the uppermost surface of the peripheral structure being vertically offset from the coplanar end surfaces or the upper surface of the dielectric layer.

[0005] On the other hand, the present disclosure further provides a semiconductor device assembly, comprising: a first semiconductor device, comprising a first semiconductor substrate and a first dielectric layer formed on the first semiconductor substrate; a second semiconductor device, comprising a second semiconductor substrate and a second dielectric layer formed on the second semiconductor substrate; and an interconnect structure, coupling the first semiconductor device to the second semiconductor device, the interconnect structure comprising: a first plurality of conductive elements of the first semiconductor device, each of which is directly bonded to a corresponding one of a second plurality of conductive elements of the second semiconductor device in a first bonding plane, and a first peripheral structure of the first semiconductor device, the first peripheral structure surrounding the first plurality of conductive elements and directly bonded to a second peripheral structure of the second semiconductor device in a second bonding plane, the second peripheral structure surrounding the second plurality of conductive elements, wherein the first bonding plane is vertically offset from the second bonding plane.

[0006] On the other hand, the present disclosure further provides a method for manufacturing a semiconductor device assembly, comprising: aligning a first interconnect structure on an upper surface of a first semiconductor device with a second interconnect structure on a lower surface of a second semiconductor device, the second interconnect structure being configured to receive the first interconnect structure; and bonding the first semiconductor device to the second semiconductor device by forming metal-metal bonds between a corresponding plurality of first conductive elements in the first interconnect structure and a plurality of second conductive elements in the second interconnect structure in a first plane, and forming first oxide-oxide bonds between a first surface of a first peripheral structure in the first interconnect structure and a corresponding second surface of a second peripheral structure of the second interconnect structure in a second plane, wherein the second plane is vertically offset from the first plane. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Many aspects of the present technology may be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale. Instead, emphasis is placed upon clearly illustrating the principles of the present technology.

[0008] Figures 1A to 1B Side cross-sectional views of two semiconductor devices at various stages of the hybrid bonding process.

[0009] Figure 2 Isometric view of a semiconductor device having vertically offset bonding surfaces configured in accordance with embodiments of the present technology.

[0010] Figure 3 A side cross-sectional view of a semiconductor device configured in accordance with an embodiment of the present technology.

[0011] Figures 4A to 4GA side cross-sectional view of a semiconductor device configured in accordance with an embodiment of the present technology.

[0012] Figure 5 A side cross-sectional view of a semiconductor device configured in accordance with an embodiment of the present technology.

[0013] Figures 6A to 6J Side cross-sectional views of first and second semiconductor devices with corresponding interconnect structures configured in accordance with embodiments of the present technology.

[0014] Figure 7 A block diagram illustrating a method of bonding a first semiconductor device to a second semiconductor device according to an embodiment of the present technology.

[0015] Figure 8 Schematic diagram of a system including a semiconductor device or package configured according to an embodiment of the present technology.

[0016] Figure 9 FIG. 1 is a block diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present technology. DETAILED DESCRIPTION

[0017] As described above, conventional hybrid bonding operations can be difficult to align and may fail when there is insufficient surface area to form mechanically robust oxide-oxide bonds. Embodiments of the present technology address these shortcomings by providing a semiconductor device having a three-dimensional hybrid bonding interconnect structure that includes additional surface area for oxide bonding and facilitates mechanical alignment. For example, a semiconductor device may include a semiconductor substrate and a dielectric layer formed above the substrate. The dielectric layer may have an upper surface positioned distal from the semiconductor substrate. The semiconductor device may further include an interconnect structure at least partially disposed within the dielectric layer. The interconnect structure may include a plurality of conductive elements electrically coupled to circuitry in the semiconductor substrate, and each of the plurality of conductive elements may have an end face coplanar with the other end faces. The interconnect structure may further include a continuous region of a first insulating material at least partially between the plurality of conductive elements. The continuous region may have an uppermost surface that may be coplanar with the coplanar end faces of the plurality of conductive elements. The interconnect structure may further include a peripheral structure of a second insulating material surrounding the plurality of conductive elements and the region of the first insulating material. The peripheral structure may have an uppermost surface that may be vertically offset from a coplanar end surface (e.g., a coplanar end surface and a continuous region of a plurality of conductive elements) or an upper surface of a dielectric layer. In some embodiments, the peripheral structure may further include a side surface positioned between the uppermost surface and the dielectric layer. The side surface may be perpendicular to the uppermost surface and / or the dielectric layer. The interconnect structure of the present technology is expected to provide more consistent bonding component alignment and / or higher bonding strength. The vertically offset surface can provide mechanical coupling (e.g., convex-concave, plug-and-socket, etc.), which can both increase bond strength and provide alignment for bonding components (e.g., peripheral structures, multiple conductive elements, dielectric layers, etc.). A semiconductor device configured according to the present technology may also have an increased surface area available for bonding (e.g., a vertically offset uppermost surface of the peripheral structure), which can further increase bond strength due to having more material available for bonding.

[0018] Those skilled in the art will recognize that appropriate stages of the methods described herein can be performed at the wafer level or at the die level. Thus, depending on the context in which it is used, the term "substrate" can refer to a wafer-level substrate or a singulated die-level substrate. Furthermore, unless the context indicates otherwise, the structures disclosed herein can be formed using semiconductor fabrication techniques, the details of which are familiar to those skilled in the art. For example, materials can be deposited using chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques.

[0019] Numerous specific details are disclosed herein to provide a thorough and useful description of embodiments of the present technology. However, one skilled in the art will appreciate that the technology may have additional embodiments and that the technology may be used without the following references. Figures 2 to 8 The present invention is practiced without the need for certain details of the described embodiments. For example, some details of semiconductor devices and / or packaging well known in the art have been omitted to avoid obscuring the present invention. In general, it should be understood that various other devices and systems besides the specific embodiments disclosed herein may be within the scope of the present invention.

[0020] As used herein, the terms "vertical," "horizontal," "upper," "lower," "above," and "below" may refer to the relative direction or position of features in a semiconductor device in view of the orientation shown in the figures. For example, "upper" or "topmost" may refer to a feature that is positioned closer to the top of the page than another feature. However, these terms should be broadly understood to include semiconductor devices having other orientations, such as inverted or tilted orientations, where top / bottom, over / under, above / below, up / down, and left / right may be interchanged depending on the orientation.

[0021] Figures 1A to 1B are side cross-sectional views of a semiconductor assembly 100 ("assembly 100") at various stages of a hybrid bonding process. Figure 1A , assembly 100 includes a first semiconductor device 110 having a plurality of first metal bonding areas 112 and a plurality of first oxide bonding areas 114. Assembly 100 further includes a second semiconductor device 120 having a plurality of second metal bonding areas 122 and a plurality of second oxide bonding areas 124. The plurality of first metal bonding areas 112 may correspond to and be vertically aligned with the plurality of second metal bonding areas 122. Similarly, the plurality of first oxide bonding areas 114 may correspond to and be vertically aligned with the plurality of second oxide bonding areas 124.

[0022] refer to Figure 1B, the first semiconductor device 110 and the second semiconductor device 120 can be coupled using hybrid bonds 130. Hybrid bonds 130 can be formed using any suitable technique, including techniques known to those skilled in the art. Hybrid bonds 130 can couple the plurality of first metal bonding regions 112 to the plurality of second metal bonding regions 122 using metal-metal bonds. Hybrid bonds 130 can also couple the plurality of first oxide bonding regions 114 to the plurality of second oxide bonding regions 124 using oxide-oxide bonds. In the illustrated embodiment, the metal-metal bonds and the oxide-oxide bonds are coplanar. Hybrid bonds 130, metal-metal bonds, and / or oxide-oxide bonds can be formed using any suitable technique, including techniques known to those skilled in the art.

[0023] Figure 2 An isometric view of a semiconductor device 200 ("device 200") having vertically offset bonding surfaces configured in accordance with an embodiment of the present technology. Device 200 may include a semiconductor substrate 204 at least partially covered by a first insulating material layer 210 having an upper surface 212. In the illustrated embodiment, device 200 further includes an interconnect structure 214 that may be coupled to semiconductor substrate 204 and at least partially disposed in first insulating material layer 210. Interconnect structure 214 may include a plurality of conductive elements 218 electrically coupled to semiconductor substrate 204. Each of the plurality of conductive elements 218 may have an end face 220 that may be coplanar with other end faces 220. Interconnect structure 214 may further include a continuous region of a second insulating material 222 at least partially between the plurality of conductive elements 218. The continuous region of second insulating material 222 may have an uppermost surface 224 that is coplanar with the end faces 220 of the plurality of conductive elements 218. The interconnect structure 214 may further include a perimeter structure 226 that surrounds the plurality of conductive elements 218 and the continuous region of the second insulating material 222. The perimeter structure 226 may have an uppermost surface 228 that may be vertically offset from the coplanar end surfaces 220 of the plurality of conductive elements 218 and the uppermost surface 224 of the continuous region of the second insulating material 222, or the upper surface 212 of the first insulating material layer 210.

[0024] Despite Figure 2 2. The peripheral structure 226 is described as having an octagonal shape in the embodiment, but in other embodiments, the peripheral structure 226 may be circular, triangular, square, rectangular, pentagonal, hexagonal, or any other suitable shape. Figure 2 As illustrated in FIG. 2 as having an elongated shape, in other embodiments, the continuous region of the second insulating material 222 may be circular, triangular, square, rectangular, pentagonal, hexagonal, or any other suitable shape. Figure 2In the embodiment, the plurality of conductive elements 218 are illustrated as a mixture of the two shapes. However, in other embodiments, each of the plurality of conductive elements 218 may be circular, triangular, square, rectangular, pentagonal, hexagonal, or any other suitable shape. Figure 2 226, in other embodiments, the plurality of conductive elements 218 may be evenly distributed within the perimeter structure 226, clustered near an inner portion of the perimeter structure 226, clustered near an outer portion of the perimeter structure 226, arranged to form a pattern (e.g., linear, circular, triangular, square, etc.) within the perimeter structure 226, arranged to form a shape having linear and / or radial symmetry with respect to the perimeter structure 226, or any other suitable distribution within the perimeter structure 226. Figure 2 2 as having sixteen conductive elements 218, but in other embodiments, the device 200 may include more or fewer conductive elements 218. For example, the device 200 may include at least one, two, three, four, five, six, seven, eight, nine, ten, twenty, fifty, or one hundred conductive elements 218.

[0025] and Figures 1A to 1B Compared with the devices 110 and 120, Figure 2 The semiconductor device 200 may have increased bonding strength. For example, the vertical offset of the uppermost surface 228 of the peripheral structure 226 may provide additional surface area available for forming oxide-oxide and / or metal-metal bonds. The increased bonding surface area may increase the overall bond strength. Additionally, the vertical offset may help align at least one of the plurality of conductive elements 218, the continuous region of the second insulating material 222, the peripheral structure 226, or the first insulating material layer 210 of the device 200 with a corresponding component on another device during the bonding process (optimally at Figures 6A to 6J (as seen in ).

[0026] Figure 3 A side cross-sectional view of a semiconductor device 300 ("device 300") configured in accordance with an embodiment of the present technology. Device 300 may include a semiconductor die 302 including a semiconductor substrate 304 (e.g., a silicon substrate, a gallium arsenide substrate, an organic laminate substrate, etc.) having a first side or surface 306.

[0027] The first side 306 of the semiconductor substrate 304 may be an active side or region including one or more circuit elements 308 (e.g., conductive lines, traces, interconnects, transistors, etc.) (as schematically shown) formed in and / or on the first side 306. The circuit elements 308 may include, for example, memory circuits (e.g., dynamic random access memory (DRAM) or other types of memory circuits), controller circuits (e.g., DRAM controller circuits), logic circuits, and / or other circuits. In other embodiments, the semiconductor substrate 304 may be a "blank" substrate that does not include integrated circuit components and is formed from, for example, crystalline, semi-crystalline, and / or ceramic substrate materials such as silicon, polysilicon, aluminum oxide (Al2O3), sapphire, and / or other suitable materials.

[0028] Semiconductor die 302 may further include an insulating material layer 310 formed over at least a portion of first side 306 of semiconductor substrate 304. Insulating material layer 310 may be a first insulating material 311 and may include one or more layers of suitable dielectric materials (e.g., passivation materials, polyimide materials, and / or other materials used to cover the surface of semiconductor devices). For example, first insulating material 311 may include silicon oxide, silicon nitride, polycrystalline silicon nitride, polycrystalline silicon oxide, tetraethyl orthosilicate (TEOS), and the like. In some embodiments, first insulating material 311 may at least partially comprise a dielectric material having a lower dielectric constant than silicon oxide (a "low-κ dielectric material"). Such low-κ dielectric materials may include fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, organic polymer dielectrics, silicon-based polymer dielectrics, and the like. First insulating material 311 may be a first oxide material selected based on bonding properties known to those skilled in the art (e.g., oxide-oxide bonding, nitride-nitride bonding, and the like).

[0029] The insulating material layer 310 may include an upper surface 312. In the illustrated embodiment, the upper surface 312 may be vertically offset from (e.g., above, on, at least partially covering, etc.) the first side 306 of the semiconductor substrate 304. The upper surface 312 may be generally planar and / or parallel to the first side 306 of the semiconductor substrate 304.

[0030] The device 300 may further include an interconnect structure 314 disposed at least partially within the insulating material layer 310. The interconnect structure 314 may have a first end portion 316 a that is mechanically and / or electrically coupled to the first side 306 of the semiconductor substrate 304, and a second end portion 316 b that is opposite the first end portion 316 a. In some embodiments, the device 300 may include a plurality of interconnect structures, and at least some of the interconnect structures 314 may be “dummy” structures that are not electrically coupled to the semiconductor substrate 304.

[0031] The interconnect structure 314 may include a plurality of conductive elements 318 that may be mechanically and / or electrically coupled to the first side 306 of the semiconductor substrate 304. For example, at least some of the plurality of conductive elements 318 may be electrically coupled to the circuit element 308. The interconnect structure 314 may include at least one, two, three, four, five, six, seven, eight, nine, ten, fifteen, twenty, fifty, or more conductive elements 318. Each conductive element 318 may have a generally elongated shape extending from a first end portion 316a of the interconnect structure 314 to a second end portion 316b of the interconnect structure 314. For example, the conductive elements 318 may be configured as pillars, rods, bars, fibers, filaments, etc. At least some of the conductive elements 318 may be wider at the first end portion 316a of the interconnect structure 314 than at the second end portion 316b of the interconnect structure. Optionally, at least some of the conductive elements 318 may be narrower at the first end portion 316a of the interconnect structure 314 than at the second end portion 316b of the interconnect structure 314. In some embodiments, some or all of the conductive elements 318 may have a linear, polygonal, curved, arcuate, Z-shaped, serpentine, or any other suitable shape. The conductive elements 318 may be made of a conductive material 319, such as copper, nickel, gold, silicon, tungsten, a conductive epoxy, combinations thereof, or the like. Each of the plurality of conductive elements 318 may have an end face 320, and at least one of the end faces 320 may be coplanar with another of the end faces 320. In some embodiments, all of the end faces 320 of the plurality of conductive elements 318 may be coplanar.

[0032] In the illustrated embodiment, the interconnect structure 314 further includes a continuous region 322 of a second insulating material 323. The continuous region 322 may extend from a first end portion 316a of the interconnect structure 314 to a second end portion 316b of the interconnect structure 314. The continuous region 322 may be at least partially between the plurality of conductive elements 318. For example, the continuous region 322 may fill the lateral spaces between the conductive elements 318, such that the interconnect structure 314 has a solid cross-section with little or no internal voids or gaps. The continuous region 322 may further include an uppermost surface 324 that may be coplanar with at least one of the end faces 320 of the plurality of conductive elements 318. In some embodiments, the uppermost surface 324 of the continuous region 322 may be coplanar with all of the end faces 320 of the plurality of conductive elements 318, such that the end faces 320 and the uppermost surface 324 may form a plane that is parallel to and / or vertically offset from the upper surface 312 of the first insulating material layer 310.

[0033] The second insulating material 323 (e.g., forming the continuous region 322) can be the same or different material as the first insulating material 311 and can be formed from any of the materials previously discussed with respect to the first insulating material 311. For example, the second insulating material 323 can include silicon oxide, silicon nitride, polysilicon nitride, polysilicon oxide, TEOS, etc. In some embodiments, the second insulating material 323 can be selected based on desired bonding properties (e.g., oxide-oxide bonding, nitride-nitride bonding, etc.) known to those skilled in the art.

[0034] In the illustrated embodiment, the interconnect structure 314 further includes a perimeter structure 326 that at least partially surrounds the plurality of conductive elements 318 and the continuous region 322 of the second insulating material 323. The perimeter structure 326 can be formed on the upper surface 312 of the insulating material layer 310, such that the perimeter structure 326 can at least partially cover the upper surface 312 of the insulating material layer 310. The perimeter structure 326 can further include an uppermost surface 328 that can be vertically offset from the upper surface 312 of the insulating material layer 310. In some embodiments, the uppermost surface 328 of the perimeter structure 326 can be vertically offset from a plane that includes the coplanar end surfaces 320 of the plurality of conductive elements 318 and the uppermost surface 324 of the continuous region 322 of the second insulating material 323.

[0035] Peripheral structure 326 may further include a side surface 330 positioned between an uppermost surface 328 of peripheral structure 326 and upper surface 312 of insulating material layer 310. In some embodiments, side surface 330 may define a perimeter of peripheral structure 326. Side surface 330 may be at a first angle relative to uppermost surface 328 and at a second angle relative to upper surface 312. For example, in the illustrated embodiment, the first and second angles are right angles, such that side surface 330 is perpendicular to uppermost surface 328 and upper surface 312. However, in other embodiments, the first and second angles may be any suitable angles such that side surface 330 forms a tapered shape of peripheral structure 326 extending from upper surface 312 toward uppermost surface 328. Peripheral structure 326 including tapered side surface 330 may advantageously facilitate mechanical self-alignment of interconnect structure 314.

[0036] Peripheral structure 326 may be formed from a third insulating material 332. Third insulating material 332 may be any of the materials previously discussed with respect to first insulating material 311. For example, third insulating material 332 may include silicon oxide, silicon nitride, polysilicon nitride, polysilicon oxide, TEOS, or the like. In some embodiments, third insulating material 332 may be selected based on desired bonding properties known to those skilled in the art (e.g., oxide-oxide bonding, nitride-nitride bonding, etc.). Third insulating material 332 may be the same or different material from first insulating material 311 and / or second insulating material 323. For example, third insulating material 332 may be different from both first insulating material 311 and second insulating material 323.

[0037] The semiconductor device 300 configured according to embodiments of the present technology can exhibit advantageous bonding behavior. Figures 1A to 1B The bond of the device 300 involving the uppermost surface 328 (e.g., bonded to the corresponding surface of the second perimeter structure) and the side surface 330 (e.g., bonded to the corresponding side surface of the second perimeter structure) of the perimeter structure 326 may have an increased surface area compared to the bond of the devices 110, 120 of FIG. 1 . In some embodiments, the end surface 320 of the plurality of conductive elements 318 and at least one of the following may be used to directly bond the semiconductor device 300 to another device, package, assembly, or any other suitable substrate (preferably in FIG. 1 ). Figures 6A to 6J 3 ): (i) upper surface 312 of first insulating material layer 310, (ii) uppermost surface 324 of continuous region 322, (iii) uppermost surface 328 of peripheral structure 326, and (iv) side surface 330 of peripheral structure 326. Any combination of bonding surfaces (i) to (iv) listed above can advantageously increase the surface area available for bonding.

[0038] Additionally, the bonding surfaces (i) to (iv) listed above may comprise different materials (e.g., as previously discussed). Using multiple materials to form a bond may also advantageously increase bond strength. Furthermore, interconnect structure 314 may correspond to another interconnect structure (preferably Figures 6A to 6J ). Using corresponding interconnect structures can provide additional mechanical coupling aspects (e.g., plug-and-socket, male-and-female, etc.) to the key, which can advantageously increase the bond strength and reduce the difficulty of aligning the corresponding components during the bonding (e.g., hybrid bonding) process.

[0039] Device 300 may include other components commonly found in semiconductor devices and known to those skilled in the art. For example, device 300 may further include an underfill or molding material (not shown) formed over and / or at least partially around semiconductor die 302. In some embodiments, device 300 includes other components such as an external heat sink, a sleeve (e.g., a thermal sleeve), and electromagnetic interference (EMI) shielding components.

[0040] Figures 4A to 4G Side cross-sectional view of a semiconductor device 400 ("device 400") configured in accordance with an embodiment of the present technology. Figures 4A to 4G The components of the apparatus 400 may be substantially similar to Figure 3 Thus, like numerical values ​​(e.g., interconnect structures 414a through g relative to interconnect structure 314) are used to identify similar or identical components, and Figures 4A to 4G The discussion of the devices 400a to g will be limited to devices other than Figure 3 Those features of the device 300. In addition, Figures 4A to 4G Any features of devices 400a to g may be used with each other and / or with Figure 3 The device 300 is combined.

[0041] Figure 4A The description is similar to Figure 3 The semiconductor device 400a of the device 300 is shown in FIG. Figure 4A The semiconductor device 400a may further include an interconnect structure 414a, wherein the continuous region 422a is at least partially between the plurality of conductive elements 418a and the peripheral structure 426a.

[0042] Figure 4B A semiconductor device 400b is illustrated having an interconnect structure 414b including a peripheral structure 426b, wherein the peripheral structure 426b includes an intermediate surface 434b. The intermediate surface 434b may be parallel to the uppermost surface 428b of the peripheral structure 426b and may be vertically offset from the uppermost surface 428b and / or the upper surface 412b of the first insulating material layer 410b.

[0043] The peripheral structure 426b may further include a second side surface 436b positioned between the intermediate surface 434b and the uppermost surface 428b. The second side surface 436b may be at a first angle relative to the intermediate surface 434b and at a second angle relative to the uppermost surface 428b. For example, the second side surface 436b may be perpendicular to the intermediate surface 434b and the uppermost surface 428b. The second side surface 436b may be horizontally offset (e.g., laterally in an inward or outward direction) from the first side surface 430b. For example, as shown by Figure 4BAs best illustrated, the second side surface 436b can be offset inwardly relative to the first side surface 430b. In other embodiments, the second side surface 436b can be offset outwardly relative to the first side surface 430b.

[0044] The peripheral structure 426b may further include a third side surface 438b positioned between the uppermost surface 428b of the peripheral structure 426b and the coplanar end surfaces 420b of the plurality of conductive elements 418b and the uppermost surface 424b of the continuous region 422b. The third side surface 438b may be at a first angle relative to the uppermost surface 428b and at a second angle relative to the coplanar end surfaces 420b of the plurality of conductive elements 418b and the uppermost surface 424b of the continuous region 422b. For example, the second side surface 436b may be perpendicular to both the uppermost surface 428b of the peripheral structure 426c and the coplanar end surfaces 420b of the plurality of conductive elements 418b and / or the uppermost surface 424b of the continuous region 422b. The third side surface 438b may be parallel to the first side surface 430b and / or the second side surface 436b and / or offset horizontally (e.g., laterally in an inward or outward direction) from the first side surface and / or the second side surface. For example, if Figure 4B As best illustrated, the third side surface 438b can be offset inwardly relative to the first side surface 430b and the second side surface 436b.

[0045] Figure 4C The description is roughly similar to Figure 4B The semiconductor device 400b is the semiconductor device 400c. However, Figure 4C The semiconductor device 400c may further include a first insulating material layer 410c at least partially covering the first side surface 430c. For example, the uppermost surface 412c of the first insulating material layer 410c may be coplanar with the middle surface 434c of the peripheral structure 426c.

[0046] Figure 4D A semiconductor device 400d is illustrated in which end surfaces 420d of a plurality of conductive elements 418d and an uppermost surface 424d of a continuous region 422d are coplanar with an uppermost surface 412d of a first insulating material layer 410d. In the illustrated embodiment, an uppermost surface 428d of a peripheral structure 426d may be vertically offset from both the uppermost surface 412d of the first insulating material layer 410d and the uppermost surface 424d of the end surfaces 420d of the plurality of conductive elements 418d and the continuous region 422d.

[0047] Figure 4EThe semiconductor device 400e is illustrated, wherein the end surfaces 420e of the plurality of conductive elements 418e, the uppermost surface 424e of the continuous region 422e, and the uppermost surface 428e of the peripheral structure 426e are coplanar with the upper surface 412e of the first insulating material layer 410e.

[0048] Figure 4F The description is roughly similar to Figure 4E The semiconductor device 400e is the semiconductor device 400f. However, Figure 4F The device 400f may further include an interconnect structure 414f, wherein a continuous region 422f is at least partially between the plurality of conductive elements 418f and the peripheral structure 426f.

[0049] Figure 4G The description is roughly similar to Figure 3 The semiconductor device 300 is a semiconductor device 400g. However, Figure 4G The semiconductor device 400g may further include a plurality of conductive elements 418g, wherein at least some of the plurality of conductive elements 418g are electrically coupled to form a single electrical connector 440g.

[0050] Figure 5 A semiconductor device 500 having a plurality of interconnect structures 514a-c configured in accordance with an embodiment of the present technology is illustrated. The semiconductor device 500, the interconnect structures 514a-c, and any components thereof may be substantially similar to Figure 3 The device 300 and the interconnect structure 314 and / or Figures 4A to 4G Thus, like numerical values ​​(e.g., device 500 relative to device 300 and devices 400a to g) are used to identify similar or identical components, and discussion of device 500 will be limited to those that differ from the Figure 3 The device 300 and / or Figures 4A to 4G Those features of the device 400a to g. In addition, Figure 5 Any of the features of the apparatus 500 may be used with Figure 3 The device 300 and / or Figures 4A to 4G The device 400a to g combination.

[0051] refer to Figure 5 , the interconnect structures 514a-c (collectively referred to as "interconnect structures 514") may be spaced apart, and the first insulating material layer 510 may be at least partially between the interconnect structures 514. Figure 5 Each of the interconnect structures 514a-c is illustrated as having the same configuration (e.g., similar to Figure 3 300), but in other embodiments, some or all of the interconnect structures 514 may have different configurations. For example, the device 500 may include Figures 4A to 4G In addition, the device 500 may include one or more of the interconnect structures 414a to g disclosed in Figure 5 For example, device 500 may include at least two, four, five, six, seven, eight, nine, ten, fifteen, twenty, fifty, or more interconnect structures 514.

[0052] Figures 6A to 6J A side cross-sectional view of first and second semiconductor devices 600a-j and 650a-j, and corresponding first and second interconnect structures 614a-j and 664a-j, configured in accordance with embodiments of the present technology. The first device 600a-j can be positioned above the second device 650a-j so that the first and second interconnect structures 614a-j are vertically aligned. The second device 650a-j and the second interconnect structure 664a-j can be configured to correspond to the first device 600a-j and the first interconnect structure 614a-j, such that the second interconnect structure 664a-j can receive the first interconnect structure 614a-j to couple the second device 650a-j to the first device 600a-j. Thus, the first device 600a-j and / or the first interconnect structure 614a-j can be directly bonded to the second device 650a-j and / or the second interconnect structure 664a-j.

[0053] Figures 6A to 6J The components of the devices 600a-j, 650a-j in FIG. 1 may be substantially similar to Figure 3 Components of the device 300. Additionally, each of the devices 600a-j, 650a-j may be configured so as to be substantially similar to Figure 4A Thus, similar values ​​(e.g., Figures 6A to 6J The first peripheral structures 626a to j and the second peripheral structures 676a to j are relative to Figure 3 The surrounding structure 326 and Figures 4A to 4G The peripheral structures 426a to g) are used to identify similar or identical components. Figures 6A to 6J The discussion of the devices 600a to j, 650a to j will be limited to devices different from Figure 3 The device 300 and / or Figures 4A to 4G Those features of the device 400a to g. In addition, Figures 6A to 6J Any features of devices 600a to j, 650a to j may be mutually Figure 5 The device 500, and Figures 4A to 4G The apparatus 400a to g and / or with Figure 3 The device 300 is combined.

[0054] Figure 6AThe description is roughly similar to Figure 3 300, and a second device 650a that may correspond to the first device 600a. For example, the second device 650a may include a second peripheral structure 676a formed at least partially above the second plurality of conductive elements 668a. The second peripheral structure 676a may include an uppermost surface 678a, an intermediate surface 684a parallel to and / or vertically offset from the uppermost surface 678a, and a second side surface 686a between the uppermost surface 678a and the intermediate surface 684a. In the illustrated embodiment, the intermediate surface 684a is coplanar with the second end surface 670a of the second plurality of conductive elements 668a and the uppermost surface 674a of the second continuous region 672a.

[0055] The first device 600a can be directly bonded to the second device 650a. During bonding, at least one of the following combinations of components can be vertically aligned and / or at least partially coupled: (i) each of the first plurality of conductive elements 618a with a corresponding one of the second plurality of conductive elements 668a; (ii) the first continuous region 622a with the second continuous region 672a; (iii) the lowermost surface 628a of the first peripheral structure 626a with the intermediate surface 684a of the second peripheral structure 676a; (iv) the first side surface 630a of the first peripheral structure 626a with the second side surface 686a of the second peripheral structure 676a; (v) at least a first portion of the lower surface 612a of the first insulating material layer 610a with the uppermost surface 678a of the second peripheral structure 676a; and (vi) at least a second portion of the lower surface 612a of the first insulating material layer 610a with the uppermost surface 662a of the second insulating material layer 660a.

[0056] The bonding described above may occur in different planes. For example, the first plurality of conductive elements 618a may be directly bonded to the second plurality of conductive elements 668a in a first plane, and at least a first portion of the lower surface 612a of the first insulating material layer 610a may be directly bonded to the uppermost surface 678a of the second peripheral structure 676a in a second plane, and the first plane may be vertically offset from the second plane.

[0057] Figure 6B Description similar to Figure 4A A first semiconductor device 600b may be configured in the manner of the semiconductor device 400a, and a second device 650b may be configured to correspond to the first device 600b. For example, the second device 650b may include an interconnect structure 664b having a second continuous region 672b that may be at least partially between the second plurality of conductive elements 668b and the second peripheral structure 676b.

[0058] The first device 600b can be bonded directly to the second device 650b as previously discussed. Figure 6A The list of elements discussed that may be vertically aligned and / or at least partially coupled may also apply to Figure 6B Additionally, portions of the first contiguous region 622b at least partially between the first plurality of conductive elements 618b and the first peripheral structure 626b may be vertically aligned with and / or coupled to corresponding portions of the second contiguous region 672b at least partially between the second plurality of conductive elements 668b and the second peripheral structure 676b.

[0059] Figure 6C Description similar to Figure 4B A first semiconductor device 600c is configured in the manner of device 400b, and a second device 650c may be configured to correspond to the first device 600c. For example, the second device 650c may include a second peripheral structure 676c having an uppermost surface 678c. The uppermost surface 678c may be coplanar with the second end surface 670c of the second plurality of conductive elements 668c and the uppermost surface 674c of the second contiguous region 672c. In the illustrated embodiment, the second peripheral structure 676c may further include a second intermediate surface 684c, which may be parallel to and / or vertically offset from the uppermost surface 678c. The second peripheral structure 676c may further include a second side surface 686c between the uppermost surface 678c and the second intermediate surface 684c. The second side surface 686c may be parallel to a side 669c of the second plurality of conductive elements 668c. The side 669c may be at least partially exposed such that it may correspond to the third side surface 638c of the first peripheral structure 626c. In some embodiments, side 669c can be configured as a plug and third side surface 638c can be configured as a corresponding receptacle; this configuration can advantageously improve alignment, mechanical coupling, and / or bonding of first device 600c and second device 650c.

[0060] The first device 600c can be directly bonded to the second device 650c, as previously discussed. During bonding, at least one of the following combinations of features can be vertically aligned and / or at least partially coupled: (i) each of the first plurality of conductive elements 618c with a corresponding one of the second plurality of conductive elements 668c; (ii) the first contiguous region 622c with the second contiguous region 672c; (iii) the lowermost surface 628c of the first perimeter structure 626c with the second intermediate surface 684c of the second perimeter structure 676c; (iv) the first side surface 636c of the first perimeter structure 626c with the second side surface 686c of the second perimeter structure 676c; (v) the first intermediate surface 634c of the first perimeter structure 626c with the uppermost surface 678c of the second perimeter structure 676c; and (vi) at least a portion of the side 669c of the second plurality of conductive elements 668c with at least a portion of the third side surface 638c of the first perimeter structure 626c.

[0061] The bonding described above can occur in different planes. For example, the first plurality of conductive elements 618c can be directly bonded to the second plurality of conductive elements 668c in a first plane, the lowermost surface 628c of the first peripheral structure 626c can be directly bonded to the second intermediate surface 684c of the second peripheral structure 676c in a second plane, and the first plane can be vertically offset from the second plane.

[0062] Figure 6D A first semiconductor device 600d is illustrated that includes a first interconnect structure 614d that may include a first perimeter structure 626d. The first perimeter structure 626d may include a lowermost surface 628d that may be coplanar with the end surfaces 620d of the first plurality of conductive elements 618d and the lowermost surface 624d of the first contiguous region 622d. The first perimeter structure 626d may further include a first intermediate surface 634d that may be parallel to and / or vertically offset from the lowermost surface 628d. The first perimeter structure 626d may further include a first side surface 636d between the first intermediate surface 634d and the lowermost surface 628d.

[0063] In the illustrated embodiment, the second semiconductor device 650d can be configured to correspond to the first semiconductor device 600d. For example, the second semiconductor device 650d can include a second interconnect structure 664d having a second peripheral structure 676d. The second peripheral structure 676d can include an uppermost surface 678d that can be vertically offset from the coplanar end surfaces 670d of the second plurality of conductive elements 668d and the uppermost surface 674d of the second contiguous region 672d. The second peripheral structure 676d can further include a second intermediate surface 684d that can be parallel to and / or vertically offset from the uppermost surface 678d. In the illustrated embodiment, the second intermediate surface 684d can be coplanar with the end surfaces 670d of the second plurality of conductive elements 668d and the uppermost surface 674d of the second contiguous region 672d. The second peripheral structure 676d can further include a second side surface 686d between the second intermediate surface 684d and the uppermost surface 678d.

[0064] The first device 600d can be directly bonded to the second device 650d. During bonding, at least one of the following combinations of features can be vertically aligned and / or at least partially coupled: (i) each of the first plurality of conductive elements 618d with a corresponding one of the second plurality of conductive elements 668d; (ii) the first continuous region 622d with the second continuous region 672d; (iii) the lowermost surface 628d of the first peripheral structure 626d with the second intermediate surface 684d of the second peripheral structure 676d; (iv) the first side surface 636d of the first peripheral structure 626d with the second side surface 686d of the second peripheral structure 676d; and (v) the first intermediate surface 634d of the first peripheral structure 626d with the uppermost surface 678d of the second peripheral structure 676d.

[0065] The bonding described above can occur in different planes. For example, the first plurality of conductive elements 618d can be directly bonded to the second plurality of conductive elements 668d in a first plane, and the first intermediate surface 634d of the first peripheral structure 626d can be directly bonded to the uppermost surface 678d of the second peripheral structure 676d in a second plane, and the first plane can be vertically offset from the second plane.

[0066] Figure 6E Description similar to Figure 6CThe first semiconductor device 600e and the second semiconductor device 650e are configured in the same manner as the corresponding first semiconductor device 600c and the second semiconductor device 650c. However, the first device 600e may further include a first insulating material layer 610e having a lower surface 612e that is coplanar with the first intermediate surface 634e of the first peripheral structure 626e, the end surface 620e of the first plurality of conductive elements 618e, and the lowermost surface 624e of the first continuous region 622e. The second device 650e may further include a second insulating material layer 660e having an uppermost surface 662e that may be coplanar with the uppermost surface 678e of the second peripheral structure 676e, the end surface 670e of the second plurality of conductive elements 668e, and the uppermost surface 674e of the second continuous region 672e.

[0067] The first device 600e can be directly bonded to the second device 650e. During bonding, Figure 6C The list of elements discussed that may be vertically aligned and / or at least partially coupled may also apply to Figure 6E Additionally, the lower surface 612e of the first insulating material layer 610e can be vertically aligned with and / or coupled to a corresponding uppermost surface 662e of the second insulating material layer 660e.

[0068] The bonding described above can occur in different planes. For example, the first plurality of conductive elements 618e can be directly bonded to the second plurality of conductive elements 668e in a first plane, and the lowermost surface 628e of the first peripheral structure 626e can be directly bonded to the second intermediate surface 684e of the second peripheral structure 676e in a second plane, and the first plane can be vertically offset from the second plane.

[0069] Figure 6F Description similar to Figure 6D The first semiconductor device 600f and the second semiconductor device 650f are configured in the same manner as the corresponding first semiconductor device 600d and the second semiconductor device 650d. However, the first device 600f may further include a first insulating material layer 610f having a lower surface 612f that may be coplanar with the first intermediate surface 634f of the first peripheral structure 626f. The second device 650f may further include a second insulating material layer 660f having an uppermost surface 662f that may be coplanar with the uppermost surface 678f of the second peripheral structure 676f.

[0070] The first device 600f can be directly bonded to the second device 650f. During bonding, Figure 6D The list of elements discussed that may be vertically aligned and / or at least partially coupled may also apply to Figure 6FAdditionally, the lower surface 612f of the first insulating material layer 610f can be vertically aligned with and / or coupled to a corresponding uppermost surface 662f of the second insulating material layer 660f.

[0071] The bonding described above can occur in different planes. For example, the first plurality of conductive elements 618f can be directly bonded to the second plurality of conductive elements 668f in a first plane, and the first intermediate surface 634f of the first peripheral structure 626f can be directly bonded to the uppermost surface 678f of the second peripheral structure 676f in a second plane, and the first plane can be vertically offset from the second plane.

[0072] Figure 6G The description can be similar to Figure 4D The first semiconductor device 600g is configured in a manner similar to the semiconductor device 400d, and may be similar to Figure 6C The second semiconductor device 650c is configured in a manner to correspond to the second semiconductor device 650g of the first device 600g.

[0073] The first device 600g can be directly bonded to the second device 650g. During bonding, at least one of the following combinations of features can be vertically aligned and / or at least partially coupled: (i) each of the first plurality of conductive elements 618g with a corresponding one of the second plurality of conductive elements 668g; (ii) the first contiguous region 622g with the second contiguous region 672g; (iii) the lowermost surface 628g of the first perimeter structure 626g with the second intermediate surface 684g of the second perimeter structure 676g; (iv) the first side surface 630g with the second side surface 686g; (v) at least a first portion of the lower surface 612g of the first insulating material layer 610g with the uppermost surface 678g of the second perimeter structure 676g; and (vi) at least a portion of the side 669g of the second plurality of conductive elements 668g with at least a portion of the third side surface 638g of the first perimeter structure 626g.

[0074] The bonding described above can occur in different planes. For example, the first plurality of conductive elements 618g can be directly bonded to the second plurality of conductive elements 668g in a first plane, the lowermost surface 628g of the first peripheral structure 626g can be directly bonded to the second intermediate surface 684g of the second peripheral structure 676g in a second plane, and the first plane can be vertically offset from the second plane.

[0075] Figure 6H The description can be similar to Figure 6G The first semiconductor device 600h is configured in the manner of the semiconductor device 600g, and can be similar to Figure 6EThe second semiconductor device 650e is configured in a manner to correspond to the second semiconductor device 650h of the first device 600h.

[0076] The first semiconductor device 600h can be directly bonded to the second semiconductor device 650h. Figure 6G The list of elements discussed that may be vertically aligned and / or at least partially coupled may also apply to Figure 6H Additionally, the lower surface 612h of the first insulating material layer 610h may be vertically aligned with and / or coupled to at least a portion of the uppermost surface 662h of the second insulating material layer 660h.

[0077] The bonding described above can occur in different planes. For example, the first plurality of conductive elements 618h can be directly bonded to the second plurality of conductive elements 668h in a first plane, and the lowermost surface 628h of the first peripheral structure 626h can be directly bonded to the second intermediate surface 684h of the second peripheral structure 676h in a second plane, and the first plane can be vertically offset from the second plane.

[0078] Figure 6I The description can be similar to Figure 4E A first semiconductor device 600i is configured in a manner similar to the semiconductor device 400e of FIG. 4 , and a second semiconductor device 650i is configured to correspond to the first semiconductor device 600i. For example, the second semiconductor device 650i may include a second peripheral structure 676i having an uppermost surface 678i that may be coplanar with the uppermost surface 662i of the second insulating material layer 660i, the second end surface 670i of the second plurality of conductive elements 668i, and the uppermost surface 674i of the second continuous region 672i. In the illustrated embodiment, the second peripheral structure 676i may be formed at least partially above the second plurality of conductive elements 668i. In other embodiments, the second peripheral structure 676i may be formed above at least a portion of the second insulating material layer 660i. For example, the second peripheral structure 676i and the second insulating material layer 660i of the second semiconductor device 650i may be configured to be substantially similar to the first peripheral structure 626i and the first insulating material layer 610i or the first semiconductor device 600i. Figure 6A The second peripheral structure 676a.

[0079] The first semiconductor device 600i can be directly bonded to the second semiconductor device 650i. During bonding, at least one of the following combinations of features can be vertically aligned and / or at least partially coupled: (i) each of the first plurality of conductive elements 618i with a corresponding one of the second plurality of conductive elements 668i; (ii) the first continuous region 622i with the second continuous region 672i; (iii) the lowermost surface 628i of the first peripheral structure 626i with the uppermost surface 678i of the second peripheral structure 676i; and (iv) the lower surface 612i of the first insulating material layer 610i with the uppermost surface 662i of the second insulating material layer 660i.

[0080] The bonding described above can occur in the same plane. For example, the first plurality of conductive elements 618i can be directly bonded to the second plurality of conductive elements 668i in a first plane, the first peripheral structure 626i can be directly bonded to the second peripheral structure 676i in a second plane, and the first plane can be coplanar with the second plane. Those skilled in the art will appreciate that any of the devices disclosed herein that include fully coplanar keys, bonding components, and / or bonding surfaces can be configured to correspond to each other.

[0081] Figure 6J Description similar to Figure 6I A first semiconductor device 600j configured in a manner similar to the first device 600i of FIG. Figure 6I The second semiconductor device 650j is configured in a manner corresponding to the second semiconductor device 650j of the first device 600j. However, the first semiconductor device 600j may further include a first plurality of conductive elements 618j, wherein at least some of the first plurality of conductive elements 618j are electrically coupled to form a first single electrical connector 640j. The second semiconductor device 650j may further include a second plurality of conductive elements 668j, wherein at least some of the second plurality of conductive elements 668j are electrically coupled to form a second single electrical connector 690j.

[0082] The first semiconductor device 600j can be directly bonded to the second semiconductor device 600j. Figure 6I The list of elements discussed that may be vertically aligned and / or at least partially coupled may also apply to Figure 6J Additionally, the first single electrical connector 640j of the first semiconductor device 600j may be vertically aligned with and / or at least partially coupled to a corresponding second single electrical connector 690j of the second semiconductor device 650j.

[0083] The bonding described above can occur in the same plane. For example, the first single electrical connector 640j can be directly bonded to the second single electrical connector 690j in a first plane, the first peripheral structure 626j can be directly bonded to the second peripheral structure 676j in a second plane, and the first plane can be vertically coplanar with the second plane. It will be understood by those skilled in the art that any of the devices disclosed herein that include fully coplanar keys, bonding components, and / or bonding surfaces can be configured to correspond to each other. For example, Figure 6J The first semiconductor device 600j may be directly bonded to Figure 6I The second semiconductor device 650i.

[0084] Figure 7 1 is a block diagram illustrating a method 700 for bonding a first semiconductor device to a second semiconductor device according to an embodiment of the present technology. The method 700 may be used to bond any of the semiconductor devices described herein and / or one or more components thereof (e.g., Figure 3 Interconnection structure 314, Figures 4A to 4G Interconnect structures 414a to g, Figure 6A Method 700 may be implemented using techniques with which details are well known to those skilled in the art.

[0085] At block 710 , method 700 includes positioning a first semiconductor device having a first interconnect structure below a second semiconductor device having a second interconnect structure. The second interconnect structure may face the first interconnect structure and be configured to receive the first interconnect structure.

[0086] At block 720, method 700 further includes aligning the first interconnect structure (e.g., vertically) with the second interconnect structure. Aligning the first interconnect structure with the second interconnect structure may include aligning a first component of the first interconnect structure with a corresponding second component of the second interconnect structure. For example, the first interconnect structure may include a first perimeter structure, the second interconnect structure may include a second perimeter structure corresponding to the first perimeter structure, and the first perimeter structure may be aligned (e.g., vertically) with the second interconnect structure.

[0087] At block 730, method 700 further includes bonding the first interconnect structure to the second interconnect structure. Bonding the first interconnect structure to the second interconnect structure may include bonding a first component of the first interconnect structure to a corresponding second component of the second interconnect structure. For example, the first interconnect structure may include a first plurality of conductive elements, the second interconnect structure may include a second plurality of conductive elements, and the first plurality of conductive elements may be directly bonded to the second plurality of conductive elements.

[0088] Bonding the first interconnect structure to the second interconnect structure may further include forming a first bond in a first plane and forming a second bond in a second plane vertically offset from the first plane. For example, the bond between the first plurality of conductive elements and the second plurality of conductive elements may be a metal-metal bond in the first plane. The first and second interconnect structures may further include respective and corresponding first and second peripheral structures bonded in the second plane with a first oxide-oxide bond. The second plane may be parallel to the first plane and / or vertically offset from the first plane.

[0089] Method 700 may further include bonding the first dielectric layer on the upper surface of the first semiconductor device to the second dielectric layer on the lower surface of the second semiconductor device using a second oxide-oxide bond. The second oxide-oxide bond may be in a third plane, and the third plane may be vertically offset from the first plane or the second plane.

[0090] Method 700 may further include bonding a first continuous region of the first insulating material at least partially between the first plurality of conductive elements to a second continuous region of the second insulating material at least partially between the second plurality of conductive elements using a third oxide-oxide bond. The third oxide-oxide bond may be formed in the first plane such that the third oxide-oxide bond is coplanar with the metal-metal bond.

[0091] With the above reference Figures 2 to 6J Any of the semiconductor devices and / or packages of the described features may be incorporated into any of a number of larger and / or more complex systems, representative examples of which are in Figure 8 6J . The system 800 may include a processor 802, a memory 804 (e.g., SRAM, DRAM, flash memory, and / or other memory devices), an input / output device 806, and / or other subsystems or components 808. The semiconductor devices, dies, and / or interconnects described above with reference to FIGs. 2-6J may be included in Figure 8. The resulting system 800 can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and / or other functions. Accordingly, representative examples of system 800 include, but are not limited to, computers and / or other data processors, such as desktop computers, notebook computers, network appliances, handheld devices (e.g., palmtop computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multi-processor systems, processor-based or programmable consumer electronic devices, network computers, and microcomputers. Additional representative examples of system 800 include lights, cameras, vehicles, etc. With respect to these and other examples, system 800 can be housed in a single unit or distributed over multiple interconnected units, for example, via a communications network. Components of system 800 can accordingly include local and / or remote memory storage devices and any of a wide variety of suitable computer-readable media.

[0092] Figure 9 9 is a block diagram illustrating a method 900 for manufacturing a semiconductor device according to an embodiment of the present technology. The method 900 may be used to manufacture any embodiment of a semiconductor device described herein, and / or one or more components thereof (e.g., Figure 3 device 300, Figures 4A to 4G Devices 400a to g, Figures 6A to 6J The first device 600a to j, Figure 6A Method 900 may be implemented using any suitable technique, including techniques the details of which are familiar to those skilled in the art.

[0093] At block 910, method 900 includes aligning a first interconnect structure of a first semiconductor device with a second interconnect structure of a second semiconductor device. The second interconnect structure may correspond to the first interconnect structure such that the second interconnect structure is configured to receive the first interconnect structure. For example, the second interconnect structure may be aligned with Figures 6A to 6J The second interconnect structures 664a to j are configured in a similar or identical manner, and the first interconnect structure can be configured in a similar or identical manner. Figures 6A to 6J The first interconnect structures 614a through j are configured in a similar or identical manner. In some embodiments, the first interconnect structure may be on an upper surface of the first semiconductor device, and the second interconnect structure may be on a lower surface of the second semiconductor device.

[0094] At block 920, the method 900 further includes bonding the first semiconductor device to the second semiconductor device. The bond may be between corresponding features or components of the first semiconductor device and the second semiconductor device, as previously described with respect to Figures 6A to 6JFor example, the upper surface of the first semiconductor device may be at least partially covered by a first dielectric material layer, the lower surface of the second semiconductor device may be at least partially covered by a second dielectric material layer, and the first dielectric material layer may correspond to and be directly bonded to the second dielectric material layer.

[0095] At block 930, method 900 further includes forming one or more metal-metal bonds between corresponding ones of the plurality of first conductive elements in the first interconnect structure and the plurality of second conductive elements in the second interconnect structure. The one or more metal-metal bonds may be coplanar such that they define a first plane, and the first plane may be parallel to the upper surface of the first semiconductor device and / or the lower surface of the second semiconductor device. In some embodiments, the first conductive elements and the second conductive elements may be formed of the same material, such as any of the conductive materials previously discussed, as well as any other suitable conductive materials generally known to those skilled in the art.

[0096] At block 940, method 900 further includes forming a first oxide-oxide bond between a first surface of a first perimeter structure in the first interconnect structure and a corresponding second surface of a second perimeter structure in the second interconnect structure. The first oxide-oxide bond may define a second plane, and the second plane may be vertically offset from the first plane. The first perimeter structure and the second perimeter structure may be formed of a first insulating material. The first insulating material may be any of the insulating materials previously discussed, as well as any other suitable insulating material generally known to those skilled in the art.

[0097] Method 900 may further include forming a second oxide-oxide bond between the first dielectric layer on the upper surface of the first semiconductor device and the second dielectric layer on the lower surface of the second semiconductor device. The second oxide-oxide bond may define a third plane, and the third plane may be offset from the first plane and / or the second plane. The first dielectric layer and the second dielectric layer may be formed of the same dielectric material. The dielectric material may be any of the dielectric materials previously discussed, as well as any other suitable dielectric material generally known to those skilled in the art.

[0098] Method 900 may further include forming a third oxide-oxide bond between a first continuous region of the first insulating material at least partially between the plurality of first conductive elements and a second continuous region of the second insulating material at least partially between the plurality of second conductive elements. The third oxide-oxide bond may be coplanar with the first plane. The first continuous region and the second continuous region may be formed from a second insulating material. The second insulating material may be any of the insulating materials previously discussed, as well as any other suitable insulating material generally known to those skilled in the art. The second insulating material may be the same as or different from the first insulating material.

[0099] In summary, it should be understood that specific embodiments of the present technology have been described herein for illustrative purposes, but various modifications may be made without departing from the present disclosure. Therefore, the present invention is not limited beyond the appended claims. In addition, certain aspects of the new technology described in the context of specific embodiments may also be combined or removed in other embodiments. Furthermore, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need to exhibit such advantages to fall within the scope of the technology. Therefore, the present disclosure and associated technology may encompass other embodiments not explicitly shown or described herein.

Claims

1. A semiconductor device comprising: semiconductor substrates; a dielectric layer formed on the substrate, the dielectric layer having an upper surface; as well as an interconnect structure disposed in the dielectric layer, the interconnect structure comprising: a plurality of conductive elements electrically coupled to circuitry in the semiconductor substrate, the plurality of conductive elements having coplanar end faces, a continuous region of first insulating material at least partially between said plurality of conductive elements, said region having an uppermost surface coplanar with said end surface, and A peripheral structure of a second insulating material surrounds the plurality of conductive elements and the region of the first insulating material, an uppermost surface of the peripheral structure being vertically offset from the coplanar end surface or the upper surface of the dielectric layer. 2 . The semiconductor device of claim 1 , wherein the continuous region extends at least partially between the peripheral structure and the plurality of conductive elements. 3 . The semiconductor device of claim 1 , wherein the peripheral structure further comprises an intermediate surface parallel to and vertically offset from the uppermost surface of the peripheral structure. 4 . The semiconductor device of claim 3 , wherein the intermediate surface is coplanar with the end surface of the conductive element and the continuous region. 5 . The semiconductor device according to claim 3 , wherein the peripheral structure further comprises a side surface extending from the uppermost surface to the intermediate surface. The semiconductor device of claim 3 , wherein the intermediate surface is vertically offset from the upper surface of the dielectric layer. The semiconductor device of claim 1 , wherein at least some of the plurality of conductive elements are electrically coupled. The semiconductor device according to claim 1 , wherein the dielectric layer is formed of the first insulating material. 9 . The semiconductor device according to claim 1 , wherein the second insulating material is different from the first insulating material.

10. A semiconductor device assembly comprising: A first semiconductor device comprising a first semiconductor substrate and a first dielectric layer formed on the first semiconductor substrate; a second semiconductor device comprising a second semiconductor substrate and a second dielectric layer formed on the second semiconductor substrate; as well as an interconnect structure coupling the first semiconductor device to the second semiconductor device, the interconnect structure comprising: a first plurality of conductive elements of the first semiconductor device, each directly bonded in a first bonding plane to a corresponding one of a second plurality of conductive elements of the second semiconductor device, and a first perimeter structure of the first semiconductor device, the first perimeter structure surrounding the first plurality of conductive elements and directly bonded to a second perimeter structure of the second semiconductor device in a second bonding plane, the second perimeter structure surrounding the second plurality of conductive elements, wherein the first bonding plane is vertically offset from the second bonding plane, Wherein the first dielectric layer is directly coupled to the second dielectric layer in one of the first bonding plane or the second bonding plane.

11. The semiconductor device assembly of claim 10, wherein the interconnect structure further comprises: a first continuous region of first insulating material at least partially between the first plurality of conductive elements, and A second contiguous region of a second insulating material is at least partially between the second plurality of conductive elements, wherein the first contiguous region is bonded to the second contiguous region in the first bonding plane.

12. The semiconductor device assembly according to claim 11, wherein: The first dielectric layer and the second dielectric layer include a first dielectric material, The first insulating material is the same as the second insulating material, The first peripheral structure and the second peripheral structure include a third insulating material different from the first insulating material and the second insulating material, and The first plurality of conductive elements and the second plurality of conductive elements include a same conductive material.

13. The semiconductor device assembly according to claim 10, wherein: The first peripheral structure further comprises a first intermediate surface, The second peripheral structure further comprises an uppermost surface, The first intermediate surface is directly bonded to the uppermost surface of the second peripheral structure in a third bonding plane, and The third bonding plane is parallel to and offset from the second bonding plane.

14. The semiconductor device assembly according to claim 13, wherein: The first peripheral structure further comprises a first side surface between the first intermediate surface and the second bonding plane, The second peripheral structure further includes a second side surface between the uppermost surface and the second bonding plane, and The first side surface is directly bonded to the second side surface.

15. The semiconductor device assembly according to claim 10, wherein: The first plurality of conductive elements are coupled to the second plurality of conductive elements by metal-metal bonds, and The first peripheral structure is coupled to the second peripheral structure through an oxide-oxide bond.

16. A method for manufacturing a semiconductor device assembly, comprising: aligning a first interconnect structure on an upper surface of a first semiconductor device with a second interconnect structure on a lower surface of a second semiconductor device, the second interconnect structure being configured to receive the first interconnect structure; as well as The first semiconductor device is bonded to the second semiconductor device by: forming metal-to-metal bonds between corresponding ones of the first plurality of conductive elements in the first interconnect structure and the second plurality of conductive elements in the second interconnect structure in a first plane, forming a first oxide-oxide bond between a first surface of a first perimeter structure in the first interconnect structure and a corresponding second surface of a second perimeter structure in the second interconnect structure in a second plane, wherein the second plane is vertically offset from the first plane, and Second oxide-oxide bonds are formed between the first dielectric layer on the upper surface of the first semiconductor device and the second dielectric layer on the lower surface of the second semiconductor device in a third plane, wherein the third plane is offset from the first plane and / or the second plane.

17. The method of claim 16, further comprising forming a second oxide-oxide bond in the first plane between a first continuous region of a first insulating material at least partially between the plurality of first conductive elements and a second continuous region of a second insulating material at least partially between the plurality of second conductive elements.

18. The method according to claim 17, wherein: the first conductive element and the second conductive element comprise the same material, The first peripheral structure and the second peripheral structure are formed of a first insulating material, and The first continuous region and the second continuous region are formed of a second insulating material different from the first insulating material.

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