Chip package structure and chip module

Abstract

The present application relates to the technical field of chip packaging, and particularly provides a chip packaging structure and a chip module.The chip packaging structure comprises a substrate, a first chip device, a second chip device and a filling material, the substrate is provided with a first bearing structure with at least two windows, the first chip device and the second chip device are respectively flip-chip mounted in the windows through bumps, the filling material covers the first chip device, the second chip device and the first bearing structure, a first cavity is formed between the first chip device and the substrate, and the filling material fills the area between the second chip device and the substrate and forms a second cavity.In the chip packaging structure, the filling material fills the area between the chip device and the substrate and forms a cavity, so that the instability of the packaging structure caused by the thermal expansion of the filling material can be avoided, and the stability of the chip packaging structure is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip packaging, and in particular to a chip packaging structure and a chip module. BACKGROUND

[0002] With the miniaturization of electronic devices, the market requires higher and higher integration of chips, and usually chips with different functions are integrated together and flip-chip mounted on a substrate. Generally, chips with filtering functions such as Surface Acoustic Wave (SAW) filter chips and Bulk Acoustic Wave (BAW) filter chips require a cavity structure between the chip and the substrate during packaging to meet their functional, performance or other special requirements, and chips without filtering functions are also flip-chip mounted on the substrate. In practice, it is found that changes in temperature can cause the packaging structure of the chip to become unstable. SUMMARY

[0003] The embodiments of the present application provide a chip packaging structure and a chip module, which can improve the stability of the chip packaging structure.

[0004] The first aspect of the embodiments of the present application provides a chip packaging structure, comprising:

[0005] a substrate, one side of which is provided with a first bearing structure, the first bearing structure having at least two windows;

[0006] a first chip device comprising a first chip and a plurality of first bumps, the first chip device being flip-chip mounted in a first window of the at least two windows through the plurality of first bumps;

[0007] a second chip device comprising a second chip and a plurality of second bumps, the second chip device being flip-chip mounted in a second window of the at least two windows through the plurality of second bumps;

[0008] a filling material covering the first chip device, the second chip device and the first bearing structure, so that a first cavity is formed between the first chip device and the substrate, and the filling material fills the area between the second chip device and the substrate to form a second cavity.

[0009] Optionally, the middle region of the first chip device in the first orthographic projection towards the substrate is located in the first window, and the edge region of the first orthographic projection is located on the first bearing structure.

[0010] Optionally, the second orthographic projection of the second chip device towards the substrate is located in the second window.

[0011] Optionally, a middle region of a second projection of the second chip device towards the substrate is located in the second window, and an edge region of the second projection is located on the first bearing structure.

[0012] Optionally, the filling material comprises a sealing resin containing particles.

[0013] Optionally, a distance h2 between the second chip device and the first bearing structure is greater than a maximum particle size of the particles.

[0014] Optionally, a distance h1 between the first chip device and the first bearing structure is less than or equal to the maximum particle size of the particles.

[0015] Optionally, the distance h1 is less than 5 um.

[0016] Optionally, the substrate further comprises a second bearing structure.

[0017] The second bearing structure is located in the first window; and / or,

[0018] The second bearing structure is located in the second window.

[0019] Optionally, the first chip is a filter function chip, and the second chip is a non-filter function chip.

[0020] Optionally, the chip packaging structure further comprises a protective layer, the protective layer is attached to an outer surface of the first chip device and is laid on the first bearing structure to isolate the first cavity and the filling material.

[0021] Optionally, the outer surface of the first chip device comprises a first front surface away from the substrate, and the protective layer attached to the first front surface has an opening.

[0022] Optionally, an area of the first front surface exposed to the opening is in contact with the filling material.

[0023] Optionally, the protective layer is further attached to an outer surface of the second chip device and is discontinuous with the protective layer located on the first bearing structure to form a channel between the second chip device and the first bearing structure for the filling material to enter.

[0024] Optionally, the outer surface of the second chip device comprises a side surface and a second front surface away from the substrate, the second front surface is attached with the protective layer, and at least a part of the side surface is not attached with the protective layer.

[0025] Optionally, a projection area of the second cavity towards the substrate is s, a projection area of the second chip device towards the substrate is S, and 0.2S≤s≤0.8S.

[0026] Optionally, 1 / 3S≤s≤2 / 3S.

[0027] The second aspect of the embodiment of the present application provides a chip packaging structure, characterized by comprising:

[0028] a substrate, one side of which is provided with a bearing structure, the bearing structure having at least two windows;

[0029] a first chip device flip-chip mounted in a first window of the at least two windows;

[0030] a second chip device flip-chip mounted in a second window of the at least two windows;

[0031] a first filling material filling a region between the second chip device and the substrate and forming a second cavity;

[0032] a second filling material covering the first chip device, the second chip device, the first filling material and the bearing structure, so that a first cavity is formed between the first chip device and the substrate.

[0033] The third aspect of the embodiment of the present application provides a chip packaging structure, characterized by comprising:

[0034] a substrate comprising a first surface;

[0035] a first chip device flip-chip mounted on the first surface of the substrate;

[0036] a second chip device flip-chip mounted on the first surface of the substrate;

[0037] a protective layer adhering to an outer surface of the first chip device and an outer surface of the second chip device and laid on the substrate, so that a first cavity is formed between the first chip device and the substrate;

[0038] a filling material covering the protective layer and filling a region between the second chip device and the substrate, a second cavity being formed between the second chip device and the substrate.

[0039] Optionally, the second chip device comprises a plurality of second bumps, the second chip device being flip-chip mounted on the first surface of the substrate through the plurality of second bumps, and the filling material at least partially covering at least one second bump of the plurality of second bumps.

[0040] The fourth aspect of the embodiment of the present application provides a chip module comprising any of the above chip packaging structures.

[0041] In the chip packaging structure provided by the embodiment of the present application, the filling material is filled between the chip device and the substrate and cavities are formed, so that the chip packaging structure can avoid instability caused by expansion of the filling material due to heat, and the thermal stability of the chip packaging structure is improved. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor under the premise of the drawings.

[0043] Figure 1 is a schematic diagram of a chip packaging structure provided by the embodiment of the present application;

[0044] Figure 2 is another schematic diagram of a chip packaging structure provided by the embodiment of the present application;

[0045] Figure 3 is another schematic diagram of a chip packaging structure provided by the embodiment of the present application;

[0046] Figure 4 is another schematic diagram of a chip packaging structure provided by the embodiment of the present application;

[0047] Figure 5 is another schematic diagram of a chip packaging structure provided by the embodiment of the present application;

[0048] Figure 6A is a top view of a first chip device provided by the embodiment of the present application;

[0049] Figure 6B is another top view of the first chip device provided by the embodiment of the present application;

[0050] Figure 6C is another top view of the first chip device provided by the embodiment of the present application;

[0051] Figure 6D is another top view of the first chip device provided by the embodiment of the present application;

[0052] Figure 6E is another top view of the first chip device provided by an embodiment of the present application;

[0053] Figure 6F is another top view of the first chip device provided by an embodiment of the present application;

[0054] Figure 7 is a schematic view of another chip packaging structure provided by an embodiment of the present application;

[0055] Figure 8 is a schematic view of another chip packaging structure provided by an embodiment of the present application;

[0056] Figure 9 is a schematic view of another chip packaging structure provided by an embodiment of the present application;

[0057] Figure 10 is a schematic view of another chip packaging structure provided by an embodiment of the present application;

[0058] Figure 11 is a schematic view of another chip packaging structure provided by an embodiment of the present application. DETAILED DESCRIPTION

[0059] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0060] It should be understood that the present application can be implemented in different forms and should not be interpreted as being limited to the embodiments presented herein. On the contrary, these embodiments are provided to make the disclosure complete and fully, and to fully convey the scope of the present application to those skilled in the art. In the drawings, the sizes and relative sizes of the layers and regions can be exaggerated for clarity throughout the same drawing reference numbers represent the same elements.

[0061] It will be understood that when an element or layer is referred to as being "on" or "connected to" or "coupled to" or "connected to" or "connected with" or "connected to" another element or layer, it can be directly on, connected or coupled to, or connected with, the other element or layer, or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0062] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0063] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0064] For a thorough understanding of the present application, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, in which:

[0065] The present application relates to chip packaging technical field, specifically relates to a chip packaging structure and chip module. The inventor finds that when there are multiple chip devices in the current chip packaging structure, some chip devices (such as chip devices with filtering function) need cavities, and other chip devices do not need cavities, and the filling material often fills the area between the chip devices and the substrate, but during chip aging test or working process, the temperature rise will cause the filling material to expand due to heat, so that the connection between the chip and the substrate falls off or the contact is unstable, and even causes the chip to deform. In order to solve the above problems, therefore, the present application has the inventive concept, which will be illustrated by the following embodiments:

[0066] It should be noted that the embodiments of the present application can be applied to the packaging structure of multiple non-filtering function chip devices, and can also be applied to the packaging structure of the chip module, which includes chip devices with filtering function and non-filtering function.

[0067] In an embodiment, please refer to Figure 1 , Figure 1 is a schematic diagram of a chip packaging structure provided by the embodiments of the present application. The chip packaging structure shown in the figure includes a substrate 1, a first chip device 2, a second chip device 3 and a filling material 4.

[0068] Among them, the substrate 1 can adopt resin, ceramic, quartz or other types of substrate, and the present embodiment is not limited. One side of the substrate 1 is provided with a first bearing structure 11 and a plurality of pads 12. The bearing structure 11 has at least two windows, and the pads 12 are located in the at least two windows. The opening direction of the window can be perpendicular to the substrate 1, or can have a certain angle with the substrate 1, and the present embodiment is not limited. The pads 12 can be embedded in the substrate 1, or can be arranged on the surface of the substrate 1, and the present embodiment is not limited. The pads 12 can be metal or alloy, and the metal can be nickel, palladium, molybdenum, tungsten, ruthenium, gold, magnesium, aluminum, copper, chromium, titanium, osmium, iridium, etc. The pads 12 are connected to external or internal lines through the wiring (not shown in the figure) on the substrate 1.

[0069] Specifically, the first bearing structure 11 can be a structure formed on the substrate 1 by a material with good formability and good solder resistance, or it can be a solder mask layer structure of the substrate 1, such as resin, solder mask green paint, dry film, etc., and the present embodiment is not limited.

[0070] In the embodiment, the first chip device 2 includes a first chip and a plurality of first bumps 21, the first chip device 2 is flip-chip mounted in the first opening, and the connection between the first chip device 2 and the substrate 1 is achieved by connecting the plurality of first bumps 21 with the pads 12 in the opening. The first opening is any one of the at least two openings, and the first bump 21 can be tin, gold, or other common bump types such as metal bumps, which are not limited in the embodiment.

[0071] In the embodiment, the second chip device 3 includes a second chip and a plurality of second bumps 31, the second chip device 3 is flip-chip mounted in the second opening, and the connection between the second chip device 3 and the substrate 1 is achieved by connecting the plurality of second bumps 31 with the pads 12 in the opening. The second opening is any one of the at least two openings, and the second bump 31 can be tin, gold, or other common bump types such as metal bumps, which are not limited in the embodiment.

[0072] In one embodiment, the distance h1 between the first chip device 2 and the first supporting structure 11 is less than the distance h2 between the second chip device 3 and the first supporting structure 11.

[0073] Optionally, the distance h1 between the first chip device 2 and the first supporting structure 11 is less than 5 um, and h1 can be 4 um, 3 um, 1 um, or the like, which is not limited in the embodiment.

[0074] It should be noted that h1 can be the minimum distance, for example, the vertical distance, between the first chip device 2 and the first supporting structure 11. h2 can be the minimum distance between the second chip device 3 and the first supporting structure 11.

[0075] In the embodiment, the filler 4 covers the first chip device 2, the second chip device 3, and the first supporting structure 11, so that the first chip device 2 forms a first cavity 5 with the substrate 1 in the first opening, and the filler 4 fills the area between the second chip device 3 and the substrate 1, so that a second cavity 6 is formed between the second chip device 3 and the substrate 1.

[0076] It can be understood that the second cavity 6 is formed between the second chip device 3 and the substrate in the second opening, which can be between the fillers 4 as shown in Figure 1 It can be understood that the second cavity 6 is formed between the second chip device 3 and the substrate in the second opening, which can be between the fillers 4 as shown in

[0077] In the embodiment, the second cavity 6 can be formed by controlling the pressure of the process, the amount of the filling material 4, the size of the area between the second chip device 3 and the substrate 1, and other ways, which are not limited in the embodiment.

[0078] In an embodiment, the filling material 4 at least partially covers at least one of the plurality of second bumps 31. The thermal stability of the second chip device 3 can be further improved while increasing the connection stability of the second bump 31 and the pad 12.

[0079] Specifically, the filling material 4 is used to isolate the chip device from the external environment, avoid the humidity, temperature, particles and other factors of the external environment from affecting the chip device, so as to protect the chip device. The filling material 4 can be plastic sealing material, which can be sealing resin or other insulating materials with weak fluidity.

[0080] In an embodiment, the area of the second cavity 6 in the orthographic projection towards the substrate 1 is smaller than the area of the first cavity 5 in the orthographic projection towards the substrate 1.

[0081] In another embodiment, the volume of the second cavity 6 is smaller than the volume of the first cavity 5.

[0082] In yet another embodiment, the area of the second cavity 6 in the orthographic projection towards the substrate 1 is s, the area of the second chip device 3 in the orthographic projection towards the substrate 1 is S, and the relationship between the area s of the second cavity 6 in the orthographic projection towards the substrate 1 and the area S of the second chip device 3 in the orthographic projection towards the substrate 1 can be 0.2S≤s≤0.8S.

[0083] Further, the relationship between the area s of the second cavity 6 in the orthographic projection towards the substrate 1 and the area S of the second chip device 3 in the orthographic projection towards the substrate 1 can also be 0.25S≤s≤0.75S.

[0084] Further, the relationship between the area s of the second cavity 6 in the orthographic projection towards the substrate 1 and the area S of the second chip device 3 in the orthographic projection towards the substrate 1 can also be 1 / 3S≤s≤2 / 3S.

[0085] For example, the relationship between the area s of the second cavity 6 in the orthographic projection towards the substrate 1 and the area S of the second chip device 3 in the orthographic projection towards the substrate 1 can be s=0.2S, s=0.25S, s=0.3S, s=0.4S, s=0.5S, s=0.6S, s=0.7S, s=0.75S, s=0.8S, etc., which are not limited in the embodiment.

[0086] In the embodiment, the second cavity 6 is generally formed in the middle area close to the second chip device 3, and can also be formed in other areas, which are not limited in the embodiment.

[0087] It should be noted that in the embodiments of the present application, the orthographic projection towards the substrate can be understood as the projection perpendicular to the substrate, and the following will not be described in detail.

[0088] The chip module is generally arranged with a plurality of chip devices, and the density is large. If each chip device has a large cavity, the cavity area of the chip module will be too large, thereby reducing the structural strength. In the embodiments, the orthographic projection area of the second cavity 6 towards the substrate 1 is smaller than the orthographic projection area of the first cavity 5 towards the substrate 1, or the volume of the second cavity 6 is smaller than the volume of the first cavity 5, or the relationship between the orthographic projection area s of the second cavity 6 towards the substrate 1 and the orthographic projection area S of the second chip device 3 towards the substrate 1 satisfies 0.2S≤s≤0.8S. In this way, the influence of the thermal expansion of the filler 4 on the stability of the second chip device can be avoided, and the structural strength of the entire chip module can be improved, thereby improving the reliability of the chip packaging structure.

[0089] In one embodiment, as shown in Figure 2 , Figure 2 is a schematic view of another chip packaging structure provided by the embodiments of the present application. In Figure 2 , the first chip device 2 has a first orthographic projection towards the substrate 1, wherein the middle region is located in the first window, and the edge region is located on the first bearing structure 11; the second chip device 3 has a second orthographic projection towards the substrate 1, wherein the middle region is located in the second window, and the edge region is located on the first bearing structure 11.

[0090] That is, a part of the first bearing structure 11 extends to the region between the first chip device 2 and the substrate 1 and extends to the region between the second chip device 3 and the substrate 1, and is arranged opposite to the edge of the first chip device 2 and the second chip device 3. The area of the first window on the substrate 1 is smaller than the projection area of the first chip device 2 on the substrate 1, and the area of the second window on the substrate 1 is also smaller than the projection area of the second chip device 3 on the substrate 1.

[0091] In the present embodiment, the first bearing structure 11 exists in the edge region between the second chip device 3 and the substrate 1, which can reduce the channel size of the filler 4 entering the region between the second chip device 3 and the substrate 1, and the filler 4 is more likely to form the second cavity 6 in the region between the second chip device 3 and the substrate 1, thereby avoiding the filler 4 from being expanded by heat to cause the connection between the second chip device 3 and the substrate 1 to fall off or unstable contact, or even cause the second chip device 3 to deform, thereby improving the stability of the chip packaging structure.

[0092] In another embodiment, as shown in Figure 1As shown, the first chip device 2 is located in the first window in the middle region of the first orthographic projection towards the substrate 1, and the edge region of the first orthographic projection is located on the first bearing structure 11; the second chip device 3 is located in the second window in the second orthographic projection towards the substrate 1.

[0093] That is, a part of the first bearing structure 11 extends to the region between the first chip device 2 and the substrate 1, and is arranged opposite to the edge of the first chip device, the first bearing structure 11 does not extend to the region between the second chip device 3 and the substrate 1, the area of the first window on the substrate 1 is smaller than the projection area of the first chip device 2 on the substrate 1, and the area of the second window on the substrate 1 is greater than the projection area of the second chip device 3 on the substrate 1.

[0094] In the embodiment, the first chip is a filter functional chip, such as a surface acoustic wave filter, a bulk acoustic wave filter and the like, which includes a functional area, and a plurality of first bumps 21 are arranged around the periphery of the functional area; the second chip is a non-filter functional chip, such as a power amplifier, a low-noise amplifier, a radio frequency switch and the like.

[0095] In an embodiment, the filling material 4 includes a sealing resin containing particles. The particles can be silicon dioxide (SiO2) particles, aluminum oxide (Al2O3) particles, or a combination of multiple particles, which is not limited in the embodiment of the present application.

[0096] Optionally, the distance between the first chip device 2 and the first bearing structure 11 located at the edge of the first window is less than or equal to the maximum particle size of the particles in the filling material 4, which can play a blocking role, so that the filling material 4 does not flow into the first cavity 5 during the process, avoiding contamination of the filter functional chip, thereby improving the reliability of the chip device.

[0097] Optionally, the distance h2 between the second chip device 3 and the first bearing structure 11 located at the edge of the second window is greater than the maximum particle size of the particles in the filling material 4, so that the filling material 4 can smoothly enter the region between the second chip device 3 and the substrate 1.

[0098] In the embodiment of the present application, the filling material is filled between the second chip device and the substrate and forms a cavity, which can avoid the instability of the packaging structure due to the thermal expansion of the filling material when the temperature rises, thereby improving the thermal stability of the chip packaging structure.

[0099] In another embodiment, please refer to Figure 3 , Figure 3 is another schematic diagram of a chip packaging structure provided by the embodiment of the present application. The embodiment can have the same structure as the previous embodiment, and the embodiment will not be described here. The difference between the embodiment and the previous embodiment is that:

[0100] The substrate 1 is further provided with a second bearing structure 13, which is located in the first window, or which is located in the second window, or which is located in the first window and the second window.

[0101] It can be understood that the second bearing structure 13 located in the first window can be located in the range surrounded by the plurality of first bumps 21, and can be continuous or discontinuous relative to the functional area of the first chip. The second bearing structure 13 located in the second window can be located in the area between any two second bumps 31, and can be continuous or discontinuous, which is not limited in the embodiment.

[0102] Specifically, the second bearing structure 13 can be a structure formed by a material with good formability and good solder resistance on the substrate 1, or can be a structure of a solder resist layer of the substrate 1, such as resin, solder resist green paint, dry film, etc., which is not limited in the embodiment.

[0103] It should be noted that the second bearing structure 13 and the first bearing structure 11 can be prepared in the same process, or can be prepared in different processes, and can use the same material or different materials, which is not limited in the embodiment.

[0104] In addition, when the second bearing structure 13 and the first bearing structure 11 are prepared in the same process, a plurality of slots can be provided on the bearing structure, so that the bumps of the chip device can contact the pads on the substrate through the plurality of slots. The size of each slot can be just capable of accommodating the bump, or can be capable of accommodating a plurality of bumps at the same time, which is not limited in the embodiment.

[0105] It can be understood that the second bearing structure 13 is located in the second window and is opposite to the second chip device 3, so that the filling material 4 is less likely to enter the area between the second chip device 3 and the substrate 1, thereby being more helpful to form the second cavity, and the formed second cavity can be more easily maintained, and the thermal stability of the chip packaging structure is higher.

[0106] In Figure 3 , the second chip device 3 is located in the second window in the second projection toward the substrate 1, and in combination with the second bearing structure 13 in the second window, the filling material 4 can more easily form the second cavity 6 between the second chip device 3 and the substrate 1 (which can be the second bearing structure 13), thereby avoiding the instability of the second chip device 3 caused by the thermal expansion of the filling material 4.

[0107] In yet another embodiment, please refer to Figure 4 , Figure 4is a schematic view of another chip packaging structure provided by an embodiment of the present application. The embodiment can have the same structure as the above two embodiments, and the embodiment will not be described here again. The difference between the embodiment and the above two embodiments is that:

[0108] The chip packaging structure further comprises a protective layer 7, which is attached to the outer surface of the first chip device 2 and laid on the first bearing structure 11 to isolate the first cavity 5 from the filling material 4.

[0109] It can be understood that the first chip device 2 comprises an inner surface and an outer surface, the inner surface being the surface opposite to the substrate 1, and the outer surface being other surfaces except the inner surface, such as the side surface and the front surface away from the substrate 1.

[0110] Specifically, the protective layer 7 is used to isolate the first cavity 5 from the filling material 4 or to block the filling material 4 from entering the first cavity 5 to pollute the cavity environment. The protective layer 7 can be an epoxy resin film, or other polymer films such as dry films or other resin materials. The protective layer 7 can be a material that has a certain ductility at high temperature but poor fluidity, and does not present a liquid state at high temperature, so that the protective layer 7 can better cover surfaces of various shapes and can play a better blocking role.

[0111] It should be noted that the protective layer 7 is attached to the outer surface of the first chip device 2 to isolate the first cavity 5 from the filling material 4, so that the filling material 4 cannot enter and pollute the first cavity 5 through the gap between the first chip device 2 and the first bearing structure 11 during the process, thereby causing the chip in the cavity to fail or affecting the working performance of the chip. Through the structure of the embodiment, the reliability of the chip device can be improved.

[0112] In an embodiment, please refer to Figure 5 , Figure 5 is a schematic view of another chip packaging structure provided by an embodiment of the present application. The outer surface of the first chip device 2 comprises a first front surface 22 away from the substrate 1 and a side surface 23, and the protective layer 7 attached to the first front surface 22 has an opening 71.

[0113] It can be understood that the opening 71 can penetrate the protective layer 7, so that the first front surface 22 exposed in the area of the opening 71 is in contact with the filling material 4; the opening 71 can also not penetrate the protective layer 7, that is, the bottom of the opening 71 is on the protective layer 7, and the first front surface 22 is thus not exposed and in contact with the filling material 4.

[0114] In an embodiment, please refer to Figure 6A to Figure 6F , Figure 6A to Figure 6F is a top view of the first chip device 2. As shown in Figure 6A , the shape of the first opening 71 can be square; as shown in Figure 6B , it can also be multiple circular or elliptical shapes; as shown inFigure 6C As shown, it can also be an irregular shape; such as Figure 6D As shown, it can also be a ring; such as Figure 6E As shown, it can also be a cross-shaped opening; it can also be as shown in the image. Figure 6F The ring shape is shown. In this embodiment, the shape of the first opening 71 can be regular or irregular, and the number of first openings 71 can be one or more. This embodiment does not limit the shape, number, or size of the first openings 71, as long as they allow the protective layer 4 to adhere to the side 23. The first opening 71 does not extend beyond the edge of the first front surface 22. The first opening 71 can be close to the middle area of ​​the first front surface 22 or the edge area of ​​the first front surface 22. This embodiment does not limit this.

[0115] In the manufacturing process, a protective layer is typically first laid on the side of the chip device away from the substrate. Then, pressure is applied to the protective layer between the chip devices, or to the protective layer outside the chip devices, facing the substrate. This causes the protective layer to adhere to the outer surface of the chip device and the substrate, forming a sealed cavity between the chip device and the substrate. A filler is then applied over the protective layer. Due to the limited ductility of the protective layer, this process can easily lead to breakage, allowing the filler to enter the cavity through the break, causing chip failure or affecting chip performance. In this embodiment, the protective layer 7 has an opening on the first front side 22 of the first chip device 2, which reduces the limitation of the protective layer 7's ductility to a certain extent, thereby preventing breakage and improving chip packaging reliability.

[0116] Furthermore, the protective layer 7 has an opening 71 on the front side of the first chip device 2, which allows the filler 4 to contact the first chip device 2 at the opening 71, thereby increasing the bonding force between the first chip device 2 and the protective layer 7 and the filler 4, and improving the reliability of the packaging structure.

[0117] In another embodiment, please refer to Figure 7 and Figure 8 , Figure 7 and Figure 8 This is a schematic diagram of another chip packaging structure provided in an embodiment of the present invention. The protective layer 7 may also be attached to the outer surface of the second chip device 3 and is discontinuous with the protective layer 7 located on the first support structure 11, so as to form a channel 8 between the second chip device 3 and the first support structure 11 for the filler 4 to enter.

[0118] It is understood that the protective layer 7 is attached to the outer surface of the second chip device 3 and is disconnected from or has a gap with the protective layer 7 located on the first support structure 11, so that there is a channel 8 between the second chip device 3 and the first support structure 11, and the filler 4 can easily enter to fill the area between the second chip device 3 and the substrate 1.

[0119] That is, the channel 8 can have one or multiple, can be disconnected from the protective layer 7 between the second chip device 3 and the first bearing structure 11, forming a larger channel, or can be spaced apart to form multiple channels, which is not limited in the embodiment.

[0120] Further, the filling material 4 can at least partially cover at least one of the plurality of second bumps 31, so that the area between the second chip device 3 and the substrate 1 is filled with sufficient filling material 4, so that the connection stability of the second bump 31 of the second chip device 3 and the pad 12 is improved, and the structural strength of the second chip device is also improved, and there is a cavity, and the filling material 4 does not cause thermal expansion due to too much filling material 4. The filling material 4 can partially cover the second bump 31, or can completely cover the second bump 31, which is not limited in the embodiment.

[0121] In one embodiment, the second projection of the second chip device 3 towards the substrate 1 is located in the second window. The filling material 4 can more easily enter the area between the second chip device 3 and the substrate 1, so that the filling material 4 can at least partially cover at least one of the plurality of second bumps 31. Further, the substrate 1 is also provided with a second bearing structure 13 located in the second window, and the filling material 4 can more easily form a second cavity 6 between the second chip device 3 and the substrate 1 (or the second bearing structure 13), to avoid the filling material 4 from causing unstable packaging of the second chip device 3 due to thermal expansion. In this way, the connection stability between the second bump 31 and the pad 12 can be better guaranteed, and the overall thermal stability of the chip packaging structure is also improved.

[0122] In another embodiment, please refer to Figure 9 and Figure 10 , Figure 9 and Figure 10 are schematic diagrams of another chip packaging structure provided by the embodiment of the application. The outer surface of the second chip device 3 includes a side surface 33 and a second front surface 32 away from the substrate 1, and the second front surface 32 is attached with a protective layer 7, and at least a part of the side surface 33 is not attached with the protective layer 7.

[0123] That is, the second front surface 32 can be left with the protective layer 7, and at least a part of the side surface 33 is not attached with the protective layer 7, which can be that the side surface 33 is not attached with the protective layer 7, or one side surface is not attached with the protective layer 7, or a part of one side surface is not attached with the protective layer 7, which is not limited in the embodiment.

[0124] It can be understood that the protective layer 7 can be processed by laser (laser) to be disconnected or form a notch between the protective layer 7 attached to the outer surface of the second chip device 3 and the protective layer 7 attached to the first bearing structure 11.

[0125] In yet another embodiment, the thickness of the protective layer 7 is H, the distance between the first chip device 2 and the first bearing structure 11 is h1, and the relationship between the two can satisfy: 0.9H < h1 ≤ 2H. Specifically, h1 = H, h1 = 1.3H, h1 = 1.6H, h1 = 1.8H, and the embodiment is not limited.

[0126] Preferably, 0.9H < h1 ≤ 1.5H.

[0127] It can be understood that the relationship between the distance h1 between the first chip device 2 and the first bearing structure 11 and the thickness H of the protective layer 7 satisfies the above condition, the protective layer 7 is not easy to break, and the filler 4 thus will not enter the first cavity 5 to pollute the cavity environment.

[0128] In yet another embodiment, please refer to Figure 11 , Figure 11 Another schematic diagram of a chip packaging structure provided by the embodiment of the present application. In Figure 11 , the chip packaging structure comprises: a substrate 1, which is provided with a bearing structure 11 on one side, the bearing structure 11 has at least two windows, and the substrate 1 is also provided with a plurality of pads 12; a first chip device 2, which is flip-chip mounted in a first window of the at least two windows, specifically flip-chip mounted in the window through a first bump 21 and in contact with the pad 12; a second chip device 3, which is flip-chip mounted in a second window of the at least two windows, specifically flip-chip mounted in the window through a first bump 31 and in contact with the pad 12; a first filler 9, which is filled into the area between the second chip device 3 and the substrate 1 and forms a second cavity 6; and a second filler 4, which covers the first chip device 2, the second chip device 3, the first filler 9 and the bearing structure 11, so that a first cavity 5 is formed between the first chip device 2 and the substrate 1.

[0129] The embodiment has the same structure compared with the above-mentioned embodiments, and the embodiment will not be described here again. The difference between the embodiment and the above-mentioned two embodiments is that:

[0130] The first filler 9 is first filled into the area between the second chip device 3 and the substrate 1 and forms the second cavity 6, so as to ensure that the first filler 9 will not cause unstable connection between the second chip device 3 and the substrate 1 or deformation of the second chip device 3 when it expands due to heat, thereby improving the stability of the chip packaging structure.

[0131] The first filler 9 and the second filler 4 can be different materials or the same material, such as resin materials containing particles, and the volume of the particles contained in the first filler 9 is smaller than that contained in the second filler 4, so as to facilitate the first filler 9 to enter the area between the second chip device 3 and the substrate 1 from the area between the second chip device 3 and the bearing structure 11.

[0132] In yet another embodiment, the chip package structure comprises: a substrate having a first surface provided with a carrier structure, the carrier structure having at least two windows; a first chip device flip-chip mounted in a first window of the at least two windows; a second chip device flip-chip mounted in a second window of the at least two windows; a first filler filling a region between the second chip device and the substrate; and a second filler covering the first chip device, the second chip device, the first filler, and the carrier structure, so that a first cavity is formed between the first chip device and the substrate; the first filler has a modulus smaller than that of the second filler.

[0133] It can be understood that the embodiment differs from the previous embodiment in that the first filler, after filling the region between the second chip device and the substrate, does not form a cavity, and the modulus (i.e. stress) of the first filler is smaller than that of the second filler, so that even if the first filler expands due to heat, the second chip device and the substrate are not connected unstably or the second chip device is deformed, thereby improving the stability of the chip package structure.

[0134] In yet another embodiment, the chip package structure comprises: a substrate comprising a first surface; a first chip device flip-chip mounted on the first surface of the substrate; a second chip device flip-chip mounted on the first surface of the substrate; a protective layer adhering to an outer surface of the first chip device and an outer surface of the second chip device, and laid on the substrate, so that a first cavity is formed between the first chip device and the substrate; and a filler covering the protective layer and filling a region between the second chip device and the substrate, so that a second cavity is formed between the second chip device and the substrate.

[0135] It can be understood that the first surface of the substrate is the surface provided with pads, and the first chip device and the second chip device are both flip-chip mounted on the first surface through bumps, and the pads are connected. The protective layer adhering to the outer surface of the second chip device is discontinuous, such as having a gap or being completely disconnected, between the protective layer adhering to the outer surface of the second chip device and the protective layer laid on the substrate, and the filler can enter and fill the region between the second chip device and the substrate from the discontinuity.

[0136] Specifically, the first chip device comprises a first chip and a plurality of first bumps, and the first chip device is flip-chip mounted on the first surface of the substrate through the plurality of first bumps; the second chip device comprises a second chip and a plurality of second bumps, and the second chip device is flip-chip mounted on the first surface of the substrate through the plurality of second bumps; and when the filler fills the region between the second chip device and the substrate, the filler at least partially covers at least one of the plurality of second bumps.

[0137] In the embodiment, the protective layer is attached to the outer surface of the first chip device and the outer surface of the second chip device respectively, so that the first chip device and the substrate have a first cavity therebetween, and the filling material covers the protective layer, and the protective layer can prevent the filling material from entering the first cavity, thereby avoiding the pollution of the cavity environment to cause the first chip to fail or affect the working performance. The filling material can pass through the protective layer to fill the area between the second chip device and the substrate, so that the second chip device and the substrate have a second cavity therebetween, which can avoid the filling material from expanding due to heat to cause unstable connection between the second chip device and the substrate or deformation of the second chip device, thereby improving the stability of the chip packaging structure.

[0138] The embodiment of the present application further provides a chip module comprising the chip packaging structure mentioned in the present application. The chip module can comprise a plurality of non-filtering functional chip devices, or a plurality of filtering functional chip devices and a plurality of non-filtering functional chip devices.

[0139] The above-mentioned embodiments are only used to illustrate the technical solutions of the present application, but not limit the same; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalent ones; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A chip packaging structure, characterized in that, include: A substrate having a first support structure and a plurality of pads on one side, wherein the first support structure has at least two openings; A first chip device includes a first chip and a plurality of first bumps. The first chip device is flip-mounted into a first window of at least two openings via the plurality of first bumps. The plurality of first bumps are connected to pads in the first window. The second chip device includes a second chip and a plurality of second bumps. The second chip device is flip-mounted into the second window of the at least two openings via the plurality of second bumps. The plurality of second bumps are connected to pads in the second window. A filler material covers the first chip device, the second chip device, and the first carrier structure, such that a first cavity is formed between the first chip device and the substrate. The filler material fills the area between the second chip device and the substrate, forming a second cavity. The projected area of ​​the second cavity toward the substrate is smaller than the projected area of ​​the first cavity toward the substrate. The filler material includes a sealing resin containing particulate matter.

2. The chip packaging structure according to claim 1, characterized in that, The first chip device is located within the first window in the middle region of the first orthographic projection toward the substrate, and the edge region of the first orthographic projection is located on the first support structure.

3. The chip packaging structure according to claim 1 or 2, characterized in that, The second chip device is located within the second window in a second orthographic projection toward the substrate.

4. The chip packaging structure according to claim 1 or 2, characterized in that, The second chip device is located within the second window in the middle region of the second orthographic projection toward the substrate, and the edge region of the second orthographic projection is located on the first support structure.

5. The chip packaging structure according to claim 1, characterized in that, The distance h2 between the second chip device and the first support structure is greater than the maximum particle size of the particulate matter.

6. The chip packaging structure according to claim 1, characterized in that, The distance h1 between the first chip device and the first support structure is less than or equal to the maximum particle size of the particulate matter.

7. The chip packaging structure according to claim 1, characterized in that, The distance h1 between the first chip device and the first support structure is less than 5 μm.

8. The chip packaging structure according to claim 1, characterized in that, The substrate is also provided with a second support structure; The second load-bearing structure is located within the first window; and / or, The second load-bearing structure is located within the second window.

9. The chip packaging structure according to claim 1, characterized in that, The first chip is a filtering chip, and the second chip is a non-filtering chip.

10. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure further includes a protective layer, which is attached to the outer surface of the first chip device and laid on the first support structure to isolate the first cavity from the filler.

11. The chip packaging structure according to claim 10, characterized in that, The outer surface of the first chip device includes a first front side away from the substrate, and a protective layer attached to the first front side has an opening.

12. The chip packaging structure according to claim 11, characterized in that, The area of ​​the first front exposed to the opening is in contact with the filler.

13. The chip packaging structure according to any one of claims 10-12, characterized in that, The protective layer also adheres to the outer surface of the second chip device and is discontinuous with the protective layer located on the first support structure to form a channel between the second chip device and the first support structure for the filling material to enter.

14. The chip packaging structure according to claim 13, characterized in that, The outer surface of the second chip device includes a side surface and a second front surface away from the substrate, the second front surface being attached to the protective layer, and at least a portion of the side surface not being attached to the protective layer.

15. The chip packaging structure according to claim 1, characterized in that, The projected area of ​​the second cavity toward the substrate is s, and the projected area of ​​the second chip device toward the substrate is... .

16. The chip packaging structure according to claim 15, characterized in that, 。 17. A chip packaging structure, characterized in that, include: A substrate having a support structure and multiple pads on one side, wherein the support structure has at least two openings; A first chip device is flip-mounted within a first window of the at least two windows, and the first window is provided with the solder pads. The second chip device is flip-chip mounted in the second window of the at least two windows, and the second window is provided with the solder pads. A first filler is used to fill the area between the second chip device and the substrate, forming a second cavity; The second filler material covers the first chip device, the second chip device, the first filler material, and the carrier structure, thereby forming a first cavity between the first chip device and the substrate.

18. A chip packaging structure, characterized in that, include: The substrate includes a first surface; A first chip device is flip-mounted onto the first surface of the substrate; The second chip device is flip-chip mounted on the first surface of the substrate; A protective layer is attached to the outer surfaces of the first chip device and the second chip device and laid on the substrate, so that a first cavity is formed between the first chip device and the substrate; A filler material covers the protective layer and fills the area between the second chip device and the substrate, forming a second cavity between the second chip device and the substrate. The projected area of ​​the second cavity toward the substrate is smaller than the projected area of ​​the first cavity toward the substrate. The filler material includes a sealing resin containing particulate matter.

19. The chip packaging structure according to claim 18, characterized in that, The second chip device includes a plurality of second bumps, the second chip device being flip-mounted onto a first surface of the substrate via the plurality of second bumps, and the filler material at least partially covering at least one of the plurality of second bumps.

20. A chip module, characterized in that, Includes the chip packaging structure as described in any one of claims 1-19.

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