Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate having a fin thereon, the fin extending along a first direction, the fin comprising a plurality of first regions and at least one second region, the second region being located between adjacent first regions, the first region and the second region being arranged along the first direction; forming a first isolation layer on the substrate, the first isolation layer covering a portion of the sidewalls of the fin, the surface of the first isolation layer being lower than the top surface of the fin; forming a first gate structure spanning the fin and a source / drain doped region located in the fin on both sides of the first gate structure on each first region, the first gate structure covering a portion of the sidewalls and the top surface of the fin; forming an isolation trench in the second region, the isolation trench layer penetrating the fin along a second direction, the second direction being perpendicular to the first direction; performing surface treatment on the surface of the isolation trench; forming a second isolation layer in the isolation trench after the surface treatment; the performance of the semiconductor structure finally formed can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] As the integration density of semiconductor devices increases, the critical dimensions of transistors continue to shrink. However, as transistor dimensions decrease dramatically, the gate dielectric thickness and operating voltage cannot be adjusted accordingly, making it more difficult to suppress the short channel effect and increasing the channel leakage current of the transistor.

[0003] The gate of the Fin Field-Effect Transistor (FinFET) is a forked 3D structure similar to a fish fin. The channel of the FinFET protrudes from the surface of the substrate to form a fin, and the gate covers the top surface and sidewalls of the fin, so that an inversion layer is formed on each side of the channel, which can control the connection and disconnection of the circuit on both sides of the fin. This design can increase the control of the gate over the channel region, thereby effectively suppressing the short channel effect of the transistor. However, the short channel effect still exists in the Fin Field-Effect Transistor.

[0004] Furthermore, to further reduce the impact of the short channel effect on semiconductor devices and lower channel leakage current, strained silicon technology has been introduced into the field of semiconductor technology. The strained silicon technology method includes: forming grooves in the fins on both sides of the gate structure; and forming source and drain doped regions in the grooves through an epitaxial growth process.

[0005] In order to prevent the source and drain doping regions of different transistors from being connected to each other, an isolation layer needs to be formed in the fin. At the same time, in order to reduce the area of the isolation layer and improve the integration of the formed semiconductor structure, the existing technology introduces SDB (Single Diffusion Break) technology.

[0006] However, the semiconductor structures formed by existing methods have poor performance. Summary of the Invention

[0007] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the finally formed semiconductor structure.

[0008] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate has a fin, the fin extends along a first direction, the fin includes a plurality of first regions and at least one second region, the second region is located between two adjacent first regions, and the first region and the second region are arranged along the first direction; forming a first isolation layer on the substrate, the first isolation layer covering a portion of the sidewalls of the fin, and the surface of the first isolation layer is lower than the top surface of the fin; forming a first gate structure spanning the fin and a source-drain doped region located in the fin on both sides of the first gate structure on each first region, the first gate structure covering a portion of the sidewalls and the top surface of the fin; forming an isolation trench in the second region, the isolation trench layer passing through the fin along a second direction, the second direction being perpendicular to the first direction; performing surface treatment on the surface of the isolation trench; and forming a second isolation layer in the isolation trench after the surface treatment.

[0009] Optionally, the surface treatment is performed by surface solution treatment, surface ion implantation treatment, or a combination of surface solution treatment and surface ion implantation treatment.

[0010] Optionally, when the surface treatment method adopts surface solution treatment, a mixed solution of sulfuric acid and hydrogen peroxide in a ratio of 1:1 is used, the treatment time is 10 seconds to 30 seconds, and the treatment temperature is room temperature.

[0011] Optionally, when the surface treatment is performed by surface ion implantation, the implanted ions are boron ions, the implantation energy is less than 10 KeV, and the implantation dose is 10E14 atoms / cm 2 .

[0012] Optionally, before forming the first gate structure and the isolation trench, the method further includes: forming a first dummy gate structure on each of the first regions; and forming a second dummy gate structure on the second region.

[0013] Optionally, the source and drain doped regions are formed after forming the first dummy gate structure and the second dummy gate structure and before forming the isolation trench.

[0014] Optionally, the source-drain doping region formation process includes an epitaxial growth process.

[0015] Optionally, after forming the source / drain doped regions, the method further includes: forming a dielectric layer on the first isolation layer, wherein the dielectric layer covers the first dummy gate structure and the second dummy gate structure.

[0016] Optionally, the method for forming the first dummy gate structure includes: forming a first gate dielectric layer on the first isolation layer; forming a first dummy gate layer on the first gate dielectric layer; and forming a first sidewall spacer on a sidewall of the first dummy gate layer.

[0017] Optionally, the method for forming the second dummy gate structure includes: forming a second gate dielectric layer on the first isolation layer; forming a second dummy gate layer on the second gate dielectric layer; and forming a second spacer on the sidewall of the second dummy gate layer.

[0018] Optionally, the method for forming the isolation trench includes: removing the second dummy gate layer to form a second dummy gate opening; and etching the fin exposed by the second dummy gate opening to form the isolation trench.

[0019] Optionally, the method for forming the second isolation layer includes: forming a stop layer on the dielectric layer, the stop layer having a stop layer opening exposing the second pseudo gate layer, forming an initial second isolation layer in the isolation trench, the second pseudo gate opening and the stop layer opening; flattening the initial second isolation layer until the top surface of the stop layer is exposed; forming the second isolation layer; and removing the stop layer after forming the second isolation layer.

[0020] Optionally, the method for forming the first gate structure includes: removing the first dummy gate layer to form a first dummy gate opening; and forming a first gate layer in the first dummy gate opening, wherein the first gate layer is located on the first gate dielectric layer.

[0021] Optionally, the first dummy gate layer is removed after the second isolation layer is formed.

[0022] Optionally, the material of the dielectric layer includes silicon dioxide, a low-k dielectric material, or an ultra-low-k dielectric material.

[0023] Optionally, the material of the stop layer is different from the material of the dielectric layer, and the material of the stop layer includes silicon nitride.

[0024] Optionally, the material of the second isolation layer includes silicon nitride or silicon oxynitride.

[0025] Correspondingly, the present invention also provides a semiconductor structure formed by the above method, comprising: a substrate, wherein the substrate has a fin, the fin extends along a first direction, the fin includes multiple first regions and at least one second region, the second region is located between two adjacent first regions, and the first region and the second region are arranged along the first direction; a first isolation layer located on the substrate, the first isolation layer covers part of the side walls of the fin, and the surface of the first isolation layer is lower than the top surface of the fin; a first gate structure located on each first region, and a source-drain doped region located in the fin on both sides of the first gate structure, the first gate structure covers part of the side walls and top surface of the fin; an isolation trench located in the second region, the isolation trench passes through the fin along a second direction, and the second direction is perpendicular to the first direction; a second isolation layer located in the isolation trench.

[0026] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0027] In the technical solution of the present invention, before forming the second isolation layer in the isolation trench, the surface of the isolation trench is subjected to surface treatment. The surface treatment is used to release the charges accumulated on the surface of the isolation trench or to block the movement path of the charges on the surface of the isolation trench, thereby solving the problem of affecting the IDDQ performance of the ring oscillator due to leakage of the single diffusion region cutoff SDB (Single Diffusion Break), and improving the performance of the semiconductor device finally formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 3 It is a structural diagram of a semiconductor structure;

[0029] Figures 4 to 12 It is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0030] As described in the background art, the semiconductor structure formed by the existing method has poor performance.

[0031] Please refer to Figure 1 and Figure 2 , Figure 2 yes Figure 1A cross-sectional schematic diagram along the AA direction provides a substrate 100, wherein the substrate 100 has a fin 101, the fin 101 extends along a first direction, and the fin 101 includes a plurality of first regions I and at least one second region II, wherein the second region II is located between two adjacent first regions I, and the first region I and the second region II are arranged along the first direction; a first isolation layer 102 is formed on the substrate 100, the first isolation layer 102 covers a portion of the side wall of the fin 101, and the surface of the first isolation layer 102 is lower than the top surface of the fin 101.

[0032] Please refer to Figure 3 , it should be noted that, Figure 3 and Figure 2 In accordance with the viewing direction, a first gate structure 103 spanning the fin 101 and a source-drain doped region 104 located in the fin 101 on both sides of the first gate structure 103 are respectively formed on each first region I, and the first gate structure 103 covers part of the sidewall and top surface of the fin 101; a dielectric layer 106 is formed on the first isolation layer 102, and the dielectric layer 106 covers the first gate structure 103.

[0033] Please continue to refer to Figure 3 A second isolation layer 105 is formed in the second region II. The second isolation layer 105 penetrates the fin 101 along a second direction. The second direction is perpendicular to the first direction.

[0034] In the above embodiment, the second isolation layer 105 is used as a single diffusion cutoff (SDB) to prevent the source and drain doped regions 104 of each first region I from being connected to each other, thereby achieving an isolation effect. However, before the second isolation layer 105 is formed, an isolation trench for filling the second isolation layer 214 is formed in the fin, and a lot of charges accumulate on the surface of the isolation trench. These charges will cause the ring oscillator to draw a large current from the power supply during the IDDQ test. Moreover, since the charges accumulate on the surface of the isolation trench, leakage is likely to occur at the single diffusion cutoff (SDB) during use. This leakage phenomenon has a very serious impact on the IDDQ test results of the ring oscillator, thereby affecting the performance of the semiconductor device.

[0035] On this basis, the present invention provides a semiconductor structure and a method for forming the same. Before forming the second isolation layer in the isolation trench, the surface of the isolation trench is subjected to surface treatment. The surface treatment is used to release the charges accumulated on the surface of the isolation trench or to block the movement path of the charges on the surface of the isolation trench, thereby solving the problem of affecting the performance of the ring oscillator due to leakage of the single diffusion region cutoff SDB (Single Diffusion Break), and improving the performance of the semiconductor device finally formed.

[0036] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] Figures 4 to 12 , is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0038] Please refer to Figure 4 and Figure 5 , Figure 5 yes Figure 4 A cross-sectional schematic diagram along the AA direction provides a substrate 200, wherein the substrate 200 has a fin 201, wherein the fin 201 extends along a first direction, and wherein the fin 201 includes a plurality of first regions I and at least one second region II, wherein the second region II is located between two adjacent first regions I, and the first region I and the second region II are arranged along the first direction.

[0039] The method for forming the substrate 200 and the fin 201 includes: providing an initial substrate (not shown), the initial substrate having a mask layer (not shown), the mask layer exposing a portion of the top surface of the initial substrate; etching the initial substrate using the mask layer as a mask to form the substrate 200 and the fin 201 located on the substrate 200.

[0040] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0041] In this embodiment, the material of the fin 201 is silicon; in other embodiments, the material of the fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0042] Please continue to refer to Figure 5 A first isolation layer 202 is formed on the substrate 200 , where the first isolation layer 202 covers a portion of the sidewall of the fin 201 , and a surface of the first isolation layer 202 is lower than a top surface of the fin 201 .

[0043] The method for forming the first isolation layer 202 includes: forming an initial first isolation layer (not shown) on the substrate 200; etching and removing a portion of the initial first isolation layer to form the first isolation layer 202, wherein the top surface of the first isolation layer 202 is lower than the top surface of the fin 201.

[0044] The material of the first isolation layer 202 is an insulating material, and the insulating material includes silicon oxide or silicon oxynitride. In this embodiment, the material of the first isolation layer 202 is silicon oxide.

[0045] In this embodiment, after forming the first isolation layer 202, a first gate structure spanning the fin 201 and source / drain doped regions located in the fin 201 on both sides of the first gate structure are formed on each first region I. The first gate structure covers part of the sidewall and top surface of the fin 201. Figures 6 to 12 .

[0046] Please refer to Figure 6 , it should be noted that, Figure 6 and Figure 5 The viewing direction is consistent with that of the embodiment, and a first dummy gate structure is formed on each of the first regions I; and a second dummy gate structure is formed on the second region II.

[0047] The method for forming the first dummy gate structure includes: forming a first gate dielectric layer 203 on the first isolation layer 202 ; forming a first dummy gate layer 204 on the first gate dielectric layer 203 ; and forming a first spacer 205 on the sidewall of the first dummy gate layer 204 .

[0048] In this embodiment, the material of the first gate dielectric layer 203 is silicon oxide; in other embodiments, the material of the first gate dielectric layer may also be silicon oxynitride.

[0049] In this embodiment, the material of the first dummy gate layer 204 is polysilicon.

[0050] The method for forming the second dummy gate structure includes: forming a second gate dielectric layer 206 on the first isolation layer 202 ; forming a second dummy gate layer 207 on the second gate dielectric layer 206 ; and forming a second spacer 217 on the sidewall of the second dummy gate layer 207 .

[0051] In this embodiment, the material of the second gate dielectric layer 206 is the same as that of the first gate dielectric layer 203 , and the material of the second dummy gate layer 207 is also the same as that of the first dummy gate layer 204 .

[0052] In this embodiment, the second dummy gate layer 207 and the first dummy gate layer 204 are formed simultaneously. The first dummy gate layer 204 and the second dummy gate layer 207 are formed simultaneously through a global process, which can effectively improve production efficiency.

[0053] Please continue to refer to Figure 6 After forming the first dummy gate structure and the second dummy gate structure, the source-drain doped region 208 is formed.

[0054] By forming the source / drain doped region 208 after forming the first dummy gate structure and the second dummy gate structure, the position and volume of the source / drain doped region 208 can be well controlled.

[0055] In this embodiment, after forming the source / drain doped regions 208, a second isolation layer is subsequently formed in the second region. If the source / drain doped regions 208 are formed after forming the second isolation layer, a portion of the seed layer forming the source / drain doped regions 208 will contact the second isolation layer. However, the material bonding between the seed layer and the second isolation layer is poor, resulting in gaps in the subsequently grown source / drain doped regions 208, affecting the final morphology of the source / drain doped regions 208. In this embodiment, however, the second isolation layer is formed after forming the source / drain doped regions 208, enabling the seed layer forming the source / drain doped regions 208 to bond well with the material of the fin 201, thereby ensuring that the subsequently grown source / drain doped regions 208 have a better morphology.

[0056] In this embodiment, the method for forming the source-drain doped region 208 includes: forming recesses (not shown) in the fins 201 on both sides of the first gate structure respectively, and forming the source-drain doped region 208 in the recesses using an epitaxial growth process; in other embodiments, an ion implantation process can also be used to implant source and drain ions into the fins on both sides of the first gate structure, thereby forming source-drain doped regions in the fins on both sides of the first gate structure respectively.

[0057] When the type of the semiconductor device finally formed is N-type, the material of the source / drain doped region 208 is silicon doped with source / drain ions; when the type of the semiconductor device is P-type, the material of the source / drain doped region 208 is silicon germanium doped with source / drain ions.

[0058] Please refer to Figure 7 After forming the source / drain doped regions 208 , a dielectric layer 209 is formed on the first isolation layer 202 , and the dielectric layer 209 covers the first dummy gate structure and the second dummy gate structure.

[0059] The method for forming the dielectric layer 209 includes: forming an initial dielectric layer (not shown) on the first isolation layer 202, the initial dielectric layer covering the first dummy gate structure and the second dummy gate structure; and planarizing the initial dielectric layer until the top surfaces of the first dummy gate layer 204 and the second dummy gate layer 207 are exposed, thereby forming the dielectric layer 209.

[0060] In this embodiment, the material of the dielectric layer 209 is silicon oxide; in other embodiments, the material of the dielectric layer can also be low-k dielectric material (referring to a dielectric material with a relative dielectric constant lower than 3.9) or ultra-low-k dielectric material (referring to a dielectric material with a relative dielectric constant lower than 2.5).

[0061] After forming the dielectric layer 209, a second isolation layer is formed in the second region II. The second isolation layer penetrates the fin 201 along a second direction, and the second direction is perpendicular to the first direction. For the specific formation process of the second isolation layer, please refer to Figures 8 to 11 .

[0062] Please refer to Figure 8 A stop layer 210 is formed on the dielectric layer 209 , and a stop layer opening 211 is defined in the stop layer 210 to expose the second dummy gate layer 207 .

[0063] The function of the stop layer 210 is to stop the subsequent planarization of the initial second isolation layer, and its purpose is to protect the dielectric layer 209 during the planarization process.

[0064] In this embodiment, the material of the stop layer 210 is different from that of the dielectric layer 209 . This is to reduce damage to the dielectric layer 209 when the stop layer 210 is subsequently removed. The material of the stop layer 210 is silicon nitride.

[0065] Please refer to Figure 9 , removing the second dummy gate layer 207 to form a second dummy gate opening 212 ; and etching the fin 201 exposed by the second dummy gate opening 212 to form an isolation trench 213 .

[0066] In this embodiment, the process used to remove the second dummy gate layer 207 is dry etching, and the etching gas for dry etching includes one or more of HBr, Cl2, SF6, NF3, O2, Ar, He, CH2F2 and CHF3.

[0067] The isolation trench 213 penetrates the fin along a second direction, and the second direction is perpendicular to the first direction.

[0068] Please refer to Figure 10 , performing surface treatment on the isolation trench 213 .

[0069] The straight lines with arrows in the figure represent surface treatments.

[0070] In this embodiment, the surface treatment method is a combination of surface solution treatment and surface ion implantation treatment.

[0071] In other embodiments, the surface treatment is performed by surface solution treatment or surface ion implantation treatment.

[0072] In this embodiment, the process parameters of the surface solution (SPM) treatment include: using a 1:1 mixed solution of sulfuric acid and hydrogen peroxide, a treatment time of 10 seconds to 30 seconds, and a treatment temperature of room temperature.

[0073] In this embodiment, the process parameters of the surface ion implantation treatment include: the implanted ions are boron ions, the implantation energy is less than 10 KeV, the implantation dose is 10E14 atoms / cm 2 .

[0074] In this embodiment, surface solution treatment is used to release the charges accumulated on the surface of the isolation trench 213, so that no charge accumulates on the surface of the isolation trench 213, thereby cutting off the leakage at the single diffusion cutoff (SDB) from the source.

[0075] In this embodiment, a PN junction is formed on the surface of the isolation trench 213 by surface ion implantation, thereby blocking the flow path of charges on both sides of the single diffusion region cutoff (SDB), thereby avoiding the generation of leakage at the single diffusion region cutoff (SDB).

[0076] In this embodiment, the surface of the isolation trench 213 is first subjected to a surface solution treatment (SPM) and then to a surface ion implantation treatment. This, on the one hand, prevents charge accumulation at the source and blocks the source of leakage; on the other hand, it isolates the movement path of the charge, thereby reducing the impact of single diffusion break (SDB) leakage on the ring oscillator IDDQ performance and improving the performance of the resulting semiconductor device.

[0077] Please refer to Figure 11 , forming an initial second isolation layer (not marked in the figure) in the isolation trench 213, the second dummy gate opening 212 and the stop layer opening 211; planarizing the initial second isolation layer until the top surface of the stop layer 210 is exposed to form the second isolation layer 214.

[0078] The initial second isolation layer is formed using a high-density plasma deposition process or a high-aspect-ratio deposition process. In this embodiment, the initial second isolation layer is formed using a high-density plasma deposition process. The initial second isolation layer formed using the high-density plasma deposition process has a high density and can effectively enhance the isolation effect of the subsequent second isolation layer on the adjacent source-drain doped region 208.

[0079] In this embodiment, the reaction gases of the high-density plasma deposition process include: SiH4 and O2; the flow rate of SiH4 is: 100sccm~5000sccm, the flow rate of O2 is 50sccm~2000sccm; the reaction temperature is 100℃~500℃; the pressure in the reaction chamber is 0.01Torr~200Torr.

[0080] In this embodiment, the material of the second isolation layer 214 includes silicon oxide; in other embodiments, the material of the second isolation layer 214 may also be silicon oxynitride.

[0081] In this embodiment, the process of planarizing the initial second isolation layer adopts a chemical mechanical polishing process; in other embodiments, the process of planarizing the initial second isolation layer may also adopt a dry etching process or a wet etching process.

[0082] Please refer to Figure 12 , remove the stop layer 210 and the first dummy gate layer 204 to form a first dummy gate opening (not marked); form a first gate layer 215 in the first dummy gate opening, and the first gate layer 215 is located on the first gate dielectric layer 203.

[0083] In this embodiment, the process used to remove the first dummy gate layer 204 is a dry etching process, and the gas used in the dry etching process uses a gas with a high etching ratio for polysilicon material as an etching gas, such as a gas containing HBr, O2 or Cl2 as an etching gas.

[0084] In this embodiment, the process of forming the first gate layer 215 adopts a physical vapor deposition process.

[0085] In this embodiment, the material of the first gate layer 215 is copper; in other embodiments, the material of the first gate layer may also be aluminum or tungsten.

[0086] In this embodiment, before forming the first gate layer, a high-k gate dielectric layer 216 is formed. The high-k gate dielectric layer 216 is located on the first gate dielectric layer 203 , and the first gate layer 215 is located on the high-k gate dielectric layer 216 .

[0087] In this embodiment, the material of the high-k gate dielectric layer 216 is HfO 2 ; in other embodiments, the material of the high-k gate dielectric film may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or ZrO 2 .

[0088] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Figure 12 The semiconductor structure includes: a substrate 200, wherein the substrate 200 has a fin 201, the fin 201 extends along a first direction, and the fin 201 includes a plurality of first regions I and at least one second region II, wherein the second region II is located between two adjacent first regions I, and the first region I and the second region II are arranged along the first direction; a first isolation layer 203 located on the substrate 200, the first isolation layer 203 covering a portion of the sidewalls of the fin 201, and the surface of the first isolation layer 203 is lower than the top surface of the fin 201; a first gate structure located on each of the first regions I, and a source-drain doped region 208 located in the fin 201 on both sides of the first gate structure, the first gate structure covering a portion of the sidewalls and top surface of the fin 201; an isolation trench 213 located in the second region II, the isolation trench 213 penetrating the fin along a second direction, the second direction being perpendicular to the first direction; and a second isolation layer 214 located in the isolation trench 213.

[0089] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate having a fin thereon, the fin extending along a first direction, the fin including a plurality of first regions and at least one second region, the second region being located between two adjacent first regions, and the first regions and the second regions being arranged along the first direction; forming a first isolation layer on the substrate, wherein the first isolation layer covers a portion of the sidewall of the fin, and a surface of the first isolation layer is lower than a top surface of the fin; forming a first gate structure across the fins and source / drain doped regions in the fins on both sides of the first gate structure on each of the first regions, wherein the first gate structure covers part of the sidewalls and top surface of the fins; forming an isolation trench in the second region, wherein the isolation trench layer penetrates the fin along a second direction, wherein the second direction is perpendicular to the first direction; Performing surface treatment on the surface of the isolation trench, wherein the surface treatment is a combination of surface solution treatment and surface ion implantation treatment, and forming a PN junction on the surface of the isolation trench by utilizing the surface ion implantation treatment; After surface treatment, a second isolation layer is formed in the isolation trench.

2. The method for forming a semiconductor structure according to claim 1, wherein: When the surface treatment method adopts surface solution treatment, a mixed solution of sulfuric acid and hydrogen peroxide in a ratio of 1:1 is used, the treatment time is 10 seconds to 30 seconds, and the treatment temperature is room temperature.

3. The method for forming a semiconductor structure according to claim 1, wherein: When the surface treatment is performed by surface ion implantation, the implanted ions are boron ions, the implantation energy is less than 10 KeV, and the implantation dose is 10E14 atoms / cm 2 .

4. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the first gate structure and the isolation trench, the method further includes: forming a first dummy gate structure on each of the first regions; and forming a second dummy gate structure on the second region.

5. The method for forming a semiconductor structure according to claim 4, wherein: After forming the first dummy gate structure and the second dummy gate structure and before forming the isolation trench, the source and drain doping regions are formed.

6. The method for forming a semiconductor structure according to claim 1, wherein: The process for forming the source and drain doping regions includes an epitaxial growth process.

7. The method for forming a semiconductor structure according to claim 4, wherein: After forming the source and drain doped regions, the method further includes: forming a dielectric layer on the first isolation layer, wherein the dielectric layer covers the first dummy gate structure and the second dummy gate structure.

8. The method for forming a semiconductor structure according to claim 7, wherein: The method for forming the first dummy gate structure includes: forming a first gate dielectric layer on the first isolation layer; forming a first dummy gate layer on the first gate dielectric layer; and forming a first spacer on the sidewall of the first dummy gate layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the second dummy gate structure includes: forming a second gate dielectric layer on the first isolation layer; forming a second dummy gate layer on the second gate dielectric layer; and forming a second spacer on the sidewall of the second dummy gate layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: The method for forming the isolation trench includes: removing the second dummy gate layer to form a second dummy gate opening; and etching the fin exposed by the second dummy gate opening to form the isolation trench.

11. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming the second isolation layer includes: forming a stop layer on the dielectric layer, the stop layer having a stop layer opening exposing the second pseudo gate layer, forming an initial second isolation layer in the isolation trench, the second pseudo gate opening and the stop layer opening; flattening the initial second isolation layer until the top surface of the stop layer is exposed; forming the second isolation layer; and removing the stop layer after forming the second isolation layer.

12. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the first gate structure includes: removing the first dummy gate layer to form a first dummy gate opening; and forming a first gate layer in the first dummy gate opening, wherein the first gate layer is located on the first gate dielectric layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: The first dummy gate layer is removed after the second isolation layer is formed.

14. The method for forming a semiconductor structure according to claim 7, wherein: The material of the dielectric layer includes silicon dioxide, low-k dielectric material or ultra-low-k dielectric material.

15. The method for forming a semiconductor structure according to claim 11, wherein: The material of the stop layer is different from that of the dielectric layer, and the material of the stop layer includes silicon nitride.

16. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second isolation layer includes silicon nitride or silicon oxynitride.

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