A semiconductor device and a manufacturing method thereof

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductor devices. The semiconductor device comprises a capacitor and a support structure; the capacitor comprises a lower electrode, a dielectric layer and an upper electrode; the support structure surrounds the outer wall of the lower electrode at a preset height; and a convex part is arranged at the part where the capacitor is in contact with the support structure. The support structure comprises a first material layer, a second material layer and the first material layer arranged in sequence; and a concave part is arranged at the end face where the support structure is in contact with the capacitor. The convex part is embedded in the concave part to provide stable support for the capacitor. The semiconductor device and the manufacturing method thereof disclosed by the application are used to solve the technical problem that the capacitor is prone to tilting, distortion and collapse in the prior art.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] With the rapid development of integrated circuits, the requirements for high integration of dynamic random access memory (DRAM) are becoming increasingly stringent. To ensure the capacitance of capacitors in DRAM while increasing integration density, current methods mainly include increasing the aspect ratio of the capacitors or using high-dielectric materials. However, as the aspect ratio of capacitors continues to increase, defects such as tilting, twisting, and collapse can easily occur during the removal of the molding layer and in subsequent processes. Summary of the Invention

[0003] This application provides a semiconductor device and its manufacturing method, which solves the technical problem that capacitors in the prior art are prone to tilting, twisting and collapsing. It reduces the probability of tilting, twisting and collapsing of capacitors, thereby ensuring the technical effect of capacitor capacity while maintaining the high integration of dynamic random access memory.

[0004] On the one hand, this application provides the following technical solution through one embodiment:

[0005] This application provides a semiconductor device, including a capacitor and a support structure;

[0006] The capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The support structure surrounds the outer wall of the lower electrode at a preset height. The portion of the capacitor that contacts the support structure has a protrusion.

[0007] The support structure includes a first material layer, a second material layer and the first material layer arranged in sequence, and the end face of the support structure that contacts the capacitor is provided with a recess;

[0008] The protrusion engages with the recess to provide stable support for the capacitor.

[0009] Optionally, the first material layer of the support structure is SiCN, and the second material layer is SiBN.

[0010] Optionally, the protrusion is disposed on the outer wall of the lower electrode.

[0011] Optionally, the lower electrode is trench-shaped, the dielectric layer is located on the inner and outer walls of the lower electrode, and the upper electrode is located on the dielectric layer.

[0012] Optionally, the semiconductor device is a dynamic random access memory (DRAM), and the DRAM further includes:

[0013] Semiconductor substrate;

[0014] A buried channel transistor located within the semiconductor substrate, wherein one of the source / drain regions of the transistor is in contact with a bit line, and the other source / drain region is electrically connected to the capacitor.

[0015] On the other hand, this application provides a method for manufacturing a semiconductor device, comprising:

[0016] A first molding layer, a support layer, and a second molding layer are sequentially deposited on a substrate to form a molding stack layer, wherein the support layer includes a first material layer, a second material layer, and the first material layer;

[0017] Etching the molded stacked layers to form capacitor holes;

[0018] The support layer of the capacitor hole wall is etched to form a recess on the end face of the support layer;

[0019] Electrode material is deposited within the capacitor hole to form the lower electrode;

[0020] Remove the remaining first molding layer and second molding layer;

[0021] A dielectric layer is formed on the inner and outer walls of the lower electrode, and an electrode is formed on the dielectric layer to form a capacitor.

[0022] Optionally, the step of sequentially depositing the first molding layer, the support layer, and the second molding layer on the substrate includes:

[0023] The first molding layer is deposited on the substrate;

[0024] A SiCN material layer, a SiBN material layer, and the SiCN material layer are sequentially deposited on the first molding layer to form a SiCN-SiBN-SiCN support layer.

[0025] The second molding layer is deposited on the SiCN-SiBN-SiCN support layer.

[0026] Optionally, the support layer for etching the capacitor hole wall includes:

[0027] The support layer on the capacitor hole wall is etched using a wet etching process or a gas etching technique.

[0028] Optionally, the etching of the support layer on the capacitor via wall using wet etching or gas etching technology includes:

[0029] The support layer of the capacitor orifice wall is etched using a diluted mixture of sulfuric acid and hydrogen peroxide combined with a liquid hydrogen fluoride mixture, wherein the weight percentage of hydrogen fluoride in the liquid hydrogen fluoride mixture is 50–500 PPM, maintaining the etching depth of the first material layer at less than [amount missing]. The etching depth of the second material layer is

[0030] Alternatively, an isotropic hydrogen fluoride gas etching technique can be used to etch the support layer of the capacitor hole wall, wherein the etching ratio of the first material layer to the second material layer is 1:10 to 1:100, so as to form a recess on the end face of the support layer.

[0031] Optionally, the semiconductor device is a dynamic random access memory (DRAM), and before performing the semiconductor device manufacturing method, it further includes:

[0032] Etch the substrate;

[0033] A buried channel transistor is formed within the substrate;

[0034] A bit line structure is formed in the region on the substrate that contacts one of the source and drain regions of the transistor;

[0035] A contact pad is formed on the substrate in a region that contacts one of the source and drain regions of the transistor;

[0036] The lower electrode is formed on the contact pad.

[0037] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0038] Because a support structure with a first material layer, a second material layer, and a first material layer is adopted, a recess can be formed on the end face of the support structure. On the other hand, since a protrusion is provided on the capacitor, and the recess of the support structure fits into the protrusion of the capacitor, a more stable support can be provided for the capacitor. This significantly reduces the probability of the capacitor tilting, twisting, and collapsing during the removal of the molding layer and in subsequent use, thereby improving the yield of device manufacturing and ensuring the reliability of the device during use. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the structure of the semiconductor device in the embodiments of this application;

[0041] Figure 2 In the embodiments of this application, and Figure 1 A schematic diagram of another semiconductor device with the same support structure;

[0042] Figure 3 This is a schematic diagram of the dynamic random access memory in the embodiments of this application;

[0043] Figure 4 This is a flowchart of the semiconductor device manufacturing method in the embodiments of this application;

[0044] Figures 5-9 This is a schematic diagram of the semiconductor device manufacturing process in the embodiments of this application. Detailed Implementation

[0045] This application provides a semiconductor device and its manufacturing method, which solves the technical problem in the prior art that capacitors are prone to tilting, twisting or collapsing during the removal of the molding layer and in subsequent use.

[0046] The technical solution of this application embodiment is to solve the above-mentioned technical problems, and the general idea is as follows:

[0047] A semiconductor device is provided, the device including a capacitor and a support structure;

[0048] The capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The support structure surrounds the outer wall of the lower electrode at a preset height. The portion of the capacitor that contacts the support structure has a protrusion.

[0049] The support structure includes a first material layer, a second material layer and the first material layer arranged in sequence, and the end face of the support structure that contacts the capacitor is provided with a recess;

[0050] The protrusion engages with the recess to provide stable support for the capacitor.

[0051] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0052] Firstly, this application provides a semiconductor device, such as... Figure 1 As shown, it includes:

[0053] The support structure 1100 and the capacitor 1200 are included. The support structure 1100 includes a first material layer 1101, a second material layer 1102, and a second material layer 1102 located between the two first material layers 1101. The three layers together form a three-layer support structure 1100. In specific implementation, the support structure 1100 surrounds the capacitor 1200 at a preset height. A recess 1103 is provided on the end face of the support structure 1100 that contacts the capacitor 1200, and a protrusion 1201 is provided on the part of the capacitor 1200 that contacts the support structure 1100. The recess 1103 and the protrusion 1201 of the support structure fit together to provide stable support for the capacitor 1200.

[0054] In a specific implementation, the first material layer 1101 can be SiCN, and the second material layer 1102 can be SiBN, forming a three-layer support structure of SiCN-SiBN-SiCN. Since SiCN and SiBN have different chemical and physical properties, they have different etching rates when etching the SiCN-SiBN-SiCN support structure, thus forming a recess at the end face where the support structure contacts the capacitor. Furthermore, in a specific implementation, the semiconductor device can include N support structures, where N is a natural number greater than or equal to 1. For example, in one embodiment, it can be as follows: Figure 2 The diagram shows two support structures 1100 that are in contact with each other, forming a six-layer support structure 1100 to provide more stable support for the capacitor. It should be noted that those skilled in the art can set a target number of support structures according to actual circumstances; this application does not limit the number of support structures. Furthermore, it should be explained that the embodiments of this application exemplarily show the case where the support structure is located at the longitudinal center of the capacitor, but it should be clear that the support structure can be located alone or simultaneously at any position along the longitudinal direction of the capacitor, such as the top, middle, or bottom position. This application does not limit the placement of the support structure in the semiconductor device.

[0055] In specific implementation, capacitor 1200 includes an upper electrode, a dielectric layer, and a lower electrode. Specifically, the lower electrode is trench-shaped, and the dielectric layer is located on the inner and outer walls of the lower electrode, its shape following the lower electrode and also being trench-shaped. The upper electrode is located on the dielectric layer, opposite to and parallel to the lower electrode. A protrusion 1201 of capacitor 1200 is disposed on the outer wall of the lower electrode. The lower electrode can be any material including suitable conductive components, such as various metals such as tungsten, titanium, nickel, platinum, etc., or metal nitrides such as titanium nitride, metal carbides such as tungsten carbide, etc., without limitation. As a component corresponding to the support structure, this application does not limit the number or position of the capacitor protrusions 1201, as long as they can fit into the recesses 1103 of the support structure, thus forming a stable support between the support structure 1100 and the capacitor 1200.

[0056] In specific applications, this semiconductor device can be a dynamic random access memory, such as... Figure 3 As shown, the dynamic random access memory (DRAM) includes a semiconductor substrate 301 and a buried channel transistor 302 located within the semiconductor substrate 301. One of the source / drain regions of the transistor 302 is in contact with a bit line, and the other source / drain region is electrically connected to a capacitor 303 through a storage node contact. A support structure 304 is disposed between the capacitors 303, and the concave portion of the support structure 304 engages with the convex portion of the capacitor 303, providing stable support for the capacitors 303 to reduce the probability of tilting, twisting, or collapsing during the removal of the molding layer and during subsequent use. In specific implementations, this DRAM can be applied to any electronic system, such as computers, servers, displays, cameras, set-top boxes, wireless devices, smartphones, telephones, or vehicles, etc., which contain computing or processing functions. Of course, the semiconductor device can also be a capacitor or a storage cell composed of capacitors. This application does not limit this and will not provide further examples.

[0057] Compared to existing devices of the same type, the semiconductor device described in this embodiment can significantly reduce the phenomenon of capacitor tilting, twisting, and collapse.

[0058] On the other hand, this application provides a method for manufacturing the aforementioned semiconductor device, comprising:

[0059] A first molding layer, a support layer, and a second molding layer are sequentially deposited on a substrate to form a molding stack layer, wherein the support layer includes a first material layer, a second material layer, and the first material layer;

[0060] Etching the molded stacked layers to form capacitor holes;

[0061] The support layer of the capacitor hole wall is etched to form a recess on the end face of the support layer;

[0062] Electrode material is deposited within the capacitor hole to form the lower electrode;

[0063] Remove the remaining first molding layer and second molding layer;

[0064] A dielectric layer is formed on the inner and outer walls of the lower electrode, and an electrode is formed on the dielectric layer to form a capacitor.

[0065] Below, in conjunction with Figure 4 The specific implementation steps of this formation method are described in detail below:

[0066] First, step S401 is performed, in which a first molding layer, a support layer, and a second molding layer are sequentially deposited on the substrate to form a molding stack layer. The support layer includes a first material layer, a second material layer, and the first material layer. In a specific implementation, it can be done as follows: Figure 5 As shown, a first molding layer 5210 is deposited on a substrate 5100 using methods commonly used in the semiconductor field, such as chemical vapor deposition or atomic layer deposition. Then, a first material layer 5221, a second material layer 5222, and another first material layer 5221 are sequentially deposited on the first molding layer 5210 to form a support layer 5220. The first material layer can be SiCN, and the second material layer can be SiBN. Subsequently, a second molding layer 5230 is deposited on the support layer 5220 to form a molding stack layer 5200.

[0067] Then, step S402 is performed to etch the molded stacked layer to form a capacitor hole. In specific implementations, the capacitor hole formed after etching can be cylindrical, and the cross-section of the etched device is as follows: Figure 6 As shown.

[0068] Next, step S403 is performed to etch the support layer of the capacitor hole wall, forming a recess on the end face of the support layer. In specific implementation, wet etching or gas etching techniques can be used to etch the support layer of the capacitor hole wall. Specifically, a DSP (Diluted mixture of sulfuric acid and hydrogen peroxide) combined with an HF (hydrogen fluoride) liquid mixture can be used for etching, wherein the weight percentage of HF in the HF liquid mixture is 50–500 ppm (parts per million). The entire wet etching process takes 150–600 seconds, and after etching, the amount of etching on the first material layer is less than... The etching depth of the second material is For example, for a SiCN-SiBN-SiCN support layer, the etching time using the above method is 300 seconds, and after etching, the amount of SiCN etched is... The etching depth of SiBN is Of course, in practical applications, different process parameters can be selected as needed to form a recess of the desired depth. This is not limited here, nor will any examples be given.

[0069] In an optional embodiment, isotropic hydrogen fluoride gas etching can also be used to etch the support layer of the capacitor via wall, wherein the etching ratio of the first material layer to the second material layer is 1:10 to 1:100, to form a recess of the desired depth on the end face of the support layer. Of course, in specific implementations, other methods can also be used to form the recess on the end face of the support layer; this application does not limit the method of forming the recess. After the etching of the support layer is completed, the device structure is as follows: Figure 7 As shown.

[0070] Next, step S404 is executed to deposit electrode material in the capacitor hole to form the lower electrode. In specific implementations, commonly used semiconductor processes such as atomic layer deposition (ALD) or physical vapor deposition (PVD) can be used to deposit the electrode material. In one embodiment, atomic layer deposition (ALD) can be used to deposit TiN material within the capacitor hole to form an electrode with protrusions. The protrusions of the electrode are embedded in the recesses of the support layer. After the electrode is formed, the device structure is as follows: Figure 8 As shown.

[0071] Subsequently, step S405 is executed to remove the remaining first and second molding layers. In specific implementations, a wet etching process can be used to remove the first and second molding layers, followed by drying using IPA DRY (isopropyl alcohol) to obtain the desired result. Figure 9 The device shown.

[0072] Finally, step S406 is performed to form a dielectric layer on the inner and outer walls of the lower electrode, and an electrode is formed on the dielectric layer to form a capacitor. Specifically, a dielectric layer is first formed on both the inner and outer walls of the lower electrode. The material of the dielectric layer can be an insulating oxide or an insulating nitride, such as silicon dioxide, silicon nitride, chromium oxide, and zirconium oxide, etc., which is not limited in this application. Conventional techniques such as physical vapor deposition and chemical vapor deposition can be used to form the dielectric layer, which is not limited in this application. Then, an upper electrode is formed on the dielectric layer using conventional techniques to constitute a complete capacitor. The upper electrode can be formed of a conductive material, including various conductive metals, conductive metal compounds, or conductive doped semiconductors, which is not limited in this application.

[0073] In a specific embodiment, the semiconductor device provided in this application can be a dynamic random access memory. Before performing the above-described semiconductor device fabrication method, it is necessary to first etch the substrate and form a buried channel transistor and a contact structure in the etched area. One of the source and drain regions of the buried channel transistor is connected to the capacitor through the contact structure, and the other source and drain region is connected to the bit line. The channel region of the buried transistor is connected to the word line, so as to realize the reading or writing operation of the charge stored in the capacitor.

[0074] The technical solutions described in the embodiments of this application have at least the following technical effects or advantages:

[0075] By employing a first material layer, a second material layer, and a third material layer to form the support layer, and using a DSP combined with an HF liquid mixture to etch the support layer, a recess of the desired depth can be formed on the end face of the support structure. Furthermore, because a recess is formed on the end face of the support structure, a protrusion structure can be formed at this recess location when the capacitor electrode is subsequently formed. The interlocking of the recess in the support layer with the protrusion in the capacitor provides more stable support for the capacitor, significantly reducing the probability of tilting, twisting, and collapsing of the capacitor during the removal of the molding layer and in subsequent use. This improves the device formation yield and ensures the reliability of the device during use. Simultaneously, the use of expensive supercritical carbon dioxide cleaning can be avoided, indirectly reducing manufacturing costs by increasing the strength of the support structure.

[0076] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0077] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A semiconductor device, characterized by, The capacitor comprises a lower electrode, a dielectric layer and an upper electrode, and the support structure surrounds the outer wall of the lower electrode at a preset height, and a convex part is arranged at the part where the capacitor is in contact with the support structure. The support structure comprises a first material layer, a second material layer and the first material layer arranged in sequence, and a concave part is arranged at the end face of the support structure in contact with the capacitor, the first material layer of the support structure is SiCN, the second material layer is SiBN, and a plurality of support structures are arranged at the top, middle and bottom positions of the capacitor in the longitudinal direction respectively; the convex part is embedded in the concave part to provide stable support for the capacitor. The convex part is arranged on the outer wall of the lower electrode.

2. The semiconductor device of claim 1, wherein, The lower electrode is in a groove shape, the dielectric layer is arranged on the inner wall and the outer wall of the lower electrode respectively, and the upper electrode is arranged on the dielectric layer.

3. The semiconductor device of claim 1, wherein, The semiconductor device is a dynamic random access memory, and the dynamic random access memory further comprises:

4. The semiconductor device of claim 1, wherein, a semiconductor substrate; a buried channel transistor in the semiconductor substrate, one of the source-drain regions of the transistor is in contact with a bit line, and the other source-drain region is electrically connected with the capacitor. The method comprises:

5. A method of manufacturing a semiconductor device, characterized by depositing a first molding layer, a support layer and a second molding layer on a substrate in sequence to form a molding stack layer, wherein the support layer comprises a first material layer, a second material layer and the first material layer, and a plurality of support layers are arranged at the top, middle and bottom positions of the capacitor in the longitudinal direction respectively; etching the molding stack layer to form a capacitor hole; etching the support layer of the capacitor hole wall to form a concave part at the end face of the support layer; depositing an electrode material in the capacitor hole to form a lower electrode; removing the remaining first molding layer and second molding layer; forming a dielectric layer on the inner wall and the outer wall of the lower electrode, and forming an electrode on the dielectric layer to form a capacitor; wherein the step of depositing a first molding layer, a support layer and a second molding layer on a substrate in sequence comprises: depositing the first molding layer on the substrate; depositing a SiCN material layer, a SiBN material layer and the SiCN material layer on the first molding layer in sequence to form a SiCN-SiBN-SiCN support layer; depositing the second molding layer on the SiCN-SiBN-SiCN support layer. The etching of the support layer of the capacitor hole wall comprises:

6. The method of claim 5, wherein, using a wet etching process or a gas corrosion technology to etch the support layer of the capacitor hole wall. The etching of the support layer of the capacitor hole wall using a wet etching process or a gas corrosion technology comprises:

7. The method of claim 6, wherein, using a diluted sulfuric acid and hydrogen peroxide mixture combined with a hydrogen fluoride liquid mixture to etch the support layer of the capacitor hole wall, wherein the weight percentage of hydrogen fluoride in the hydrogen fluoride liquid mixture is 50-500 PPM, and the etching amount of the first material layer is maintained to be less than 1 Å, and the etching amount of the second material layer is 10-30 Å. ​ Alternatively, the support layer of the capacitor hole wall is etched by isotropic hydrogen fluoride gas etching technology, wherein the etching selectivity ratio of the first material layer to the second material layer is 1:10-1:100, so as to form a recess on the end surface of the support layer.

8. The method of claim 5, wherein, The semiconductor device is a dynamic random access memory, and before the semiconductor device forming method is performed, the method further comprises: etching the substrate; forming a buried channel transistor in the substrate; forming a bit line structure on the substrate in a region in contact with one of the source / drain regions of the transistor; forming a contact pad on the substrate in a region in contact with one of the source / drain regions of the transistor; wherein the lower electrode is formed on the contact pad.

Images