Voltage conversion circuit with adaptive mechanism

Abstract

The present application discloses a voltage conversion circuit with an adaptive mechanism, comprising: a control branch and an output branch. The control branch comprises a first resistor and a switch circuit coupled between a second supply voltage and a control terminal. The switch circuit is coupled between the control terminal and the ground terminal, receives an input voltage from the input terminal and generates a control voltage accordingly at the control terminal. The withstand voltage P-type transistor circuit of the output branch is coupled between the second supply voltage and an output terminal generating an output voltage, and is controlled by the control voltage. The withstand voltage N-type transistor circuit of the output branch is coupled between the output terminal and the ground terminal, and is controlled by an inverted input voltage. When the input voltage is in a high state of the first power domain, the output voltage is in a high state of the second power domain. When the input voltage is in a low state of the first power domain, the output voltage is in a low state of the second power domain.

Description

Technical Field

[0001] The present invention relates to voltage conversion technology, and in particular to a voltage conversion circuit with an adaptive mechanism. Background Art

[0002] Signals need to be transmitted between different circuits or chips. However, the voltage of the power supply used by different circuits or chips may be different. To ensure that the signal is correctly transmitted between different circuits or chips, it needs to be processed by a boost or buck circuit.

[0003] However, between two different circuits or chips, the voltage of the power supply on which the former operates may be greater than that of the latter, or the voltage of the power supply on which the latter operates may be greater than that of the former. If there is no voltage conversion circuit that can process different voltage magnitude relationships at the same time, different circuits must be designed for different voltage magnitude relationships, and voltage conversion cannot be performed flexibly. Summary of the invention

[0004] In view of the problems in the prior art, an object of the present invention is to provide a voltage conversion circuit with an adaptive mechanism to improve the prior art.

[0005] The present invention includes a voltage conversion circuit with an adaptive mechanism, which is configured to convert an input voltage corresponding to a first power domain into an output voltage corresponding to a second power domain, wherein a high state of a first power domain in the first power domain corresponds to a first supply voltage, and a high state of a second power domain in the second power domain corresponds to a second supply voltage. The voltage conversion circuit includes: a control branch and an output branch. The control branch includes a first resistor and a switch circuit. The first resistor is electrically coupled between the second supply voltage and the control terminal. The switch circuit is electrically coupled between the control terminal and the ground terminal, and is configured to receive an input voltage from the input terminal, and accordingly, the control terminal generates a control voltage. The output branch includes a withstand voltage P-type transistor circuit and a withstand voltage N-type transistor circuit. The withstand voltage P-type transistor circuit is electrically coupled between the second supply voltage and the output terminal, and is controlled by the control voltage, wherein the output terminal is configured to generate an output voltage. The withstand voltage N-type transistor circuit is electrically coupled between the output terminal and the ground terminal, and is controlled by an inverting input voltage, wherein the inverting input voltage is the inversion of the input voltage. When the input voltage is in the high state of the first power domain, the inverting input voltage is in the low state of the first power domain, the control voltage is the difference between the second supply voltage and the first supply voltage when the second supply voltage is greater than the first supply voltage, and is zero when the second supply voltage is not greater than the first supply voltage, and the output voltage is in the high state of the second power domain. When the input voltage is in the low state of the first power domain, the inverting input voltage is in the high state of the first power domain, the control voltage is the second supply voltage, and the output voltage is in the low state of the second power domain.

[0006] The features, implementation and effects of the present invention are described in detail below with reference to the drawings as preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A circuit diagram showing a voltage conversion circuit with an adaptive mechanism in one embodiment of the present invention;

[0008] Figure 2 A detailed circuit diagram of a switch circuit in one embodiment of the present invention is shown;

[0009] Figure 3 A detailed circuit diagram of a switch circuit in one embodiment of the present invention is shown;

[0010] Figure 4 A circuit diagram showing a voltage conversion circuit in one embodiment of the present invention;

[0011] Figure 5 A circuit diagram of a voltage conversion circuit is shown in one embodiment of the present invention.

[0012]

Explanation of symbols

[0013] 100: Voltage conversion circuit

[0014] 110: Control branch

[0015] 120: output branch

[0016] 130: Switching circuit

[0017] 140: Withstand voltage P-type transistor circuit

[0018] 150: Withstand voltage N-type transistor circuit

[0019] 160: Inverting circuit

[0020] 200: drive branch

[0021] 210: Voltage generating branch

[0022] 220: Current Source

[0023] 300: drive branch

[0024] 310: voltage generating branch

[0025] 320: Current Source

[0026] 400: voltage conversion circuit

[0027] 410: output branch

[0028] 420: Withstand voltage P-type transistor circuit

[0029] 430: Voltage-resistant N-type transistor circuit

[0030] 440: On-voltage generating circuit

[0031] 450: Voltage Generating Current Source

[0032] 500: voltage conversion circuit

[0033] 510 1 ~510 N :Output branch

[0034] BUF: Buffer

[0035] GND: Ground terminal

[0036] IC: Control current

[0037] IG: On-voltage generates current

[0038] IS: Switching current

[0039] INV: Inverter

[0040] IVin: inverting input voltage

[0041] MN1: N-type metal oxide semiconductor transistor reverse input voltage

[0042] MN20: Diode-connected N-type MOS transistor

[0043] MN21, MN31, MN41: The first N-type metal oxide semiconductor transistor

[0044] MN22, MN32, MN42: Second N-type metal oxide semiconductor transistor

[0045] MN23: The third N-type metal oxide semiconductor transistor

[0046] MP1: P-type metal oxide semiconductor transistor

[0047] MP30: Diode-connected P-type MOS transistor

[0048] MP31, MP41: The first P-type metal oxide semiconductor transistor

[0049] MP42: The second P-type metal oxide semiconductor transistor

[0050] NC: Control terminal

[0051] NG: Voltage generating terminal

[0052] OUT: Output terminal

[0053] R1: The first resistor

[0054] R2: Second resistor

[0055] Rg: Voltage generating resistance

[0056] VB1: First conduction voltage

[0057] VB2: Second conduction voltage

[0058] VC: Control voltage

[0059] VDD1: First supply voltage

[0060] VDD2: Second supply voltage

[0061] VG: Gate voltage

[0062] Vin: Input voltage

[0063] Vout: output voltage DETAILED DESCRIPTION

[0064] An object of the present invention is to provide a voltage conversion circuit with an adaptive mechanism, which can convert the input voltage of the first power domain into the output voltage of the second power domain regardless of which of the first supply voltage of the first power domain and the second supply voltage of the second power domain is larger.

[0065] Please refer to Figure 1 . Figure 1 A circuit diagram of a voltage conversion circuit 100 with an adaptive mechanism is shown in one embodiment of the present invention.

[0066] The voltage conversion circuit 100 is configured to convert an input voltage Vin corresponding to a first power domain into an output voltage Vout corresponding to a second power domain. In one embodiment, the first power domain and the second power domain may correspond to different chips or different circuit blocks, respectively.

[0067] In the first power domain, the circuit components operate according to the first supply voltage VDD1. Therefore, the high state of the first power domain corresponds to the first supply voltage VDD1, and the low state is the ground voltage. In the second power domain, the circuit components operate according to the second supply voltage VDD2. Therefore, the high state of the second power domain corresponds to the second supply voltage VDD2, and the low state is the ground voltage. In a numerical example, the first supply voltage VDD1 is, for example, 3.3 volts, the second supply voltage VDD2 is, for example, one of 5 volts, 3.3 volts, and 1.8 volts, and the ground voltage is 0 volts.

[0068] The voltage conversion circuit 100 includes a control branch 110 and an output branch 120 .

[0069] The control branch 110 includes a first resistor R1 and a switch circuit 130. The first resistor R1 is electrically coupled between the second supply voltage VDD2 and the control terminal NC. The switch circuit 130 is electrically coupled between the control terminal NC and the ground terminal GND, and is configured to receive an input voltage Vin from the input terminal IN and generate a control voltage VC at the control terminal NC accordingly.

[0070] Please also refer to Figure 2 . Figure 2 The detailed circuit diagram of the switch circuit 130 in one embodiment of the present invention is shown. In this embodiment, the switch circuit 130 includes: a driving branch 200 and a voltage generating branch 210 .

[0071] The driving branch 200 includes a current source 220 and a diode-connected N-type metal oxide semiconductor transistor MN20 .

[0072] The current source 220 is configured to operate according to the first supply voltage VDD1 and generate a switch current IS.

[0073] The diode-connected N-type MOS transistor MN20 is electrically coupled between the current source 220 and the ground terminal GND. Since the diode-connected N-type MOS transistor MN20 is connected in a diode type, its gate and drain are electrically coupled to each other. Therefore, the gate voltage VG of the diode-connected N-type MOS transistor MN20 is the same as the voltage of its drain, which is generated according to the switch current IS. The diode-connected N-type MOS transistor MN20 is controlled by the gate voltage VG to be turned on.

[0074] The voltage generating branch 210 includes a first N-type MOSFET MN21 , a second N-type MOSFET MN22 , and a third N-type MOSFET MN23 which are connected in series between the control terminal NC and the ground terminal GND.

[0075] The gate of the first N-type MOSFET MN21 is electrically coupled to the gate of the diode-connected N-type MOSFET MN20, so the first N-type MOSFET MN21 is controlled by the gate voltage VG. The second N-type MOSFET MN22 is controlled by the input voltage Vin. The third N-type MOSFET MN23 is controlled by the first supply voltage VDD1.

[0076] In one embodiment, the transistor width-to-length ratio (W / L) of the first N-type MOS transistor MN21 is A times the transistor width-to-length ratio of the diode-connected N-type MOS transistor MN20. Therefore, the current source 220 is configured so that the magnitude of the switch current IS is the ratio of the first supply voltage VDD1 to A times the first resistance value of the first resistor R1, and can be expressed as VDD1 / (R1×A).

[0077] The output branch 120 includes a withstand voltage P-type transistor circuit 140 and a withstand voltage N-type transistor circuit 150 .

[0078] The withstand voltage P-type transistor circuit 140 is electrically coupled between the second supply voltage VDD2 and the output terminal OUT and is controlled by the control voltage VC, wherein the output terminal OUT is configured to generate an output voltage Vout. In this embodiment, the withstand voltage P-type transistor circuit 140 includes a P-type metal oxide semiconductor transistor MP1, and the P-type metal oxide semiconductor transistor MP1 is a laterally diffused metal oxide semiconductor (LDMOS) transistor.

[0079] The withstand voltage N-type transistor circuit 150 is electrically coupled between the output terminal OUT and the ground terminal GND, and is controlled by an inverting input voltage IVin, wherein the inverting input voltage IVin is the inverse of the input voltage Vin. In this embodiment, the withstand voltage N-type transistor circuit 150 includes an N-type metal oxide semiconductor transistor MN1, and the N-type metal oxide semiconductor transistor MN1 is a lateral diffused metal oxide semiconductor transistor.

[0080] In one embodiment, the voltage conversion circuit 100 may further include an inverter circuit 160. The inverter circuit 160 includes an inverter INV and optionally includes a buffer BUF connected in series with the inverter INV to receive the input voltage Vin and generate an inverted input voltage IVin.

[0081] exist Figure 1 In the figure, the number of buffers BUF is shown as one. However, in practice, the number of buffers BUF can be 0, 1, or more depending on the requirements. In more detail, since the generation of the control voltage VC needs to be processed by the switch circuit 130, the number of buffers BUF can make the time for the withstand voltage P-type transistor circuit 140 to receive the control voltage VC and the time for the withstand voltage N-type transistor circuit 150 to receive the inverting input voltage Vin substantially equal.

[0082] It should be noted that the term “substantially equal” means that the time when the withstand voltage P-type transistor circuit 140 receives the control voltage VC and the time when the withstand voltage N-type transistor circuit 150 receives the inverting input voltage Vin are not necessarily completely equal, but may have an error within a reasonable range.

[0083] The operation of the voltage conversion circuit 100 will be described in more detail below according to different input voltages Vin.

[0084] In the first working condition, the input voltage Vin is in the first power domain high state (VDD1). Figure 1In the figure, the voltage conversion circuit 100 is numbered “(1)” to indicate the voltage of each circuit node in the first working condition.

[0085] Since the input voltage Vin is in the first power domain high state (VDD1), the inverting input voltage IVin will be in the first power domain low state (0). At this time, the withstand voltage N-type transistor circuit 150 will be turned off due to the control of the inverting input voltage Vin.

[0086] For the switch circuit 130, when the input voltage Vin is in the first power domain high state (VDD1), Figure 2 The second N-type MOSFET MN22 will be controlled by the input voltage Vin to be turned on, and the first N-type MOSFET MN21 and the third N-type MOSFET MN23 will also be turned on. Due to the multiple relationship between the width and length of the first N-type MOSFET MN21 and the diode-connected N-type MOSFET MN20, the control current IC flowing through the voltage generating branch 210 will be VDD1 / R1.

[0087] Therefore, when the control current IC flows through Figure 1 When the first resistor R1 is connected to the control terminal NC, the maximum voltage drop of VDD1 will be (R1×VDD1 / R1). If the second supply voltage VDD2 is greater than the first supply voltage VDD1, the control voltage VC generated by the control terminal NC will be VDD2-VDD1. If the second supply voltage VDD2 is not greater than the first supply voltage VDD1, since the ground voltage of the ground terminal GND is 0, the control voltage VC can only reach 0 at the lowest.

[0088] Therefore, after receiving the input voltage Vin of the first power domain high state (VDD1), the switch circuit 130 will make the control voltage VC the difference (VDD2-VDD1) between the second supply voltage VDD2 and the first supply voltage VDD1 when the second supply voltage VDD2 is greater than the first supply voltage VDD1, and zero when the second supply voltage VDD2 is not greater than the first supply voltage VDD1. At this time, the withstand voltage P-type transistor circuit 140 will be turned on due to the control of the control voltage VC.

[0089] Under such a condition, the output terminal OUT will receive the injection of current according to the second supply voltage VDD2 due to the conduction of the voltage-resistant P-type transistor circuit 140, and accumulate charge according to the injected current due to the closing of the voltage-resistant N-type transistor circuit 150, thereby causing the output voltage Vout to rise to the second power domain high state (VDD2).

[0090] In the second working condition, the input voltage Vin is in the first power domain low state (0). Figure 1 In the figure, the voltage conversion circuit 100 is labeled with the number "(2)" to indicate the voltage of each circuit node in the second working condition.

[0091] Since the input voltage Vin is in the first power domain low state (0), the inverting input voltage IVin will be in the first power domain high state (VDD1). At this time, the withstand voltage N-type transistor circuit 150 will be turned on due to the control of the inverting input voltage Vin.

[0092] For the switch circuit 130, when the input voltage Vin is in the first power domain low state (0), the second N-type metal oxide semiconductor transistor MN22 will be controlled by the input voltage Vin and turned off, and the first N-type metal oxide semiconductor transistor MN21 and the third N-type metal oxide semiconductor transistor MN23 will also be turned off. The control current IC will continue to charge the control terminal NC, so that the control voltage VC generated by the control terminal NC is VDD2.

[0093] Therefore, after receiving the input voltage Vin of the first power domain low state (0), the switch circuit 130 will make the control voltage VC the second supply voltage (VDD2). At this time, the withstand voltage P-type transistor circuit 140 will be turned off due to the control of the control voltage VC.

[0094] In this case, the output terminal OUT stops receiving current injection due to the shutdown of the withstand voltage P-type transistor circuit 140, and charges are lost due to the conduction of the withstand voltage N-type transistor circuit 150, thereby causing the output voltage Vout to drop to the second power domain low state (0).

[0095] Therefore, the voltage conversion circuit 100 can convert the input voltage Vin of the first power domain into the output voltage Vout of the second power domain no matter the first supply voltage VDD1 of the first power domain is greater than the second supply voltage VDD2 of the second power domain or the first supply voltage VDD1 is less than the second supply voltage VDD2.

[0096] Furthermore, by using lateral diffusion MOS transistors, the source and drain of the P-type MOS transistor MP1 and the N-type MOS transistor MN1 can withstand high voltage. The voltage difference between the gate and source of the P-type MOS transistor MP1 and the N-type MOS transistor MN1 can also be less than the first supply voltage VDD1 corresponding to the high state in the first power domain due to the control voltage VC and the inverting input voltage IVin respectively received by the gate. Each component can thus be protected from damage due to excessive voltage difference.

[0097] Please refer to Figure 3 . Figure 3 The detailed circuit diagram of the switch circuit 130 in another embodiment of the present invention is shown. In this embodiment, the switch circuit 130 includes a driving branch 300 and a voltage generating branch 310 .

[0098] The driving branch 300 includes a current source 320 , a second resistor R2 , and a diode-connected P-type metal oxide semiconductor transistor MP30 .

[0099] The current source 320 is configured to generate a switch current IS to the ground terminal GND.

[0100] The second resistor R2 has a second resistance value that is B times the first resistance value of the first resistor R1 , which can be expressed as B× R1 . A first end of the second resistor R2 is electrically coupled to the second supply voltage VDD2 .

[0101] The diode-connected P-type metal oxide semiconductor transistor MP30 is electrically coupled between the second end of the second resistor R2 and the current source 320 , and is configured to be turned on under the control of the gate voltage VG generated according to the switch current IS.

[0102] The voltage generating branch 310 includes a first N-type MOS transistor MN31 , a first P-type MOS transistor MP31 , and a second N-type MOS transistor MN32 which are connected in series between the control terminal NC and the ground terminal GND.

[0103] The first N-type MOSFET MN31 is controlled by the input voltage Vin. The gate of the first P-type MOSFET MP31 is electrically coupled to the gate of the diode-connected P-type MOSFET MP30 and is therefore controlled by the gate voltage VG. The second N-type MOSFET MN32 is controlled by the first supply voltage VDD1.

[0104] In one embodiment, the transistor width-to-length ratio of the first P-type metal oxide semiconductor transistor MP31 is B times the transistor width-to-length ratio of the diode-connected P-type metal oxide semiconductor transistor MP30. Therefore, the current source 320 is configured so that the magnitude of the switch current IS is the ratio between the first supply voltage VDD1 and the second resistance value of the second resistor R2, and can be expressed as VDD1 / R2.

[0105] Therefore, when the input voltage Vin is in the first power domain high state (VDD1), the first N-type MOS transistor MN31 will be controlled by the input voltage Vin and turned on, and the first P-type MOS transistor MP31 and the second N-type MOS transistor MN32 will also be turned on. Due to the multiple relationship between the width and length of the first P-type MOS transistor MP31 and the diode-connected P-type MOS transistor MP30, the control current IC flowing through the voltage generating branch 310 will be B×(VDD1 / R2)=VDD1 / R1.

[0106] Therefore, when the control current IC flows through Figure 1When the first resistor R1 is connected to the control terminal NC, the maximum voltage drop of VDD1 will be (R1×(VDD1 / R1)). If the second supply voltage VDD2 is greater than the first supply voltage VDD1, the control voltage VC generated by the control terminal NC will be VDD2-VDD1. If the second supply voltage VDD2 is not greater than the first supply voltage VDD1, since the ground voltage of the ground terminal GND is 0, the control voltage VC can only reach 0 at the lowest.

[0107] When the input voltage Vin is in the first power domain low state (0), the first N-type MOSFET MN31 will be controlled by the input voltage Vin and turned off, and the first P-type MOSFET MP31 and the second N-type MOSFET MN32 will also be turned off. The control current IC will continue to charge the control terminal NC, so that the control voltage VC generated by the control terminal NC is VDD2.

[0108] Therefore, after receiving the input voltage Vin of the first power domain low state (0), the switch circuit 130 will make the control voltage VC the second supply voltage (VDD2).

[0109] In summary, Figure 3 The switch circuit 130 generates a control voltage VC and a control voltage VC when the input voltage Vin is in the first power domain high state or the first power domain low state. Figure 2 The control voltage VC generated by the switch circuit 130 is the same.

[0110] Please refer to Figure 4 . Figure 4 A circuit diagram of a voltage conversion circuit 400 is shown in one embodiment of the present invention. Figure 4 The voltage conversion circuit 400 includes Figure 1 Therefore, the structure and working mode of the same components are not described in detail.

[0111] In this embodiment, the voltage conversion circuit 400 includes an output branch 410 , which includes a withstand voltage P-type transistor circuit 420 and a withstand voltage N-type transistor circuit 430 .

[0112] The withstand voltage P-type transistor circuit 420 includes a first P-type metal oxide semiconductor transistor MP41 and a second P-type metal oxide semiconductor transistor MP42 connected in series. The first P-type metal oxide semiconductor transistor MP41 is controlled by a control voltage VC and operates in the same manner as Figure 1 The P-type metal oxide semiconductor transistor MP1 in is the same as that in the embodiment, so it will not be described in detail.

[0113] The second P-type metal oxide semiconductor transistor MP42 is controlled by the first conduction voltage VB1 to be normally on. In one embodiment, the voltage conversion circuit 400 further includes a conduction voltage generating circuit 440 configured to generate the first conduction voltage VB1.

[0114] The on-state voltage generating circuit 440 includes a voltage generating resistor Rg and a voltage generating current source 450. The voltage generating resistor Rg is electrically coupled between the second supply voltage VDD2 and the voltage generating terminal NG. The voltage generating current source 450 is electrically coupled between the voltage generating terminal NG and the ground terminal GND and is configured to generate an on-state voltage generating current IG.

[0115] In one embodiment, the magnitude of the on-voltage generating current IG is the ratio (VDD1 / Rg) between the first supply voltage VDD1 and the resistance of the voltage generating resistor Rg, so as to generate the first on-voltage VB1 at the voltage generating terminal NG. Therefore, the first on-voltage VB1 is the difference between the second supply voltage VDD2 and the first supply voltage VDD1 when the second supply voltage VDD2 is greater than the first supply voltage VDD1, and is zero when the second supply voltage VDD2 is not greater than the first supply voltage VDD1, so that the second P-type metal oxide semiconductor transistor MP42 is maintained in a normally on state.

[0116] The withstand voltage N-type transistor circuit 430 includes a first N-type metal oxide semiconductor transistor MN41 and a second N-type metal oxide semiconductor transistor MN42 connected in series. The first N-type metal oxide semiconductor transistor MN41 is controlled by the inverting input voltage IVin and operates in the same manner as Figure 1 The N-type metal oxide semiconductor transistor MN1 in is the same as that in the embodiment, so it will not be described in detail.

[0117] The second N-type MOSFET MN42 is controlled by the second conduction voltage VB2 to be normally on. In one embodiment, the second conduction voltage VB2 is the first supply voltage VDD1, so that the second N-type MOSFET MN42 is normally on.

[0118] Therefore, in this embodiment, the control branch 110, the first P-type metal oxide semiconductor transistor MP41 and the first N-type metal oxide semiconductor transistor MN41 actually work in the same manner as Figure 1 However, due to the configuration of the second P-type MOS transistor MP42 and the second N-type MOS transistor MN42, the first P-type MOS transistor MP41 and the first N-type MOS transistor MN41 can be implemented by MOS transistors with a general withstand voltage, without the need to be implemented by lateral diffused MOS transistors.

[0119] Please refer to Figure 5 . Figure 5 A circuit diagram of a voltage conversion circuit 500 is shown in one embodiment of the present invention. Figure 5 The voltage conversion circuit 500 includes Figure 1 Therefore, the structure and working mode of the same components are not described in detail.

[0120] In this embodiment, the voltage conversion circuit 500 includes output branches 5101-510N, each of which includes Figure 4 The illustrated voltage-resistant P-type transistor circuit 420 and the voltage-resistant N-type transistor circuit 430. Figure 5 The working mode of the control branch 110 and the output branch 5101 is similar to Figure 4 The voltage conversion circuit 400 shown is the same.

[0121] However, in the output branches 5102-510N, the first P-type metal oxide semiconductor transistor MP41 in each withstand voltage P-type transistor circuit 420 is controlled by the voltage of the node where the first P-type metal oxide semiconductor transistor MP41 and the second P-type metal oxide semiconductor transistor MP42 of the previous output branch are electrically coupled. The second P-type metal oxide semiconductor transistor MP42 in each withstand voltage P-type transistor circuit 420 is controlled by the first conduction voltage VB1 to be normally turned on.

[0122] On the other hand, the first N-type MOS transistor MN41 in each withstand voltage N-type transistor circuit 430 is controlled by the voltage of the node where the first N-type MOS transistor MN41 and the second N-type MOS transistor MN42 of the previous output branch are electrically coupled. The second N-type MOS transistor MN42 in each withstand voltage N-type transistor circuit 430 is controlled by the second conduction voltage VB2 to be normally on.

[0123] A node where the second P-type MOSFET MP42 and the second N-type MOSFET MN42 of the output branch 510N are electrically coupled is used as the output terminal OUT and configured to generate an output voltage Vout.

[0124] In one embodiment, when the input voltage Vin is high, each MOS transistor of the output branch needs a larger transistor width-to-length ratio. To reduce power consumption and increase speed, the voltage conversion circuit 500 can connect multiple output branches 5102-510N in series and gradually increase the transistor width-to-length ratio of the MOS transistor of each output branch 5102-510N.

[0125] It should be noted that the above implementation is only an example. In other embodiments, those skilled in the art can make changes without violating the spirit of the present invention. It should be understood that the steps mentioned in the above implementation, except for those whose order is specifically described, can be adjusted according to actual needs, and can even be executed simultaneously or partially simultaneously.

[0126] In summary, the voltage conversion circuit with adaptive mechanism in the present invention can be configured to convert the input voltage of the first power domain into the output voltage of the second power domain regardless of which of the first supply voltage of the first power domain and the second supply voltage of the second power domain is larger.

[0127] Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. A person having ordinary knowledge in the technical field may make changes to the technical features of the present invention according to the explicit or implicit contents of the present invention. All these changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be subject to the scope of the patent application defined in this specification.

Claims

1. A voltage conversion circuit with an adaptive mechanism, characterized in that: The voltage conversion circuit is configured to convert an input voltage corresponding to a first power domain into an output voltage corresponding to a second power domain, wherein a first power domain high state in the first power domain corresponds to a first supply voltage, and a second power domain high state in the second power domain corresponds to a second supply voltage, the voltage conversion circuit comprising: A control branch, comprising: a first resistor electrically coupled between the second supply voltage and a control terminal; and a switch circuit, electrically coupled between the control terminal and a ground terminal, configured to receive the input voltage from an input terminal and accordingly cause the control terminal to generate a control voltage; An output branch, comprising: a voltage-resistant P-type transistor circuit electrically coupled between the second supply voltage and an output terminal and controlled by the control voltage, wherein the output terminal is configured to generate the output voltage; as well as A withstand voltage N-type transistor circuit is electrically coupled between the output terminal and the ground terminal and is controlled by an inverting input voltage, wherein the inverting input voltage is an inverse of the input voltage; wherein when the input voltage is in a first power domain high state, the inverting input voltage is in a first power domain low state, the control voltage is the difference between the second supply voltage and the first supply voltage when the second supply voltage is greater than the first supply voltage, and is zero when the second supply voltage is not greater than the first supply voltage, and the output voltage is in a second power domain high state; When the input voltage is in a first power domain low state, the inverting input voltage is in the first power domain high state, the control voltage is the second supply voltage, and the output voltage is in a second power domain low state.

2. The voltage conversion circuit according to claim 1, characterized in that: When the input voltage is in the high state of the first power domain, the inverted input voltage turns off the withstand voltage N-type transistor circuit, and the control voltage turns on the withstand voltage P-type transistor circuit; as well as When the input voltage is in the low state of the first power domain, the inverting input voltage turns on the withstand voltage N-type transistor circuit, and the control voltage turns off the withstand voltage P-type transistor circuit.

3. The voltage conversion circuit according to claim 1, wherein: The voltage-resistant P-type transistor circuit includes a P-type metal oxide semiconductor transistor, and the voltage-resistant N-type transistor circuit includes an N-type metal oxide semiconductor transistor. The P-type metal oxide semiconductor transistor and the N-type metal oxide semiconductor transistor are respectively a laterally diffused metal oxide semiconductor LDMOS transistor.

4. The voltage conversion circuit according to claim 1, wherein: The withstand voltage P-type transistor circuit comprises a first P-type metal oxide semiconductor transistor and a second P-type metal oxide semiconductor transistor connected in series, wherein the first P-type metal oxide semiconductor transistor is controlled by the control voltage, the second P-type metal oxide semiconductor transistor is controlled by a first on-voltage to be normally on, and the first on-voltage is the difference between the second supply voltage and the first supply voltage when the second supply voltage is greater than the first supply voltage, and is zero when the second supply voltage is not greater than the first supply voltage; and The voltage-resistant N-type transistor circuit includes a first N-type metal oxide semiconductor transistor and a second N-type metal oxide semiconductor transistor connected in series, wherein the first N-type metal oxide semiconductor transistor is controlled by the inverting input voltage, and the second N-type metal oxide semiconductor transistor is controlled by a second on-state voltage to be normally on, and the second on-state voltage is the first supply voltage.

5. The voltage conversion circuit according to claim 4, characterized in that: Also includes a conduction voltage generating circuit, including: a voltage generating resistor electrically coupled between the second supply voltage and a voltage generating terminal; and a voltage generating current source electrically coupled between the voltage generating terminal and the ground terminal and configured to generate a conduction voltage generating current; The magnitude of the conduction voltage generating current is a ratio of the first supply voltage to a resistance value of the voltage generating resistor, so as to generate the first conduction voltage at the voltage generating end.

6. The voltage conversion circuit according to claim 1, wherein: The switching circuit comprises: A driving branch, comprising: a current source configured to operate according to the first supply voltage and generate a switching current; and a diode-connected N-type metal oxide semiconductor transistor, electrically coupled between the current source and the ground terminal, and configured to be turned on by being controlled by a gate voltage generated according to the switch current; as well as a voltage generating branch, comprising a first N-type metal oxide semiconductor transistor, a second N-type metal oxide semiconductor transistor and a third N-type metal oxide semiconductor transistor connected in series between the control terminal and the ground terminal, wherein the first N-type metal oxide semiconductor transistor is controlled by the gate voltage, the second N-type metal oxide semiconductor transistor is controlled by the input voltage, and the third N-type metal oxide semiconductor transistor is controlled by the first supply voltage; The transistor width-to-length ratio of the first N-type metal oxide semiconductor transistor is A times the transistor width-to-length of the diode-connected N-type metal oxide semiconductor transistor, and the magnitude of the switching current is the ratio of the first supply voltage to A times a first resistance value of the first resistor.

7. The voltage conversion circuit according to claim 1, wherein: The switching circuit comprises: A driving branch, comprising: a current source configured to generate a switching current to the ground terminal; a second resistor having a second resistance value B times a first resistance value of the first resistor, and a first end of the second resistor being electrically coupled to the second supply voltage; as well as a diode-connected P-type metal oxide semiconductor transistor, electrically coupled between a second end of the second resistor and the current source, and configured to be turned on by being controlled by a gate voltage generated according to the switch current; as well as a voltage generating branch, comprising a first N-type MOS transistor, a first P-type MOS transistor and a second N-type MOS transistor connected in series between the control terminal and the ground terminal, wherein the first N-type MOS transistor is controlled by the input voltage, the first P-type MOS transistor is turned on by the gate voltage, and the second N-type MOS transistor is turned on by the first supply voltage; The transistor width-to-length ratio of the first P-type metal oxide semiconductor transistor is B times the transistor width-to-length of the diode-connected P-type metal oxide semiconductor transistor, and the magnitude of the switching current is the ratio between the first supply voltage and the second resistance value of the second resistor.

8. The voltage conversion circuit according to claim 1, characterized in that: Also includes: an inverting circuit, comprising an inverter and optionally at least one buffer connected in series with the inverter to receive the input voltage and generate the inverted input voltage; The number of the buffers enables the time for the withstand voltage P-type transistor circuit to receive the control voltage and the time for the withstand voltage N-type transistor circuit to receive the inverted input voltage to be substantially equal.

9. The voltage conversion circuit according to claim 1, wherein: The number of the output branches is more than one.

10. The voltage conversion circuit according to claim 1, wherein: The first supply voltage is 3.3V, and the second supply voltage is one of 5V, 3.3V, and 1.8V.

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