Reset pulse width adjustable timer circuit and driver

Abstract

The application discloses a reset pulse width adjustable Timer circuit and a driver, and realizes an effective method for adjusting the reset pulse width based on a CMOS process technology.The reset pulse width adjustable Timer circuit comprises a state indication module, a current source module, a charge and discharge module and a comparator module for realizing the adjustable pulse width.The source voltage comparison circuit can effectively determine the end time of the reset signal pulse by the comparison result of the comparison voltage and the threshold value of the Timer, so that the pulse width of the reset signal is adjustable, the precision of the Timer timing and resetting is greatly improved, the problem that the Timer may be abnormally stopped and the abnormal situation may be missed due to the fixed pulse width of the reset signal of the traditional Timer structure after the timing period is accumulated is solved, and the reliability and stability of the synchronous rectification driver in the isolated DC / DC power supply are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of circuit design, and particularly relates to a Timer circuit with adjustable reset pulse width and a driver. BACKGROUND

[0002] The driver is an important component in an isolated DC / DC switching power supply, receives a pulse synchronization signal of a PWM controller, and outputs a signal for driving and controlling a switching tube and a freewheeling tube. A timer (Timer) applied in the driver is a circuit for detecting whether the synchronization pulse signal is correct. When the synchronization signal (SYNC) is correct, a logic part in the driver periodically transmits a reset signal to the Timer; when the synchronization signal (SYNC) is incorrect or has a value lower than a requirement, the logic part in the driver stops outputting the reset signal, the Timer appears in a timeout state, and then indicates the driver to shut down.

[0003] Generally, the reset signal of the Timer is a narrow pulse signal with a fixed width, and if the width is not set properly, many problems will occur with the accumulation of the synchronization signal period. When the reset pulse width is less than an ideal pulse width, an internal leakage tube cannot make a capacitor outside an input port of the Timer fully discharge. After repeated cycles, with the continuous accumulation of charge difference, the voltage value of the capacitor of the input port also continuously increases. Even if the synchronization signal is not abnormal, the driver will be mistakenly shut down when the voltage value of the capacitor reaches a timeout threshold. When the reset pulse width is greater than the ideal pulse width, there is a certain time interval between the time point at which the capacitor discharges and the time point at which the capacitor starts to charge. When the synchronization signal is abnormal, the driver cannot be timely reported and shut down, and finally, the detection is missed. SUMMARY

[0004] The application provides a Timer circuit with adjustable reset pulse width and a driver, which can effectively make the pulse end time of the reset signal Reset determined by the comparison result of the comparison voltage of the Timer and the threshold value, and realize adjustable pulse width of the reset signal.

[0005] To achieve the above object, the reset pulse width adjustable Timer circuit comprises a state indicating module, a charging and discharging module and a comparator module; the state indicating module comprises a source voltage comparison circuit and a first inverter, the source voltage comparison circuit comprises transistors MN1, MN2, MN3, MN4 and a resistor R1, the first inverter comprises MN5 and a transistor MP7; the gate and the drain of the transistor MN1 are connected to node a, and the source is connected to node b; the drain of the transistor MN2 is connected to node d, the gate is connected to node a, and the source is connected to the drain of the transistor MN4; the drain and the gate of the transistor MN3 are connected to node b, and the source is connected to the first end of the resistor R1; the gate of the transistor MN4 is connected to node b, the source is connected to node c, and node c is connected to the input voltage V of the Timer TIMER ; the second end of the resistor R1 is grounded; the gate of the transistor MP7 is connected to node d, the source is connected to node e, and the drain is connected to the output V OUT2 ; node e is connected to the power supply voltage; the gate of the transistor MN5 is connected to node d, the drain is connected to the output V OUT2 , and the source is grounded; the comparator module is used for comparing the size of the input voltage V TIMER and the timeout threshold voltage, and outputting a high level or low level signal according to the comparison result; the charging and discharging module is used for providing the input voltage V TIMER for the state indicating module and the comparator module.

[0006] Further, the charging and discharging module comprises a resistor R2, a capacitor C1 and a transistor MN15; the first end of the resistor R2 is connected to the power supply voltage VCC, and the second end is connected to the first end of the capacitor C1; the second end of the capacitor C1 is grounded; the source of the transistor MN15 is connected to the ground, the drain is connected to node c, and the gate is connected to the input signal Reset; the second end of the resistor R2 and the first end of the capacitor C1 are connected to the input signal V TIMER .

[0007] Further, the drain of the transistor MN15 is connected to the negative electrode of a diode DZ, the drain is connected to the positive electrode of the diode DZ, and the positive electrode of the diode DZ is connected to the ground.

[0008] Further, the comparator module comprises transistors MP8, MP9, MN7, MN8, MN10, MP10 and MN12; the gate of transistor MP8 is connected with node c, the source is connected with node f, and the drain is connected with node g; the gate of transistor MN7 is connected with node g, the source is connected with ground, and the drain is connected with node g; the gate of transistor MP9 is connected with the timeout threshold voltage, the source is connected with node f, and the drain is connected with node j; the gate of transistor MN8 is connected with node g, the drain is connected with the drain of transistor MP9, and the source is connected with ground; the gate of transistor MN10 is connected with node j, the drain is connected with node h, and the source is connected with ground; the gate of transistor MP10 is connected with node h, the source is connected with node e, and the drain is connected with output V OUT1 ; the gate of transistor MN12 is connected with node h, the drain is connected with output V OUT1 , and the source is connected with ground; node e is connected with the power voltage VCC.

[0009] Further, the current source module for providing voltage for the state indication module, the charge and discharge module and the comparator module is further included.

[0010] Further, the current source module comprises transistors MP1, MP2, MP3, MP4 and MP5; the source of transistor MP1 is connected with node e, the gate is connected with the input signal Vg, and the drain is connected with the input signal Vg; the source of transistor MP2 is connected with node e, the gate is connected with the input signal Vg, and the drain is connected with node a; the source of transistor MP3 is connected with node e, the gate is connected with the input signal Vg, and the drain is connected with node d; the source of transistor MP4 is connected with node e, the gate is connected with the input signal Vg, and the drain is connected with node f; the source of transistor MP5 is connected with node e, the gate is connected with the input signal Vg, and the drain is connected with node h; the gate of transistor MP1 is connected with the reference voltage Vg, and the gates of transistors MP2, MP3, MP4 and MP5 are connected with the input signal Vg.

[0011] Further, the resistance R1 is an adjustable resistance.

[0012] A driver comprising the reset pulse width adjustable Timer circuit.

[0013] Compared with the prior art, the present application has at least the following beneficial technical effects:

[0014] The state indication module in the present application compares the input signal V TIMER with the threshold value of the source voltage, and when the rising edge of the Reset reset signal comes, V TIMERThe low level output by the state indicating module affects the logic part of the driver to generate the falling edge of the reset reset signal when the voltage drops below the threshold value, so as to finally realize the adjustable reset pulse width. The source voltage comparison circuit can effectively determine the end time of the reset signal pulse by the comparison result of the comparison voltage of the Timer and the threshold value, so as to realize the adjustable pulse width of the reset signal of the reset, and greatly improve the accuracy of the Timer timing and resetting. The problem of the traditional Timer structure using the fixed pulse width of the reset signal, which may cause the Timer to be stopped and abnormal situation to be detected after the timing period is accumulated.

[0015] Further, since the resistance R1 is connected, the threshold value of the voltage comparison of the state indicating module is adjustable. On the one hand, the flexibility of the charging and discharging speed setting of the Timer circuit is increased; on the other hand, the discharging capacity of the leakage tube MN15 of the charging and discharging module is ensured, and the capacitor C1 will not become 0V due to the leakage charge, avoiding the V TIMER The curve has a long tail during the falling, which affects the response speed of the timer circuit.

[0016] The driver has the adjustable pulse width of the reset signal of the Timer circuit, which avoids the situation that the driver cannot be timely reported and stopped, and avoids the missed detection. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 The figure is a system block diagram of the driver.

[0018] Figure 2 The figure is a specific circuit diagram of the Timer. DETAILED DESCRIPTION

[0019] In order to make the purpose and technical scheme of the present application more clear and convenient to understand. The present application is further described in detail in combination with the drawings and examples, and the specific examples described herein are only used to explain the present application, and are not used to limit the present application.

[0020] In the description of the present application, it needs to be understood that the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, which are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features referred to. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more. In the description of the present application, it needs to be explained that, unless otherwise specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, or the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0021] The present application is an effective method for realizing reset pulse width adjustment based on CMOS process technology, which can be applied in synchronous rectifier driver, solves the problem of possible false shutdown and abnormal situation of missing detection of Timer after timing period accumulation caused by traditional use of fixed pulse width Reset reset signal, and improves the reliability and stability of synchronous rectifier driver in isolated DC / DC power supply.

[0022] Figure 1 The circuit block diagram of a typical synchronous rectifier gate driver, which includes: logic circuit (Logic), timer (Timer), protection circuit, gate circuit (logic "and") and drive circuit, and the gate circuit is an AND gate.

[0023] The logic circuit mainly converts the synchronous signal (SYNC signal) accepted by the driver into the pulse signal required by the power switch tube and the freewheeling tube of the next stage of the driver. The drive circuit amplifies the signal to finally improve the current capacity of the output end. The protection circuit generally has under-voltage lock, current sampling and over-temperature protection circuits. The main function of Timer is to detect whether the SYNC signal is abnormal. If the SYNC signal is normal, Logic will send a periodic Reset signal to Timer to reset the Timer; if the SYNC is abnormal, Logic does not send the Reset signal, and Timer will have a timeout phenomenon, and its output VOUT1 The Logic will be fed back through the logical AND gate, and the whole driver will be shut down. The Reset signal sent by the Logic has a fixed pulse width, and there will be deviations from the ideal value. With the accumulation of working periods, there will be missed detection and false detection, which reduces the reliability and accuracy of the driver.

[0024] The output end of the logic circuit is connected with the input end of the driving circuit, the Reset signal sending end of the logic circuit is connected with the signal input end of the timer, and the output end V OUT1 of the timer is connected with the input end of the AND gate circuit. OUT2 One input end of the logic circuit is connected with the output end of the protection circuit, and the other input end of the logic circuit is connected with the output end of the AND gate circuit; the output end of the logic circuit is connected with the signal feedback input end of the logic circuit.

[0025] Embodiment 1

[0026] The present application provides a Timer circuit with adjustable reset pulse width, which makes up for the shortcomings of the traditional circuit, and the specific circuit is shown in the figure. Figure 2 The Timer circuit is composed of four modules, which are a state indication module for realizing adjustable pulse width, a current source module, a charging and discharging module and a comparator module.

[0027] The state indication module is composed of a source voltage comparison circuit and a first inverter, and the source voltage comparison circuit is composed of transistors MN1, MN2, MN3, MN4 and a resistor R1; the first inverter is composed of MN5 and transistor MP7. The gate and drain of transistor MN1 are connected with node a, and the source is connected with node b. The drain of transistor MN2 is connected with node d, the gate is connected with node a, and the source is connected with the drain of transistor MN4; the drain and gate of transistor MN3 are connected with node b, and the source is connected with the first end of resistor R1. The gate of transistor MN4 is connected with node b, the source is connected with node c, and node c is connected with the input voltage V TIMER of the Timer; the second end of resistor R1 is grounded (gnd). The gate of transistor MP7 is connected with node d, the source is connected with node e, and the drain is connected with output V OUT2 ; the gate of transistor MN5 is connected with node d, the drain is connected with output V OUT2 , and the source is grounded.

[0028] The current source module is composed of five transistors, i.e. transistor MP1, transistor MP2, transistor MP3, transistor MP4 and transistor MP5. The source of transistor MP1 is connected to node e, the gate is connected to input signal Vg and the drain is connected to input signal Vg; the source of transistor MP2 is connected to node e, the gate is connected to input signal Vg and the drain is connected to node a; the source of transistor MP3 is connected to node e, the gate is connected to input signal Vg and the drain is connected to node d; the source of transistor MP4 is connected to node e, the gate is connected to input signal Vg and the drain is connected to node f; the source of transistor MP5 is connected to node e, the gate is connected to input signal Vg and the drain is connected to node h. The transistors MP1, MP2, MP3, MP4 and MP5 constitute a current mirror structure. The gate of transistor MP1 is connected to reference voltage Vg, the gates of transistors MP2, MP3, MP4 and MP5 are connected to the mirror current of transistor MP1, which provides reference current for transistors MN1 and MN3, transistors MN2 and MN4, transistors MP8, MP9, MN7 and MN8, and transistor MN10, respectively.

[0029] The charge-discharge module is composed of four devices, i.e. resistor R2, capacitor C1, transistor MN15 and diode DZ. The first end of resistor R2 is connected to power supply voltage VCC, the second end is connected to the first end of capacitor C1; the second end of capacitor C1 is connected to ground; the source of transistor MN15 is connected to ground, the drain is connected to node c and the gate is connected to input signal Reset; the negative electrode of diode DZ is connected to node c and the positive electrode is connected to ground. The second end of resistor R2 and the first end of capacitor C1 are connected to input signal V TIMER .

[0030] The comparator module is composed of seven devices, including transistor MP8, transistor MP9, transistor MN7, transistor MN8, transistor MN10, transistor MP10 and transistor MN12; the gate of transistor MP8 is connected to node c, the source is connected to node f and the drain is connected to node g; the gate of transistor MN7 is connected to node g, the source is connected to ground and the drain is connected to node g; the gate of transistor MP9 is connected to input 0.2VCC, the source is connected to node f and the drain is connected to node j; the gate of transistor MN8 is connected to node g, the drain is connected to the drain of transistor MP9 and the source is connected to ground; the gate of transistor MN10 is connected to node j, the drain is connected to node h and the source is connected to node i; the gate of transistor MP10 is connected to node h, the source is connected to node e and the drain is connected to output V OUT1 ; the gate of transistor MN12 is connected to node h, the drain is connected to output V OUT1 and the source is connected to node i. Node e is connected to power supply voltage VCC; node i is connected to ground.

[0031] Transistors MN1, MN2, MN3, MN4, MN5, MN7, MN8, MN10, MN12 and MN15 are N-channel MOS transistors.

[0032] The transistors MP1, MP2, MP3, MP4, MP5, MP7, MP8, MP9 and MP10 are P-channel MOS transistors.

[0033] The charge-discharge module provides the input voltage Vtimer for the Timer circuit, and this module is the basis for the Timer circuit to detect whether the synchronization signal received by the driver is normal. VCC, C1 and R2 in the charge-discharge module constitute a charging network, and when the gate of transistor MN15 has no reset signal pulse, VCC generates a current through R2 to directly charge C1, and the voltage of capacitor C1 is equal to the input voltage V TIMER of the Timer. When the Reset reset signal arrives, transistor MN15 will leak the charge in the capacitor, and the voltage of the capacitor will decrease rapidly, and the voltage of Vtimer will decrease rapidly. Diode D Z mainly plays a role in clamping the voltage of V TIMER , because when the Reset reset signal is abnormal, capacitor C1 will continue to be charged, resulting in a very high voltage, and diode D Z limits the voltage of V TIMER , to avoid the discharge time of capacitor C1 being too long when the next Reset reset signal arrives.

[0034] The comparator module is composed of a comparator circuit and a second inverter circuit, and the comparator is composed of MP8, MP9, MN7, MN8 and MN10. Since the gate of MP9 is connected to the timer timeout threshold voltage, which is 0.2VCC, and MP8 is connected to the input voltage V TIMER , the comparator compares these two voltages, and as V TIMER changes, MN10 outputs digital signals of high and low levels; the second inverter composed of MP10 and MN12 mainly plays a role in isolation and shaping. When V TIMER <0.2VCC, the gate potential of MN10 is low, and the transistor is cut off, at this time the potential of point j is high, and after passing through the second inverter, it is low at this time, which means that the synchronization signal detected by the Timer is completely normal, and the driver will not be turned off; when V TIMERWhen the voltage is ≥0.2VCC, the gate potential of MN10 is high, and the transistor is turned on. At this time, the potential at point j is low, and it becomes high after passing through the second inverter. This indicates that the synchronization signal detected by the Timer is abnormal, causing the Timer's reset pulse signal to not arrive, thus causing the Timer to time out, i.e., V. TIMER If the voltage exceeds the threshold, the driver will shut down.

[0035] The status indicator module primarily helps the Logic determine the end time of the timer reset signal, enabling adjustable pulse width. When the timer reset signal is applied to the Timer circuit, it turns on the leakage current transistor MN15, and capacitor C1 rapidly leaks charge to ground through MN15. The voltage across the capacitor (which is also the Timer's input signal V) is... TIMER ), will decrease accordingly, when V TIMER When the value is reduced to the target value, the Timer outputs signal V. OUT2 It will change from a low level (without affecting the Logic circuit) to a high level, ending the Reset pulse signal output by the Logic, thus achieving adjustable reset pulse width.

[0036] The detailed operation of the status indicator module is as follows. In this module, the source voltage of MN3 is fixed, so the operating points of MN1 and MN2 are fixed and both are in the on state. The source voltage of MN4 is not fixed and varies with V. TIMER As the value changes, MN4 may be in a conducting or cut-off state. Adjusting the resistance of resistor R1 can change the threshold value of the source voltage comparison in the status indicator module; for example, a threshold value of 200mV.

[0037] When V TIMER When V = 0V, transistors MN1 and MN4 are both turned on. Because the V of MN4... GS The gate-source voltage must be greater than V of MN3. GS Therefore, the current flowing through MN4 must be greater than the reference current. However, due to the current limitation of the current source MP3, the maximum current through MN4 can only be equal to the reference current, so MN2 and MN4 enter the deep linear region. At this time, the voltage drop V between MN2 and MN4... DS Both the drain-source voltage and the voltage at point d are very small, so the potential at point d is low, and the output of the first inverter is high; when 200mV > V TIMER When the voltage is greater than 0V, the potential at point d gradually increases. This is because the source voltage of MN4 increases, and the voltage of MN4... GS As the voltage decreases, the operating point of MN2 gradually shifts towards the saturation region, and the drain-source voltage V of MN2 and MN4... DC The voltage increases continuously, but at this stage, the potential at point d is still considered low by the first inverter of the next stage, and the first inverter outputs V. OUT2 Maintain a high level; when VTIMER = 200mV, V GS of MN3 and MN4 are equal, so the states of transistors MN1 and MN2, MN3 and MN4 in the differential structure comparator are completely same. At this time, the voltage of point d is the turning point of the source voltage comparison circuit and is high level output by the first inverter; when V TIMER > 200mV, the threshold voltage V GS of MN4 is greater than V TH , transistor MN4 is cut off, and because MP3 always works in the on state (no current flows, in the deep linear region), the potential of point d is directly pulled up to the high potential, close to the power supply voltage VCC. At this time, MN5 in the first inverter is on and MP7 is cut off, and the signal V OUT2 output to the logic circuit is low level. Therefore, the state indication module provided by the application can compare V TIMER with the threshold value determined by the resistance R1, when the rising edge of the Reset reset signal comes, V TIMER rapidly decreases; until it decreases below the threshold value, the low level output by the state indication module will affect the logic part of the driver to make the falling edge of the Reset reset signal, and finally realize the adjustable reset pulse width.

[0038] According to the above description, it can be known that: the new voltage comparison technology adopted by the application realizes the Timer circuit with adjustable reset pulse width, greatly improves the precision of Timer timing and resetting, and solves the problem that the traditional Timer structure may cause the Timer to be possibly mis-stopped and abnormally detected due to the use of the fixed pulse width Reset reset signal after the timing period is accumulated.

[0039] Embodiment 2

[0040] A synchronous rectification gate driver, comprising a logic circuit (Logic), a timer (Timer), a protection circuit, a gate circuit (logic "and") and a driving circuit, the gate circuit being an AND gate. The timer is the Timer circuit with adjustable pulse width described in Embodiment 1.

[0041] The connection relationship of the logic circuit (Logic), the timer (Timer), the protection circuit, the gate circuit (logic "and") and the driving circuit is as shown in Figure 1 , the output end of the logic circuit is connected with the input end of the driving circuit, the Reset signal sending end of the logic circuit is connected with the signal input end of the timer, the output end V OUT1 of the timer is connected with the input end of the gate circuit, the output end V OUT2 of the timer is connected with one input end of the logic circuit, the output end of the protection circuit is connected with the other input end of the logic circuit; the output end of the logic circuit is connected with the signal feedback input end of the logic circuit.

[0042] The above description is the preferred embodiment of the present application and is not intended to limit the present application. The present application can be variously changed and modified by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the present application.

Claims

1. A timer circuit with adjustable reset pulse width, characterized in that, It includes a status indication module, a charge / discharge module, and a comparator module; The status indication module includes a source voltage comparison circuit and a first inverter. The source voltage comparison circuit includes transistors MN1, MN2, MN3, and MN4, as well as a resistor R1. The first inverter includes MN5 and transistor MP7. The gate and drain of transistor MN1 are connected to node a, and the source is connected to node b; the drain of transistor MN2 is connected to node d, the gate is connected to node a, and the source is connected to the drain of transistor MN4; the drain and gate of transistor MN3 are connected to node b, and the source is connected to the first terminal of resistor R1. Transistor MN4 has its gate connected to node b and its source connected to node c. Node c is connected to the input voltage V of the timer. TIMER The second terminal of resistor R1 is grounded; the gate of transistor MP7 is connected to node d, the source to node e, and the drain to the output V. OUT2 Node e is connected to the power supply voltage; the gate of transistor MN5 is connected to node d, and the drain is connected to the output voltage V. OUT2 The source is grounded; The comparator module is used to compare the input voltage V. TIMER The comparison result determines the magnitude of the timeout threshold voltage and outputs a high-level or low-level signal accordingly. The charging and discharging module is used to provide input voltage V to the status indication module and the comparator module. TIMER .

2. The timer circuit with adjustable reset pulse width according to claim 1, characterized in that, The charging / discharging module includes a resistor R2, a capacitor C1, and a transistor MN15. The first terminal of resistor R2 is connected to the power supply voltage VCC, and the second terminal is connected to the first terminal of capacitor C1. The second terminal of capacitor C1 is grounded. The source of transistor MN15 is connected to ground, the drain is connected to node c, and the gate is connected to the input signal Reset. The second terminal of resistor R2 and the first terminal of capacitor C1 are connected to the input signal VCC. TIMER .

3. The timer circuit with adjustable reset pulse width according to claim 1, characterized in that, The drain of transistor MN15 is connected to the negative terminal of diode DZ, and the drain is connected to the positive terminal of diode DZ. The positive terminal of diode DZ is connected to ground.

4. The timer circuit with adjustable reset pulse width according to claim 1, characterized in that, The comparator module includes transistors MP8, MP9, MN7, MN8, MN10, MP10, and MN12; the gate of transistor MP8 is connected to node c, the source is connected to node f, and the drain is connected to node g. The gate of transistor MN7 is connected to node g, the source is grounded, and the drain is connected to node g. Transistor MP9 has its gate connected to the timeout threshold voltage, its source connected to node f, and its drain connected to node j; transistor MN8 has its gate connected to node g, its drain connected to the drain of transistor MP9, and its source connected to ground; transistor MN10 has its gate connected to node j, its drain connected to node h, and its source connected to ground; transistor MP10 has its gate connected to node h, its source connected to node e, and its drain connected to the output V. OUT1 The gate of MN12 is connected to node h, and the drain is connected to the output V. OUT1 The source is grounded; node e is connected to the power supply voltage VCC.

5. The timer circuit with adjustable reset pulse width according to claim 1, characterized in that, It also includes a current source module for providing voltage to the status indication module, the charge / discharge module, and the comparator module.

6. The timer circuit with adjustable reset pulse width according to claim 5, characterized in that, The current source module includes transistors MP1, MP2, MP3, MP4, and MP5. The source node of transistor MP1 is connected to node e, and its gate is connected to the input signal Vg. The source node of transistor MP2 is connected to node e, its gate is connected to the input signal Vg, and its drain node is connected to node a. The source node of transistor MP3 is connected to node e, its gate is connected to the input signal Vg, and its drain node is connected to node d. The source node of transistor MP4 is connected to node e, its gate is connected to the input signal Vg, and its drain node is connected to node f. The source node of transistor MP5 is connected to node e, its gate is connected to the input signal Vg, and its drain node is connected to node h. The gate of transistor MP1 is connected to the reference voltage Vg, and the gates of transistors MP2, MP3, MP4, and MP5.

7. The timer circuit with adjustable reset pulse width according to claim 1, characterized in that, The resistor R1 is an adjustable resistor.

8. A driver, characterized in that, Includes a timer circuit with adjustable reset pulse width as described in any one of claims 1-7.

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