Output impedance calibration and related apparatus, systems and methods

Abstract

Output impedance calibration and related apparatus, systems, and methods are disclosed. An apparatus may include a ZQ calibration circuit. The ZQ calibration circuit may include a first register configured to store a first impedance calibration code generated in response to a ZQ calibration command. The ZQ calibration circuit may also include a second register configured to store a shift value. Additionally, the ZQ calibration circuit may include a computation block configured to generate a second impedance calibration code based on the first impedance calibration code and the shift value.

Description

[0001] Priority requirements

[0002] This application claims the benefit of U.S. Patent Application No. 17 / 238,561, entitled “Output Impedance Calibration, and Related Devices, Systems, and Methods,” filed April 23, 2021. Technical Field

[0003] Embodiments of this disclosure relate to impedance calibration. However, more specifically, some embodiments of this disclosure relate to the output impedance calibration of microelectronic devices, and related methods, apparatus, and systems. Background Technology

[0004] Memory devices are typically provided as internal components, semiconductors, or integrated circuits in computers or other electronic systems. Many different types of memory exist, including, for example, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), resistive random access memory (RRAM), double data rate memory (DDR), low-power double data rate memory (LPDDR), phase-change memory (PCM), and flash memory.

[0005] Electronic systems (e.g., memory systems) typically contain one or more types of memory, which are usually coupled to one or more communication channels within the memory system. Time-varying signals in such systems are used to transmit information (e.g., data) via one or more conductors, typically referred to as signal lines. These signal lines are often bundled together to form a communication bus, such as an address or data bus.

[0006] To meet the demands for higher performance operating characteristics, designers continue to strive to increase the operating speed of data transmission across communication buses within electronic systems. One problem with increased data transmission rates is maintaining signal integrity during bursts of data on the communication bus of an electronic (e.g., memory) system. As transmission rates increase, the impedance characteristics of the communication bus can become more pronounced, and signal waveforms can begin to spread, and / or reflections can occur at locations of impedance mismatch on the communication bus. Signal integrity (e.g., data integrity) can be compromised when the impedance (e.g., output impedance) of one or more nodes of a memory device coupled to the communication bus is not properly matched to the impedance of the communication bus. Summary of the Invention

[0007] One or more embodiments of this disclosure include an apparatus. The apparatus may include a ZQ calibration circuit comprising: a first register configured to store a first impedance calibration code generated in response to a ZQ calibration command; a second register configured to store a shift value; and a calculation block configured to generate a second impedance calibration code based on a third impedance calibration code and the shift value.

[0008] Some embodiments of this disclosure include a system. The system may include a microelectronic device that may include at least one driver configured in one of several configurations based on selected calibration codes. The microelectronic device may also include logic for determining a difference between a first calibration code and a second calibration code among a plurality of calibration codes. Additionally, the microelectronic device may include one or more registers for storing one or more calibration codes among the plurality of calibration codes and a shift value indicating the difference between the first calibration code and the second calibration code. Furthermore, the microelectronic device may include a computational block for adjusting a third calibration code among the plurality of calibration codes based on the shift value.

[0009] Additional embodiments of this disclosure include an electronic system. The electronic system may include: at least one input device; at least one output device; at least one processor device operatively coupled to the input device and the output device; and at least one memory system operatively coupled to the at least one processor device. The memory system may include a memory device comprising a driver and a circuit system coupled to the driver. The circuit system may be adapted to configure the driver based on a first impedance calibration code generated in response to a first calibration operation. The circuit system may be further adapted to store a second impedance calibration code generated in response to a test operation. Furthermore, the circuit system may be configured to store a third impedance calibration code generated in response to a second calibration operation. The circuit system may also be adapted to configure the driver based on a fourth impedance calibration code generated based on the third impedance calibration code and the difference between the first and second impedance calibration codes.

[0010] Other embodiments of this disclosure include a method. The method may include performing a first calibration operation to determine a first impedance calibration code for a microelectronic device. The method may also include performing a test operation to determine a second impedance calibration code for the microelectronic device based on a plurality of measured signal integrity responses generated via the microelectronic device. Additionally, the method may include performing a second calibration operation to determine a third impedance calibration code for the microelectronic device. Furthermore, the method may include updating the third impedance calibration code based on the difference between the first impedance calibration code and the second impedance calibration code. Attached Figure Description

[0011] Figure 1 This is a block diagram of an example memory system comprising several memory devices according to various embodiments of the present disclosure.

[0012] Figure 2 This is a functional block diagram of an example memory device according to various embodiments of the present disclosure.

[0013] Figure 3 Example memory systems comprising dual in-line memory modules coupled to a host are described according to various embodiments of the present disclosure.

[0014] Figure 4A and 4B Each describes an example channel performance response of the memory system.

[0015] Figure 5 An example memory system is depicted, which includes an output driver that couples a memory device to the host.

[0016] Figure 6 An example memory system comprising a memory device coupled to a host output driver according to various embodiments of the present disclosure is described.

[0017] Figure 7A A flowchart illustrating example methods for operating a memory system according to various embodiments of this disclosure.

[0018] Figure 7B A flowchart illustrating an example method for performing read training of a memory device according to various embodiments of the present disclosure.

[0019] Figure 7C A flowchart illustrating an example method for calibrating a memory device according to various embodiments of the present disclosure.

[0020] Figure 8 A flowchart illustrating example methods of operating a memory device according to various embodiments of the present disclosure.

[0021] Figure 9 This is a simplified block diagram of an example memory system implemented according to one or more embodiments described herein.

[0022] Figure 10 This is a simplified block diagram of an example electronic system implemented according to one or more embodiments described herein. Detailed Implementation

[0023] Memory devices (e.g., memory devices within memory systems) may include output devices comprising one or more output drivers for driving signals (e.g., off-chip signals) during data transmission. It should be understood that various memory systems—including, for example, memory systems with two dual in-line memory modules (DIMMs) per channel (2DPC) and memory systems with four DIMMs per channel (4DPC)—may include variable internal characteristics and may exhibit variable channel performance responses (e.g., during data transmission). Channel performance can affect signal integrity, and even if a memory system may meet design specifications, its signal integrity may still be less than ideal (e.g., due to less than ideal channel performance). In some conventional devices, systems, and methods, signal integrity issues are addressed by manually adjusting the output driver circuitry (e.g., manually adjusting the on-resistance (Ron) of the output drivers). However, manually adjusting the output driver circuitry requires additional resources and time and may introduce other problems (e.g., due to design fragments with variable characteristics).

[0024] As disclosed herein, various embodiments relate to automated impedance calibration (e.g., for semiconductor device readout operations). According to various embodiments, during a first mode (e.g., during power-on of the semiconductor device), a first impedance calibration operation may be performed (e.g., in response to a long calibration command) to determine a first calibration code (e.g., for one or more drivers of the semiconductor device). Additionally, during the first mode, a test operation may be performed to determine a second calibration code (e.g., based on a measured signal integrity response of the semiconductor device). Furthermore, a difference (“shift value”) between the first and second calibration codes may be determined, and the difference may be stored (e.g., stored in a register). Additionally, during a second mode (e.g., during operation of the semiconductor device), a second impedance calibration operation may be performed (e.g., in response to a short calibration command) to determine a third calibration code. Furthermore, during the second mode, a fourth calibration code may be determined based on the third calibration code and the shift value. More specifically, the third calibration code may be updated based on the shift value to generate the fourth calibration code. Therefore, during the operation of the semiconductor device, one or more drivers of the semiconductor device can be tuned (e.g., independently of the host) based on shift values ​​determined through previously performed test operations.

[0025] Various embodiments of this disclosure can enhance and potentially optimize signal integrity associated with semiconductor devices (e.g., memory devices and / or memory systems). For example, in some embodiments, signal integrity of the semiconductor device can be enhanced and potentially optimized without manual adjustment of the output impedance (e.g., without adjustment by the designer and / or user). Additionally, according to some embodiments, unwanted design fragments can be avoided (e.g., via automated impedance calibration, as described herein). It should be understood that the various embodiments disclosed herein can replace (i.e., substitute for) conventional calibration operations.

[0026] Although various embodiments are described herein with reference to memory systems and / or memory devices, this disclosure is not limited thereto, and the embodiments are generally applicable to microelectronic systems and / or devices that may or may not include semiconductor devices and / or memory devices. Embodiments of this disclosure will now be illustrated with reference to the accompanying drawings.

[0027] Figure 1 An example memory system 100 according to various embodiments of the present disclosure is illustrated. The memory system 100 includes several memory devices 102-105 coupled to a communication bus 110 (e.g., a system bus). Each memory device 102-105 may include one or more memory dies, and the memory devices 102-105 may be collectively referred to as dual in-line memory modules (DIMMs), multi-chip packages (MCPs), or stacked packages (POPs). Each memory device 102-105 of the memory system 100 may include an output driver comprising several cell drivers and associated calibration circuitry, as described more fully below.

[0028] The memory system 100 further includes a controller 112 coupled to each memory device 102-105 via a communication bus 110. The controller 112, which may include a processor or any other type of controller (also referred to herein as a “host”), may be configured to control and / or regulate various operations of the memory system 100 and provide interactivity with another device or system coupled to the memory system 100 via an interface 114.

[0029] The communication bus 110 may include one or more of an address bus 120, a data bus 122, and a control signal bus 124. In some embodiments, the memory devices 102-105, the communication bus 110, and the controller 112 may be configured (e.g., physically arranged and mounted) on a printed circuit board (PCB).

[0030] Figure 2This is a functional block diagram illustrating an example memory device 200 according to at least one embodiment of the present disclosure. The memory device 200 may include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), double data rate SDRAM (DDR SDRAM, such as DDR4 SDRAM, etc.), or synchronous graphics random access memory (SGRAM). For example, Figure 1 One or more of the memory devices 102-105 may include memory device 200. Memory device 200, which can be integrated on a semiconductor chip, may include memory array 202.

[0031] exist Figure 2 In this embodiment, memory array 202 is shown as comprising eight memory banks BANK0-7. More or fewer memory banks may be included in memory array 202 in other embodiments. Each memory bank includes several access lines (word lines WL), several data lines (bit lines BL and / or BL), and several memory cells MC disposed at the intersections of the word lines WL and the bit lines BL and / or BL. The selection of word lines WL may be performed by row decoder 204, and the selection of bit lines BL and / or BL may be performed by column decoder 206. Figure 2 In one embodiment, row decoder 204 may include a corresponding row decoder for each memory bank BANK0-7, and column decoder 206 may include a corresponding column decoder for each memory bank BANK0-7.

[0032] Bit lines BL and / BL are coupled to the corresponding sense amplifiers SAMP. Read data from bit line BL or / BL can be amplified by the sense amplifier SAMP and transmitted to the read / write amplifier 260 via the complementary local data line (LIOT / B), the transmission gate (TG), and the complementary master data line (MIOT / B). Conversely, write data output from the read / write amplifier 260 can be transmitted to the sense amplifier SAMP via the complementary master data line MIOT / B, the transmission gate TG, and the complementary local data line LIOT / B, and written to the memory cell MC coupled to bit line BL or / BL.

[0033] The memory device 200 may be generally configured to receive various inputs via various terminals (e.g., address terminal 210, command terminal 212, clock terminal 214, data terminal 216, and data mask terminal 218) (e.g., from an external controller). The memory device 200 may include additional terminals, such as power supply terminal 220 and power supply terminal 222.

[0034] During the intended operation, one or more command signals COM received via command terminal 212 can be transmitted to command decoder 250 via command input circuitry 252. Command decoder 250 may include circuitry configured to generate various internal commands by decoding one or more command signals COM. Examples of internal commands include the activity command ACT and the read / write signal R / W.

[0035] Additionally, one or more address signals ADD received via address terminal 210 can be transmitted to address decoder 230 via address input circuit 232. Address decoder 230 can be configured to supply row address XADD to row decoder 204 and column address YADD to column decoder 206. Although command input circuit 252 and address input circuit 232 are described as separate circuits, in some embodiments, address signals and command signals can be received via a common circuit.

[0036] The activation command ACT may include a pulse signal activated in response to a command signal COM (e.g., an activation command) indicating row access. In response to the activation signal ACT, the row decoder 204 specifying the bank address can be activated. Therefore, the word line WL specified by the row address XADD can be selected and activated.

[0037] The read / write signal R / W may include a pulse signal activated in response to a command signal COM (e.g., a read command or a write command) indicating column access. In response to the read / write signal R / W, the column decoder 206 may be activated, and the bit line BL specified by the column address YADD may be selected.

[0038] In response to the activity command ACT, the read signal, the row address XADD, and the column address YADD, data can be read from the memory cell MC specified by the row address XADD and the column address YADD. The read data can be output via the sense amplifier SAMP, the transmission gate TG, the read / write amplifier 260, the input / output circuit 262, and the data terminal 216. Additionally, in response to the activity command ACT, the write signal, the row address XADD, and the column address YADD, write data can be supplied to the memory array 202 via the data terminal 216, the input / output circuit 262, the read / write amplifier 260, the transmission gate TG, and the sense amplifier SAMP. The write data can be written to the memory cell MC specified by the row address XADD and the column address YADD.

[0039] Clock signals CK and / CK can be received via clock input 214. Clock input circuit 270 can generate an internal clock signal ICLK based on clock signals CK and / CK. The internal clock signal ICLK can be transmitted to various components of memory device 200, such as command decoder 250 and internal clock generator 272. Internal clock generator 272 can generate an internal clock signal LCLK, which can be transmitted to input / output circuit 262 (e.g., for controlling the operating timing of input / output circuit 262). Additionally, data mask input 218 can receive one or more data mask signals DM. When a data mask signal DM is activated, overwriting of corresponding data can be disabled.

[0040] Power supply voltages VDD and VSS can be supplied to internal voltage generator circuitry 221, which can provide various internal voltages VPP, VARY, VPERI, VEQ, and VCCP. Memory device 200 may also include a calibration terminal ZQ, coupled to the power supply potential VDDQ via a reference resistor RZQ. The reference resistor RZQ, which may be located on, for example, only the memory module substrate or motherboard, is included as a resistor referenced during calibration operations. The impedance of the reference resistor RZQ serves as the reference impedance for ZQ calibration circuitry 223. In some instances, voltage generator circuitry 221 provides a reference potential ZQVREF signal to ZQ calibration circuitry 223. When calibration circuitry 223 is activated (e.g., via calibration signal DOZQCAL), it performs calibration operations by referencing the impedance of reference resistor RZQ and the reference potential ZQVREF. During calibration operations, ZQ calibration circuitry 223 can provide a ZQ calibration code ZQCODE. In some instances, the ZQ calibration code ZQCODE may contain multiple bits specifying the impedance of the corresponding pull-up or pull-down circuit in the input / output circuit 262.

[0041] In some instances, memory device 200 may include ZQ calibration control circuitry 225 coupled to ZQ calibration circuitry 223 and input / output circuitry 262. For example, command decoder 250 may provide ZQ calibration command ZQCAL to ZQ calibration control circuitry 225. Upon arrival of each ZQCAL command, ZQ calibration control circuitry 225 may be configured to provide ZQ calibration code ZQCODE1 to input / output circuitry 262. In some instances, ZQ calibration code ZQCODE1 may be ZQ calibration code ZQCODE provided by ZQ calibration circuitry 223 and supplied to input / output circuitry 262 by ZQ calibration control circuitry 225. Alternatively and / or additionally, ZQCODE1 may be a pre-stored ZQ calibration code retrieved by ZQ calibration control circuitry 225 and provided to input / output circuitry 262. In other words, the ZQ calibration control circuit 225 can be configured to activate ZQ calibration and supply calibration codes provided by the ZQ calibration circuit 223 to the input / output circuit 262, or skip ZQ calibration and retrieve pre-stored calibration codes provided to the input / output circuit 262.

[0042] In some instances, the ZQ calibration control circuit 225 may pre-store multiple ZQ calibration codes provided by the ZQ calibration circuit 223 from an initial calibration table obtained from previous calibration or back-end testing. In some instances, the ZQ calibration control circuit 225 may include a voltage signal and a temperature signal TEMP that respectively indicate voltage and temperature conditions of the memory device 200. For example, the voltage signal may indicate the power supply voltage of the memory device 200. The temperature signal TEMP may indicate the operating temperature of the memory device 200. For example, the temperature signal TEMP may be provided by a temperature sensor 227. When pre-storing ZQ calibration codes, the ZQ calibration control circuit 225 may also store operating conditions, such as voltage / temperature conditions associated with the ZQ calibration codes. According to various embodiments, as described in more detail below, the memory device 200 may include one or more unit drivers and associated circuitry (e.g., a ZQ calibration circuitry) for calibrating one or more unit drivers. More specifically, as described in more detail below, the desired output impedance of one or more cell drivers of memory device 200 (e.g., for read operations) can be determined (i.e., determined via one or more calibration and / or training operations) such that memory device 200 can present acceptable (e.g., desired and / or optimal) signal integrity during device operation.

[0043] Figure 3A memory system 300 comprising a dual in-line memory module (DIMM) 302 coupled to a host 304 is depicted according to various embodiments of the present disclosure. The DIMM 302 includes a plurality of units 306 for transferring information (e.g., DQ, DQS, address, and / or command) from a memory device to a host (also referred to herein as a “controller”) 304 via a plurality of channels 305. Each unit 306 may include, for example, a data (DQ) terminal, a data strobe (DQST) terminal, and / or a data strobe complement (DQSC) terminal.

[0044] As should be understood, each unit 306 may include several terminals, pads, and / or pins. Figure 3 (Not shown in the image). It should be understood that in some instances, signal integrity (e.g., for data transmission via one or more channels 305) may vary across cells 306 of the memory system 300. Additionally, in some instances, signal integrity (e.g., for data transmission via one or more channels 305) may vary across a single cell 306.

[0045] Figure 4A and 4B Each describes an example channel performance response of the memory system. More specifically, Figure 4A and 4B Each describes a memory system (e.g., Figure 3 The channel of the memory system 300) (e.g., Figure 3 The signal integrity results of channel 305 (also referred to herein as "signal integrity", "signal integrity response", "channel performance", "channel performance response"). It should be understood that... Figure 4A Data Eye 402 compared to Figure 4B The data point 404 is relatively large, and therefore, Figure 4A The described signal integrity results are relative to Figure 4B The signal integrity results described have been improved.

[0046] Figure 5A memory system 500 is depicted, comprising an output driver 502 (e.g., an output driver for a memory device (e.g., DRAM)) coupled to a host 504 via a channel 506. The output driver 502 comprises a plurality of drivers 508 coupled in parallel. Each driver (also referred to herein as a “cell driver”) 508 may have the same or similar circuitry. More specifically, each driver 508 comprises a plurality of transistors M. Additionally, each driver 508 includes a resistor R coupled between a terminal (e.g., source or drain terminal) of an associated transistor M and a node N (also referred to herein as an “output node,” “DQ node,” “DQ pin,” or “DQ pad”). It should be understood that a plurality of operating signals can be supplied to the gate of the transistors M to select the plurality of transistors. In other words, each transistor M can be individually controlled (i.e., turned on / off) based on the associated operating signals. In this example, each driver 508 has an output impedance of 240 ohms.

[0047] As should be understood, signal integrity (i.e., the signal integrity for read operations on a memory device) can be affected by the output resistance Ron (also referred to as "on-resistance") of the output driver and system characteristics (e.g., channel characteristics) that may be associated with the output driver. It should also be understood that in some systems, the value of the output resistance Ron may be 240 ohms, which can be adjusted via output impedance (ZQ) calibration. Although the value of the output resistance Ron can be adjusted (e.g., according to design specifications), signal integrity may still be less than ideal (e.g., due to less than ideal channel performance). Therefore, according to at least some embodiments, the value of the output resistance Ron can be adjusted (e.g., from a specified value) to improve signal integrity. More specifically, according to at least some embodiments, the value of the output resistance Ron can be adjusted via an automated calibration process (e.g., without the need for manual adjustment).

[0048] In some cases, Ron values ​​outside the specification range can be used to enhance (e.g., optimize) signal integrity. For example, a Ron value of 220 ohms may provide optimal results, even if the design specification includes a Ron value of 240 ohms and a 5% allowable variation (i.e., 228–252 ohms). As mentioned above, conventional systems, devices, and methods can tune the output resistance Ron via a manual process, which requires additional resources and / or time.

[0049] Figure 6 An example memory system 600 according to various embodiments of the present disclosure is depicted. The memory system 600 includes a ZQ calibration circuit 602 (e.g., Figure 2 ZQ calibration circuit 223 of memory device 200.

[0050] The memory system 600 further includes a plurality of drivers 608, wherein each driver (also referred to herein as a “cell driver”) 608 includes a plurality of logic gates 624 and a plurality of transistors M. For example, Figure 2 The input / output circuitry 262 may include a driver 608. For example, refer to... Figure 3 and 6 ZQ calibration circuitry 602 and / or driver 608 may be part of a memory component (e.g., DQ cell 306 and DQS terminals 308 and 310), channel 606 may include channel 305, and host 604 may include host 304. Similar to... Figure 5 The memory system 500 can individually control (i.e., turn on / off) each transistor M of the memory system 600 based on associated operating signals. Each driver 608 may include a resistor R coupled between a terminal (e.g., source or drain terminal) of the associated transistor M and a node N, which may include an output node (e.g., a DQ node). It should be understood that in some embodiments (e.g., where the output resistance Ron is relatively small), the resistor R may not be necessary.

[0051] As should be understood, each driver 608 can be configured based on a calibration code. In other words, a calibration code can be associated with and / or indicate the driver configuration of one or more drivers 608. For example, a calibration code of "one" can be associated with and / or indicate the driver configuration of "one" transistor (i.e., for conducting electricity) of selected driver 608. As another example, a calibration code of "five" can be associated with and / or indicate the driver configuration of "five" transistors (i.e., for conducting electricity) of selected driver 608.

[0052] The ZQ calibration circuit 602 includes logic 610 (also referred to herein as "ZQ calibration logic" or "calibration logic"), register 612, logic 614, and register 616. According to some embodiments, logic 610 may include elements coupled to resistor RZQ (see [link to relevant documentation]). Figure 2A copy output buffer is provided to perform the ZQ calibration operation. The ZQ calibration circuit 602 also includes a computation block (e.g., an addition and / or subtraction block) 618 and a latch 620. According to some embodiments, each of registers 612 and 616 may be configured to store one or more values ​​(e.g., calibration codes and / or shift values). Additionally, logic 614 may be configured to compare two values ​​(e.g., two calibration codes) and determine the difference between said values. More specifically, for example, as described more fully below, logic 614 may be configured to compare an initial calibration code (e.g., an initial calibration code generated during power-on of the memory system 600 and in response to a “long calibration” operation) with a calibration code determined via a training operation (also referred to herein as a “test result,” “test result calibration code,” “test result code,” or some variation thereof) (e.g., a calibration code executed during power-on of the memory system 600) to determine the difference between the initial calibration code and the training result calibration code (also referred to herein as a “shift value” or “offset”). In other embodiments, another component and / or device (e.g., host 604) may be configured to determine the difference between the two calibration codes. For example, the difference between the initial ZQ calibration code and the training result calibration code may be stored in register 616 as a shift value. As a non-limiting example, the shift value may be one of "+1", "-1", "+2", "-2", "+3", "-3", etc.

[0053] The computation block 618 can be configured to receive input values ​​from register 612 (e.g., calibration codes generated during operation of memory system 600 and in response to a “short calibration” operation), add or subtract the shifted value from the input value (i.e., add or subtract based on the signal received from register 616), and generate an output value that can be used as calibration codes to configure one or more unit drivers 608.

[0054] As a non-limiting example, during operation of the memory system 600 (e.g., during an operation mode), the computation block 618 may be configured to receive a calibration code of “5” from register 612, subtract the calibration code from a value of “1” (i.e., shift the value by “-1”), and generate an updated calibration code of “4” (i.e., 5-1=4). As another non-limiting example, the computation block 618 may be configured to receive a calibration code of “7” from register 612, add a value of “2” to the calibration code (i.e., shift the value by “+2”), and generate an updated calibration code of “9” (i.e., 7+2=9). As those skilled in the art will understand, the latch 620 may receive input from the computation block 618, store values, and output signals that can be used to configure the unit driver 608 based on the calibration code generated via the computation block 618.

[0055] According to some embodiments, each cell driver 608 of the memory system 600 may be associated with a dedicated ZQ calibration circuitry (e.g., logic 610, registers 612 and 616, logic 614, compute block 618, and / or latch 620). In other embodiments, more than one cell driver 608 may be associated with (e.g., supported by) the same ZQ calibration circuitry (e.g., logic 610, registers 612 and 616, logic 614, compute block 618, and / or latch 620). Figure 6 As shown, host 604 is coupled to driver 608 (e.g., for receiving various signals) via channel 606. Additionally, according to some embodiments, host 604 may be coupled to ZQ calibration circuitry 602 (e.g., register 612).

[0056] The following describes a contemplated, non-limiting example operation of the memory system 600. In response to a calibration operation (e.g., a “long calibration operation”) during power-on (e.g., during a power-on mode) of the memory system 600, a calibration code (“initial calibration code”) may be received from register 612, and said register may store the calibration code. In some embodiments, host 604 may transmit the initial calibration code to logic 610, which may provide the calibration code to register 612. In other embodiments, the initial calibration code may be received from another device (i.e., a device not of host 604). More specifically, for example, in response to a calibration command, ZQ calibration circuit 602 may receive a calibration signal (e.g., Figure 2 (DOZQCAL) and through a reference resistor (e.g., Figure 2 The impedance and reference potential of the resistor RZQ) Figure 2 The host 604 performs a calibration operation (e.g., a long calibration operation) to generate a calibration code. Alternatively, in these embodiments, the calibration code may be provided to one or more unit drivers 608 for selecting a plurality of transistors M (e.g., selecting 1-N transistors to be on (i.e., for conduction)). In other embodiments, logic 610 and / or register 612 may not be necessary (i.e., not necessary for providing the calibration code to driver 608), and in these embodiments, the host 604 may transmit an initial calibration code to one or more unit drivers 608 for selecting a plurality of transistors M.

[0057] Additionally, according to various embodiments, the memory system 600 may be configured to determine, via testing (e.g., during power-on), a value for an output resistance Ron that enhances and potentially optimizes (i.e., optimizes at least a portion of the operation of the memory system 600) the signal integrity associated with channel 606. More specifically, for example, the memory system 600 may be configured to test several values ​​of the output resistance Ron (e.g., based on several calibration codes) to determine an optimal Ron value among several Ron values.

[0058] For example, a scan of several possible calibration codes can be performed (e.g., during power-on) to identify the optimal calibration code. In some instances, the optimal calibration code can be determined via a test procedure performed by host 604 and ZQ calibration circuit 602 and / or driver 608 (e.g., during power-on of memory system 600). More specifically, for example, with selected transistors (e.g., based on an initial calibration code) conducting, a signal can be transmitted from driver 608 to host 604 (i.e., data can be read from driver 608), and the channel performance response can be measured and / or evaluated. For example, the size of the data eye in the channel performance response can be measured and / or evaluated. Alternatively, with different selected transistors (e.g., based on another calibration code) conducting, a signal can be transmitted from driver 608 to host 604 (i.e., data can be read from driver 608), and the channel performance response can be measured and / or evaluated. Furthermore, the channel performance response can be compared with a previous channel performance response. If the channel performance response is improved compared to the previous channel performance response (i.e., the previous channel performance response associated with the initial calibration code), the associated calibration code can be stored (e.g., stored in register 612). For example, in response to determining that the channel performance response is improved relative to the previous channel performance response, host 604 can transmit a signal to ZQ calibration circuit 602 to instruct ZQ calibration circuit 602 to store the associated calibration code (e.g., stored in register 612). On the other hand, if the channel performance response is not improved compared to the previous channel performance response (i.e., the previous channel performance response associated with the initial calibration code), the associated calibration code may not be stored.

[0059] This calibration (“training” or “testing”) process can be repeated for each of several calibration codes to generate and measure and / or evaluate the channel performance response of each of several transistor configurations of driver 608 (e.g., one transistor conducting, two transistors conducting, three transistors conducting, etc.) and determine a test result calibration code associated with the desired (e.g., optimal) channel performance response (e.g., and store it in register 612). Further description of example test operations that can be used (e.g., during power-up) to determine the optimal calibration code (i.e., to improve signal integrity) is included in U.S. Patent Application No. 17 / 141,031, filed January 4, 2021, entitled “Output Impedance Calibration, and Related Devices, Systems, and Methods.” Additionally, after power-up (e.g., during operation of memory system 600), unit driver 608 can be configured based on a test result calibration code that generates the optimal channel performance response (i.e., generates the optimal channel performance response during the calibration / testing process).

[0060] Additionally, according to various embodiments, the optimal calibration code (“test result calibration code”) associated with the determined Ron value may be compared with the initial calibration code (e.g., the code generated in response to a long calibration operation) (e.g., via logic 614), and the difference between the initial calibration code and the test calibration code may be stored in register 616 (e.g., as a “shift value”).

[0061] It should be understood that one or more conditions of the memory system 600 (e.g., voltage and / or temperature) may vary (e.g., depending on the mode of the memory system 600). More specifically, the voltage and / or temperature of the memory system 600 during power-on may differ from the voltage and / or temperature of the memory system 600 during operation. Therefore, it should also be understood that another calibration operation may be performed after power-on and during operation of the memory system 600.

[0062] Continuing the example operation of memory system 600, in response to a calibration command (e.g., a short calibration command) during operation, another calibration operation can be performed, and another calibration code can be determined and stored in register 612. Additionally, according to some embodiments of this disclosure, the calibration code (e.g., determined during operation) can be updated based on a shift value stored in register 616 (e.g., via calculation block 618). Furthermore, the updated calibration code can be used to configure one or more cell drivers 608.

[0063] Therefore, as should be understood, one or more cell drivers of the memory system 600 can be tuned (i.e., tuned during operation) based on shift values ​​stored in register 616 (e.g., without feedback from host 604). In other words, one or more cell drivers of the memory system 600 can be tuned (i.e., tuned during operation without feedback from host 604) at least in part based on calibration codes (i.e., calibration codes determined via previously performed test operations (e.g., test operations performed during power-on and via host 604), which improve the signal integrity of the memory system 600 during power-on.

[0064] Figure 7A This is a flowchart of an example method 700 for operating a memory system. More specifically, method 700 can be used to initialize and / or calibrate a memory system. Method 700 may be arranged according to at least one embodiment described in this disclosure. In some embodiments, method 700 may be performed by an apparatus or system, such as... Figure 1 The memory system 100, one or more memory devices of the memory system 100, Figure 2 Memory device 200, Figure 3 Memory system 300, Figure 6 Memory system 600, Figure 9 Memory system 900, Figure 10 The electronic system 1000, or another device or system. Although described as discrete blocks, the various blocks may be further divided into additional blocks, combined into fewer blocks, or said blocks may be eliminated, depending on the desired implementation.

[0065] Method 700 may begin at block 702, wherein the memory system (e.g., Figure 6 The memory system 600 can be powered on or reset, and method 700 can continue to block 704. At blocks 704, 706, and 708, various calibration and / or training operations for the memory system can be performed. More specifically, for example, as those skilled in the art will appreciate, at block 704, ZQ calibration can be performed (e.g., utilizing the replication buffer and resistor RZQ in ZQ calibration circuit 223; see [link to relevant documentation]). Figure 2 At block 706, command and address (CA) training can be performed, and at block 708, write training can be performed.

[0066] Additionally, at block 710, read training according to various embodiments of this disclosure can be performed. (See reference...) Figure 7B The flowchart depicted hereby describes an example method 720 for performing read training on a memory device. Method 720 may be arranged according to at least one embodiment described in this disclosure. In some embodiments, method 720 may be performed by a device or system, such as... Figure 1 The memory system 100, one or more memory devices of the memory system 100, Figure 2 Memory device 200, Figure 3 Memory system 300, Figure 6 Memory system 600, Figure 9 Memory system 900, Figure 10 The electronic system 1000, or another device or system. Although described as discrete blocks, the various blocks may be further divided into additional blocks, combined into fewer blocks, or said blocks may be eliminated, depending on the desired implementation.

[0067] As should be understood, at block 722, one or more data and / or clock timing alignment operations may be performed, and method 720 may continue to block 724. At block 724, a calibration code may be determined and used to configure the unit driver, and method 720 may continue to block 726. For example, in response to a calibration command, the ZQ calibration circuit (e.g., Figure 6 The ZQ calibration circuit 602 can receive calibration signals (e.g., Figure 2 (DOZQCAL) and through a reference resistor (e.g., Figure 2 The impedance and reference potential of the resistor RZQ) Figure 2 The ZQ calibration circuit (ZQVREF) is used to perform calibration operations (e.g., long calibration operations). Additionally, the ZQ calibration circuit can provide the ZQ calibration code (i.e., the code generated via the calibration operation) to the input / output circuit 262 (see [link to circuit 262]). Figure 2 This is used to configure several circuits based on the ZQ calibration code. More specifically, in response to the ZQ calibration code, the unit driver (e.g., Figure 6 The unit driver 608 has several transistors (e.g., 1, 2, 3, etc.) (i.e., to adjust the output resistance Ron).

[0068] At block 726, in response to a signal transmitted from driver 608 to host 604 (e.g., data read via host 608), it is possible (e.g., via...) Figure 6The host (604) measures the channel performance response (i.e., the channel performance response for the calibration code and associated configuration). For example, the size of the eye of the channel performance response (e.g., height and / or width) can be measured. Additionally, at block 728, the calibration code can be updated (e.g., by increasing or decreasing the calibration code by one (1)), and method 720 can return to block 726. As should be understood, blocks 726 and 728 can be repeated for each of several calibration codes (e.g., a calibration code scan can be performed). More specifically, several driver configurations (e.g., containing 1-N conductive transistors) can be tested for several (e.g., N) calibration codes. After testing each possible calibration code, a test result calibration code (i.e., a code for optimizing signal integrity) can be determined, the difference between the initial calibration code and the test result calibration code can be determined, and at block 730, the difference between the initial calibration code and the test result calibration code (i.e., the shift value) is stored (e.g., stored in...). Figure 6 (In register 616). At block 732, one or more reference voltage training operations can be performed.

[0069] Refer again Figure 7A After the read training operation is completed at block 710, method 700 can continue to block 712, where the memory system is operable (e.g., performing various operations, such as reading, writing, refreshing, etc.).

[0070] Figure 7C A flowchart of an example method 740 for calibrating a memory device. More specifically, method 740 may be used (e.g., during operation of the memory device) to calibrate the memory device. Method 740 may be arranged according to at least one embodiment described in this disclosure. In some embodiments, method 740 may be performed by a device or system, such as Figure 1 The memory system 100, one or more memory devices of the memory system 100, Figure 2 Memory device 200, Figure 3 Memory system 300, Figure 6 Memory system 600, Figure 9 Memory system 900, Figure 10 The electronic system 1000, or another device or system. Although described as discrete blocks, the various blocks may be further divided into additional blocks, combined into fewer blocks, or said blocks may be eliminated, depending on the desired implementation.

[0071] Method 740 may begin at block 742, where a calibration code can be determined, and method 740 may continue to block 744. More specifically, in response to a “short calibration” command (i.e., during operation of the memory device), a calibration operation can be performed and a calibration code can be determined. At block 744, the calibration code can be stored, and method 740 may continue to block 746. For example, the calibration code may be stored in register 612 of the ZQ calibration circuit 602 (see [link to relevant documentation]). Figure 6 ).

[0072] At block 746, the calibration code can be updated based on a predetermined shift value, and method 740 can continue to block 748. For example, it can be based on the value stored in... Figure 7B The calibration code is updated based on the shift value at block 730. As a non-limiting example, if the calibration code is five (5) and the shift value is positive one (+1), the calibration code can be updated to six (6). As another non-limiting example, if the calibration code is five (5) and the shift value is negative three (-3), the calibration code can be updated to two (2).

[0073] At block 748, the updated calibration code can be applied to one or more cell drivers of the memory device's output driver. For example, the updated calibration code can be used to configure... Figure 6 One or more transistors of the unit driver 608.

[0074] Modifications, additions, or omissions may be made to method 740 without departing from the scope of this disclosure. For example, the operations of method 740 may be performed in a different order. Furthermore, the operations and actions outlined are provided only as examples, and some of these operations and actions may be optional, combined into fewer operations and actions, or extended into additional operations and actions without departing from the essence of the disclosed embodiments.

[0075] As mentioned above, signal integrity can vary across memory components (e.g., memory devices) of a memory system. Therefore, according to some embodiments, one or more memory devices (e.g., memory devices of a DIMM) of a memory system can be calibrated according to the various embodiments disclosed herein. More specifically, for example, one or more of memory devices 102-105 can be calibrated (i.e., individually calibrated) (e.g., via different calibration processes) according to the various embodiments disclosed herein (see [link to documentation]). Figure 1 As another example, the memory system 300 can be calibrated (i.e., individually calibrated) according to the various embodiments disclosed herein (see [link to documentation]). Figure 3One or more memory components (e.g., DQ cell 306 and DQS terminals 308 and 310). In these instances, each memory component may or may not utilize the same calibration code (i.e., during operation). In other instances, several memory components (e.g., a memory system) may be calibrated together (i.e., via a single calibration process). In this instance, each memory component may utilize the same calibration code (i.e., during operation).

[0076] As mentioned above, signal integrity can vary across components of a single memory device (e.g., DQ components and / or cell drivers). Therefore, according to various embodiments, one or more output drivers and one or more cell drivers of the memory device can be calibrated (i.e., individually calibrated) (e.g., via different calibration processes) according to the various embodiments disclosed herein. Furthermore, for example, one or more DQ components of the memory device can be calibrated (i.e., individually calibrated) according to the various embodiments disclosed herein. For example, one or more cell drivers 608 (see […]) can be calibrated (i.e., individually calibrated) according to the various embodiments disclosed herein. Figure 6 In these instances, each component (e.g., each cell driver and / or DQ component) may or may not utilize the same calibration code (i.e., during operation). In other instances, several cell drivers and / or DQ components (e.g., memory devices) may be calibrated together (i.e., via a single calibration process). In this instance, each component may utilize the same calibration code (i.e., during operation).

[0077] Figure 8 This is a flowchart of an example method 800 for operating a memory device. Method 800 may be arranged according to at least one embodiment described herein. In some embodiments, method 800 may be performed by a device or system, such as... Figure 1 The memory system 100, one or more memory devices of the memory system 100, Figure 2 Memory device 200, Figure 3 Memory system 300, Figure 6 Memory system 600, Figure 9 Memory system 900, Figure 10 The electronic system 1000, or another device or system. Although described as discrete blocks, the various blocks may be further divided into additional blocks, combined into fewer blocks, or said blocks may be eliminated, depending on the desired implementation.

[0078] Method 800 may begin at block 802, where a first calibration operation may be performed to determine a first impedance calibration code for the memory device, and method 800 may continue to block 804. For example, in response to a long calibration command, the first calibration operation may be performed (e.g., during a first mode of, for example, the power-on mode of the memory device) to determine the first impedance calibration code. But more specifically, for example, in response to a calibration command, the ZQ calibration circuit (e.g., Figure 6 The ZQ calibration circuit 602 can receive calibration signals (e.g., Figure 2 (DOZQCAL) and through a reference resistor (e.g., Figure 2 The impedance and reference potential (e.g., RZQ) of the RZQ) Figure 2 The ZQ calibration circuit (ZQVREF) is used to perform calibration operations (e.g., long calibration operations). Additionally, the ZQ calibration circuit can provide the ZQ calibration code (i.e., the code generated via the calibration operation) to the input / output circuit 262 (see [link to circuit 262]). Figure 2 This is used to configure several circuits based on the ZQ calibration code.

[0079] At block 804, a test operation can be performed to determine a second impedance calibration code for the memory device based on several measured signal integrity responses of the memory device, and method 800 can continue to block 806. For example, it can be (e.g., one by one) (e.g., via...) Figure 6 The host 604 (e.g., during a first mode of the memory device) tests several possible calibration codes to determine a second calibration code, as mentioned above, which may (e.g., during power-on) optimize the signal integrity response of the memory device.

[0080] At block 806, a second calibration operation may be performed to determine a third impedance calibration code for the memory device, and method 800 may continue to block 808. For example, in response to a short calibration command, the second calibration operation may be performed (e.g., during a second mode of operation of the memory device, for example) to determine the third impedance calibration code.

[0081] At block 808, the third impedance calibration code can be updated based on the difference between the first impedance calibration code and the second impedance calibration code. For example, during the second mode of the memory device, it can be based on (e.g., stored in...) Figure 6 The third impedance calibration code is updated by shifting a value in register 616, the shift value indicating the difference between the first and second impedance calibration codes. More specifically, however, it can be updated (e.g., via...) Figure 6 The calculation block 618) adds or subtracts the shift value from the third calibration code to update the third calibration code.

[0082] Modifications, additions, or omissions may be made to method 800 without departing from the scope of this disclosure. For example, the operations of method 800 may be performed in a different order. Furthermore, the operations and actions outlined are provided only as examples, and some of these operations and actions may be optional, combined into fewer operations and actions, or extended into additional operations and actions without departing from the essence of the disclosed embodiments. For example, in various embodiments, method 800 may include (e.g., via...) Figure 6 The logic 614) determines the shift value (i.e., determines the difference between the first impedance calibration code and the second impedance calibration code). Additionally, in various embodiments, method 800 may include (e.g., via...) Figure 6 The register 616 stores the shift value (i.e., stores a value indicating the difference between the first impedance calibration code and the second impedance calibration code). Furthermore, in various embodiments, method 800 may include at least one cell driver configuring the memory device based on the first calibration code, the second calibration code, the third calibration code, or an updated third calibration code.

[0083] A memory system is also disclosed. The memory system may include a plurality of memory devices. Each memory device may include one or more arrays (e.g., memory arrays) and one or more output drivers, as described herein.

[0084] Figure 9 This is a simplified block diagram of a memory system 900 implemented according to one or more embodiments described herein. The memory system 900 includes a plurality of memory devices 902 and a controller 904. For example, one or more memory devices 902 may include... Figure 6 The memory system 600 is at least a portion thereof, and the controller 904 may be and / or include Figure 1 Controller 112 and / or Figure 6 The host 604. Each memory device 902, which may include one or more memory cells, may include one or more output driver circuits, said output driver circuits including one or more cell drivers, as described herein.

[0085] An electronic system is also disclosed. The electronic system may include a memory system, which includes a plurality of memory devices. Figure 10This is a simplified block diagram of an electronic system 1000 implemented according to one or more embodiments described herein. The electronic system 1000 includes at least one input device 1002. The input device 1002 may be a keyboard, mouse, or touchscreen. The electronic system 1000 further includes at least one output device 1004. The output device 1004 may be a monitor, touchscreen, or speaker. The input device 1002 and the output device 1004 are not necessarily separable from each other. The electronic system 1000 further includes a storage device 1006. The input device 1002, output device 1004, and storage device 1006 are coupled to a processor 1008.

[0086] The electronic system 1000 further includes a memory system 1010 coupled to the processor 1008. It may include... Figure 9 The memory system 900 and the memory system 1010 include several memory devices (e.g., Figure 1 (Memory devices 102-105). Electronic system 1000 may include computing, processing, industrial or consumer products. For example, but not limited to, electronic system 1000 may include personal computers or computer hardware components, servers or other network-connected hardware components, handheld devices, tablet computers, electronic notebook computers, cameras, telephones, music players, wireless devices, displays, chipsets, games, vehicles or other known systems.

[0087] According to the various embodiments disclosed herein, and compared to some conventional methods, systems, and apparatuses, memory systems can tune the output impedance of one or more cell drivers without requiring manual adjustment of the output impedance. It should be understood that the apparatuses, systems, and methods disclosed herein can reduce the amount of time and / or resources that might be required to calibrate the output impedance of one or more semiconductor devices in a system. Additionally, as mentioned above, various embodiments allow the output resistance Ron to be adjusted to any suitable value, even values ​​outside the design specifications. Furthermore, according to some embodiments, calibration codes can be updated (e.g., during operation) based on shift values ​​determined via previously performed test operations (e.g., test operations performed during power-on). The shift values ​​can be stored at the memory device, and therefore the memory device can be calibrated based on the shift values ​​without increasing the load on the associated host (e.g., host 604).

[0088] One or more embodiments of this disclosure include an apparatus. The apparatus may include a ZQ calibration circuit comprising: a first register configured to store a first impedance calibration code generated in response to a ZQ calibration command; a second register configured to store a shift value; and a calculation block configured to generate a second impedance calibration code based on a third impedance calibration code and the shift value.

[0089] Some embodiments of this disclosure include a system. The system may include a microelectronic device that may include at least one driver configured in one of several configurations based on selected calibration codes. The microelectronic device may also include logic for determining a difference between a first calibration code and a second calibration code among a plurality of calibration codes. Additionally, the microelectronic device may include one or more registers for storing one or more calibration codes among the plurality of calibration codes and a shift value indicating the difference between the first calibration code and the second calibration code. Furthermore, the microelectronic device may include a computational block for adjusting a third calibration code among the plurality of calibration codes based on the shift value.

[0090] Additional embodiments of this disclosure include an electronic system. The electronic system may include: at least one input device; at least one output device; at least one processor device operatively coupled to the input device and the output device; and at least one memory system operatively coupled to the at least one processor device. The memory system may include a memory device comprising a driver and a circuit system coupled to the driver. The circuit system may be adapted to configure the driver based on a first impedance calibration code generated in response to a first calibration operation. The circuit system may be further adapted to store a second impedance calibration code generated in response to a test operation. Furthermore, the circuit system may be configured to store a third impedance calibration code generated in response to a second calibration operation. The circuit system may also be adapted to configure the driver based on a fourth impedance calibration code generated based on the third impedance calibration code and the difference between the first and second impedance calibration codes.

[0091] Other embodiments of this disclosure include a method. The method may include performing a first calibration operation to determine a first impedance calibration code for a microelectronic device. The method may also include performing a test operation to determine a second impedance calibration code for the microelectronic device based on a plurality of measured signal integrity responses generated via the microelectronic device. Additionally, the method may include performing a second calibration operation to determine a third impedance calibration code for the microelectronic device. Furthermore, the method may include updating the third impedance calibration code based on the difference between the first impedance calibration code and the second impedance calibration code.

[0092] As is customary, the various features illustrated in the drawings may not be drawn to scale. The descriptions presented in this disclosure are not intended to be actual views of any particular device (e.g., apparatus, system, etc.) or method, but are merely idealized representations for describing various embodiments of this disclosure. Therefore, the dimensions of various features may be arbitrarily enlarged or reduced for clarity. Furthermore, some drawings may be simplified for clarity. Consequently, the drawings may not depict all components of a given device (e.g., apparatus) or all operations of a particular method.

[0093] The terms used herein, and especially in the appended claims (e.g., the body of the appended claims), are generally intended to be “open-ended” terms (e.g., the term “including” should be interpreted as “including but not limited to”, the term “having” should be interpreted as “having at least”, the term “includes” should be interpreted as “including but not limited to”, etc.).

[0094] Furthermore, if the intention is to use a specific number of introduced claim statements, then this intention will be explicitly stated in the claims, and without such a statement, this intention does not exist. For example, to aid understanding, the appended claims may contain the introductory phrases “at least one” and “one or more” to introduce claim statements. However, the use of such phrases should not be construed as implying that introducing claim statements with the indefinite article “a” limits any particular claim containing such introduced claim statements to embodiments containing only one such statement, even if the same claim contains the introductory phrases “one or more” or “at least one” and an indefinite article such as “a” (e.g., “a” should be interpreted as meaning “at least one” or “one or more”); the same applies to the use of definite articles to introduce claim statements. As used herein, “and / or” includes any and all combinations of one or more of the associated listed items.

[0095] Furthermore, even when a specific number of the introduced claims are explicitly stated, it should be understood that such a statement should generally be interpreted as referring to at least the number of claims (e.g., the simple statement "two claims" without other modifiers means at least two claims, or two or more claims). Moreover, in cases where conventions such as "at least one of A, B, and C" or "one or more of A, B, and C" are used, such structures are generally intended to include only A, only B, only C, A and B, A and C, B and C, or A, B, and C, etc. For example, the term "and / or" is intended to be interpreted in this manner.

[0096] Furthermore, it should be understood that any transitional words or phrases presenting two or more alternative terms, whether in the description, claims, or drawings, encompass the possibility of including one, any, or both of the stated terms. For example, the phrase "A or B" will be understood to include the possibility of including "A" or "B" or "A and B".

[0097] Furthermore, the use of terms such as "first," "second," and "third" in this document does not necessarily imply a specific order or number of elements. Generally, the terms "first," "second," and "third" are used as general identifiers to distinguish different elements. Where there is no indication that the terms "first," "second," and "third" imply a specific order, these terms should not be construed as implying a specific order. Similarly, where there is no indication that the terms "first," "second," and "third" imply a specific number of elements, these terms should not be construed as implying a specific number of elements.

[0098] The embodiments described above and illustrated in the accompanying drawings do not limit the scope of this disclosure, which is covered by the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of this disclosure. In fact, various modifications to this disclosure will become apparent to those skilled in the art from the description, in addition to the alternative applicable combinations of the described elements shown and described herein. Such modifications and embodiments also fall within the scope of the appended claims and their equivalents.

Claims

1. An apparatus comprising: The ZQ calibration circuit includes: The first register is configured to store the first impedance calibration code generated in response to the ZQ calibration command; A second register is configured to store a shift value that indicates the difference between the first impedance calibration code and the fourth impedance calibration code; as well as A calculation block, configured to generate a second impedance calibration code based on the third impedance calibration code and the shift value, The first impedance calibration code is determined during the power-on mode of the device, and the third impedance calibration code is determined during the operation mode of the device.

2. The apparatus of claim 1, wherein the ZQ calibration circuit includes logic configured to determine the shift value.

3. The apparatus of claim 2, wherein the logic is configured to transmit a signal indicating the shift value to the second register.

4. The apparatus of claim 2, wherein the calculation block is configured to add or subtract the shift value from the third impedance calibration code to generate the second impedance calibration code.

5. The apparatus of claim 1, wherein the fourth impedance calibration code is determined during the power-on mode of the apparatus or during the operating mode of the apparatus.

6. The apparatus of claim 1, wherein the ZQ calibration circuit is adapted to determine and store the shift value.

7. A system comprising Microelectronic devices, comprising: At least one driver that can be configured in one of several configurations based on a selected calibration code; Logic used to determine the difference between the first calibration code and the second calibration code among several calibration codes; One or more registers for storing one or more calibration codes from the plurality of calibration codes and shift values ​​indicating the difference between the first calibration code and the second calibration code; and A calculation block, used to adjust the third calibration code among the plurality of calibration codes based on the shift value. The first calibration code is determined during the power-on period of the microelectronic device, and the third calibration code is determined during the operation of the microelectronic device.

8. The system of claim 7, wherein the one or more registers comprise: A first register, configured to store at least one of the first calibration code and the second calibration code; and A second register is coupled to the logic and configured to store the shift value.

9. The system of claim 7, further comprising a host computer coupled to the microelectronic device and configured to: Several signals are transmitted to the at least one driver to configure the at least one driver according to each of several configurations; Evaluate the signal integrity response for each of the plurality of configurations to select a configuration from the plurality of configurations; and The signal is transmitted to the microelectronic device to store the second calibration code associated with the selected configuration.

10. The system of claim 7, wherein the computation block is configured to add or subtract the shift value from the third calibration code to adjust the third calibration code.

11. The system of claim 7, wherein the second calibration code is determined during the power-on period of the microelectronic device or during the operation of the microelectronic device.

12. The system of claim 7, wherein the first calibration code is determined in response to a first calibration command, and the third calibration code is determined in response to a second calibration command.

13. A system comprising: At least one input device; At least one output device; At least one processor device operatively coupled to the input device and the output device; as well as At least one memory system operatively coupled to the at least one processor device, the memory system comprising: A memory device comprising: drive; and A circuit system coupled to the driver and adapted to: The driver is configured based on a first impedance calibration code generated in response to a first calibration operation; Store the second impedance calibration code generated in response to the test operation; Store the third impedance calibration code generated in response to the second calibration operation; and The driver is configured based on a fourth impedance calibration code, which is generated based on the third impedance calibration code and the difference between the first and second impedance calibration codes. The first impedance calibration code is generated during the power-on period of the memory device, and the third impedance calibration code is generated during the operation of the memory device.

14. The system of claim 13, wherein the circuit system comprises: A first register is configured to store at least one of the first impedance calibration code and the second impedance calibration code; Logic, configured to determine a shift value indicating the difference between the first impedance calibration code and the second impedance calibration code; A second register is configured to store the shift value; as well as A calculation block configured to add or subtract the shift value from the third impedance calibration code to generate the fourth impedance calibration code.

15. The system of claim 13, wherein the second impedance calibration code is generated during the power-on period of the memory device or during the operation of the memory device.

16. A method comprising: A first calibration operation is performed during the power-on of the microelectronic device to determine a first impedance calibration code for the microelectronic device; Perform test operations to determine a second impedance calibration code for the microelectronic device based on several measured signal integrity responses generated via the microelectronic device; A second calibration operation is performed during operation of the microelectronic device to determine a third impedance calibration code for the microelectronic device. as well as The third impedance calibration code is updated based on the difference between the first impedance calibration code and the second impedance calibration code.

17. The method of claim 16, wherein performing the test operation includes performing the test operation during the power-on period of the microelectronic device or during the operation of the microelectronic device.

18. The method of claim 16, further comprising determining the difference between the first impedance calibration code and the second impedance calibration code.

19. The method of claim 16, further comprising configuring at least one unit driver of the microelectronic device based on an updated third impedance calibration code.

Images