A voltage trimming built-in self-test circuit applied to a spin magnetic memory

Abstract

The present invention discloses a voltage trimming built-in self-test circuit applied to a spin magnetic memory. The circuit mainly includes an improved built-in self-test circuit introduced in the peripheral circuit of the memory array and a design of a level conversion circuit with multi-level voltage output. By means of the built-in self-test method, the present invention detects the lowest write voltage value for correctly writing data for each column of memory cells in the memory array. According to the detected required write voltage value, the control signal of the level conversion circuit with multi-level voltage output connected to the subsequent stage is configured accordingly. The level converter with multi-level voltage output can output a series of voltage signals with gradients within a certain range, and the required write voltage is output to the memory array through the level conversion circuit configured with the corresponding control signal in the peripheral circuit of the memory array. The present invention can reduce the average power consumption of the write operation of the memory cells as much as possible on the premise of ensuring the target yield.

Description

Technical Field

[0001] The present invention belongs to the technical field of magnetic memories, and particularly relates to a voltage-tuning built-in self-test circuit applied to a spin magnetic memory. Background Art

[0002] Currently, the most commonly used test method for memories is the Memory Build-in Self-test (MBIST) method. The MBIST circuit targets the memory, automatically generates a test circuit for the memory, and detects certain defects existing in the memory by executing a specific test algorithm.

[0003] Existing technologies generally only test for a specific preset write voltage value. If correct reading and writing cannot be performed at this write voltage, it is determined that the memory is faulty. This method may cause waste of memory resources and write power consumption to a certain extent. Summary of the Invention

[0004] The purpose of the present invention is to provide a voltage-tuning built-in self-test circuit applied to a spin magnetic memory, so as to solve the technical problem of reducing the write power consumption as much as possible while ensuring the yield of the target chip.

[0005] To solve the above technical problems, the specific technical solution of the present invention is as follows:

[0006] A voltage-tuning built-in self-test circuit applied to a spin magnetic memory, which introduces a built-in self-test circuit and a level converter circuit with multi-level voltage output at the periphery of the MRAM;

[0007] The built-in self-test circuit is responsible for testing the process fluctuation degree of each column in the MRAM storage array, and generating a control signal for determining the multi-level output level converter circuit according to the fluctuation situation;

[0008] The multi-level output level converter circuit can output a gradient write voltage value within a certain range according to different configuration situations of the control signal. The output range is from 0 to VDDH, where VDDH is the high level connected to the level converter circuit.

[0009] Further, the built-in self-test circuit can detect the process fluctuation situation of each column in the storage array, and generate the control signal LS[n:0] of the multi-level voltage output level converter circuit accordingly.

[0010] Further, the working process of the built-in self-test circuit includes the following steps:

[0011] When the BIST_en signal is enabled, the MRAM enters the test mode; the test vector generation module generates test vectors, which are divided into two categories: addresses and data, and writes them into the MRAM storage array;

[0012] The previously written data is read out from the MRAM storage array, compared with the expected data through the diagnostic module, and the number of error bits in the corresponding column is calculated;

[0013] The data output from the array is transmitted to the built-in self-test circuit. This data passes through XOR gates and NAND gates to compare the actually written data Output[7:0] with the expected data Data_exp[7:0], and generates an error indication flag signal Fail_flag; once Fail_flag = 1, the FBC error bit count variable increases;

[0014] If the final FBC error bit count variable is higher than the maximum number of error bits allowed under the target yield, it proves that the write voltage of this column is too small, and the control signal LS[n:0] of the level conversion circuit with multi-level output needs to be adjusted to increase the write voltage by one level;

[0015] Retest this column until the target write yield requirement is met.

[0016] Furthermore, the transistor-level circuit of the level converter includes:

[0017] The first PMOS transistor P1, whose gate is connected to the low level VDDL, source is connected to the high level VDDH, and drain is connected to the source of the switching transistor in the equivalent PMOS transistor P5;

[0018] The second PMOS transistor P2, whose gate is connected to the drains of PMOS transistors P3 and P4, source is connected to the high level VDDH, and drain is connected to the source of the switching transistor in the equivalent PMOS transistor P5;

[0019] The third PMOS transistor P3, whose gate is connected to the drains of PMOS transistors P1 and P2, source is connected to the high level VDDH, and drain is connected to the source of the switching transistor in the equivalent PMOS transistor P5;

[0020] The fourth PMOS transistor P4, whose gate is connected to the low level VDDL, source is connected to the high level VDDH, and drain is connected to the source of the switching transistor in the equivalent PMOS transistor P5;

[0021] The fifth PMOS transistor P5 is formed by paralleling circuit branches composed of multiple switching transistors and load transistors. The source of this equivalent PMOS transistor is connected, and the drain is connected to the drain of the NMOS transistor N1;

[0022] The sixth PMOS transistor P6 has its gate shorted to its drain, its source connected to the drain terminals of PMOS transistors P3 and P4, and its drain connected to the drain terminal of NMOS transistor N2;

[0023] The first NMOS transistor N1 has its gate connected to the low level VDDL, its source connected to the drain terminal of NMOS transistor N3, and its drain connected to the drain terminal of the equivalent PMOS transistor P5;

[0024] The second NMOS transistor N2 has its gate connected to the low level VDDL, its source connected to the drain terminal of NMOS transistor N4, and its drain connected to the drain terminal of PMOS transistor P6;

[0025] The third NMOS transistor N3 has its gate connected to the output terminal of inverter INV1, its source grounded, and its drain connected to the source terminal of NMOS transistor N1;

[0026] The fourth NMOS transistor N4 has its gate connected to the output terminal of inverter INV2, its source grounded, and its drain connected to the source terminal of NMOS transistor N2;

[0027] The first inverter INV1 has its input terminal connected to the control signal IN[2^n - 1] and its output terminal connected to the gate of NMOS transistor N3;

[0028] The second inverter INV2 has its input terminal connected to the output terminal of inverter INV1 and its output terminal connected to the gate of NMOS transistor N4.

[0029] Furthermore, the equivalent PMOS transistor P5 is composed of multiple parallel circuit branches, and each circuit branch structure is formed by connecting a switching NMOS transistor in series with a load transistor.

[0030] Furthermore, the gate of the load transistor in the circuit branch structure of the equivalent PMOS transistor P5 is connected to its drain to ensure that the load transistor operates in the saturation region.

[0031] Furthermore, the analytical expression for the output low level is:

[0032]

[0033] Where is the aspect ratio of PMOS transistor P1, is the aspect ratio of PMOS transistor P5, V TP,1 is the threshold voltage of PMOS transistor P1, V TP,5 is the threshold voltage of PMOS transistor P5, VDDL is the low level of the input level conversion circuit module, and VDDH is the high level of the input level conversion circuit module.

[0034] Furthermore, in order to prevent the cross-coupled latch structure from locking the circuit output state, the analytical expression for the size design constraints of the PMOS tube and the NMOS tube is:

[0035]

[0036] in is the width-to-length ratio of the NMOS transistor, is the width-to-length ratio of the PMOS transistor, V TN is the threshold voltage of the NMOS transistor, V TP is the threshold voltage of the PMOS transistor, VDDL is the low level of the input level conversion circuit module, and VDDH is the high level of the input level conversion circuit module.

[0037] The voltage trimming built-in self-test circuit for spin magnetic memory of the present invention has the following advantages:

[0038] 1. The present invention can detect the process fluctuation of each column of storage cells in the storage array through the proposed built-in self-test circuit, and allocate a write voltage that can correctly write data to each column of storage cells by configuring the control signal of the multi-level output level conversion circuit. The built-in self-test circuit with MRAM voltage adjustment proposed by the present invention can reduce the average power consumption of writing operations to the storage cells as much as possible while ensuring the target yield of the chip.

[0039] 2. The multi-level output level conversion circuit introduced by the present invention, wherein the structural design of the equivalent PMOS transistor P5 enables the circuit to output a voltage value with a gradient within a certain range, and the voltage value is determined by the size design of the load transistor in the P5 branch structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A basic structural block diagram of a storage array and peripheral circuits of a voltage trimming built-in self-test circuit for a spin magnetic memory provided by an embodiment of the present invention;

[0041] Figure 2 A diagram showing a signal connection mode between a storage array and a peripheral circuit of a voltage trimming built-in self-test circuit for a spin magnetic memory provided by an embodiment of the present invention;

[0042] Figure 3 A signal connection diagram of a built-in self-test circuit provided by an embodiment of the present invention;

[0043] Figure 4 A transistor-level circuit diagram of a multi-level output level conversion circuit provided by an embodiment of the present invention;

[0044] Figure 5A control signal connection diagram of a multi-level output level conversion circuit provided by an embodiment of the present invention;

[0045] Figure 6 The output result of a multi-level output level conversion circuit provided by an embodiment of the present invention;

[0046] Figure 7 The optimization of the write voltage for each column in the storage array of a voltage trimming built-in self-test circuit applied to a spin magnetic memory provided by an embodiment of the present invention;

[0047] Figure 8 The reduction of the average write power consumption of the storage array of a voltage trimming built-in self-test circuit applied to a spin magnetic memory provided by an embodiment of the present invention. Detailed implementation manners

[0048] In order to better understand the purpose, structure and function of the present invention, the following further describes in detail a voltage trimming built-in self-test circuit applied to a spin magnetic memory of the present invention with reference to the accompanying drawings.

[0049] Obviously, the described embodiments are only certain specific embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope protected by the present application.

[0050] In the following description, many specific details are set forth to facilitate a thorough understanding of the present application, but the present application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar generalizations without departing from the spirit of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0051] Secondly, the present application is described in detail with reference to the schematic diagrams. When detailing the embodiments of the present application, the schematic diagrams are only examples and should not limit the scope of protection of the present application herein. In addition, in actual circuit design, targeted designs for indicators such as transistor size and storage array size should be included.

[0052] Modern integrated circuits increasingly require embedding memories on the semiconductor chip itself. The traditional testing methods for memories are restricted by the testing difficulty and cost, and are no longer acceptable to chip design manufacturers. Currently, the most commonly used testing method for memories is to implement it through the Memory Build-in Self-test (MBIST) method, automatically generating the test circuit for the memory, performing read and write operations on the memory addresses according to the corresponding test algorithm, and completing the testing of the memory. The MBIST method is a testing method that targets the memory and detects certain defects existing in the memory by executing specific test algorithms.

[0053] Existing memory built-in self-test technologies generally only test for a specific preset write voltage value. If correct read and write cannot be performed at this write voltage, it is determined that the memory has a fault. This method may cause waste of memory resources and write power consumption to a certain extent.

[0054] To address the above problems, the embodiments of the present application provide a voltage trimming built-in self-test circuit applied to a spin magnetic memory, which can improve the built-in self-test method, test the process fluctuations of each column in the storage array, and allocate the lowest write voltage that can correctly write data to each column. Therefore, the present invention can minimize the write power consumption on the premise of ensuring the yield of the target chip.

[0055] Reference Figure 1 , is the design block diagram of the storage array and the peripheral circuit module that adopts the voltage trimming built-in self-test circuit applied to the spin magnetic memory proposed by the present invention. The circuit modules related to this invention mainly include the built-in self-test circuit module, the row decoding circuit module, and the write driver circuit module.

[0056] Reference Figure 2 , is the signal connection diagram of the storage array and the peripheral circuit of the magnetic random access memory that applies the voltage trimming built-in self-test circuit applied to the spin magnetic memory provided by the embodiments of the present invention. Optionally, a 64×64 storage array design is adopted, and correspondingly, a 2-bit control signal LS[1:0] needs to be designed for the level conversion circuit with multi-level voltage output. Optionally, the 64×64 MRAM array is divided into 8 partial arrays of 8×64, and 8 level conversion circuits with multi-level voltage output are required to match the write voltage for it.

[0057] In the improved built-in self-test circuit module, for the specific circuit connection situation, reference Figure 3。The working process of the voltage trimming built-in self-test circuit for spin magnetic memory is described as follows: First, when the BIST_en signal is enabled, the MRAM macro cell enters the test mode; at this time, the test vector generation module generates test vectors, which are divided into two categories: address and data, and writes them into the storage array. After that, the previously written data is read out from the storage array, and through the diagnostic module, it is compared with the expected data to calculate the number of error bits in the corresponding column. Second, the data Output[7:0] output by the array is transmitted to the BIST control circuit. Through the XOR gate and NAND gate circuits, the actual written data Output[7:0] is compared with the expected data Data_exp[7:0] to generate an error indication flag signal Fail_flag. Once Fail_flag = 1, the FBC is incremented by one. Finally, if the final FBC > FT, it proves that the write voltage of this column is too small, and the control signal LS[1:0] of the level conversion circuit needs to be adjusted to increase the write voltage by one level. Retest this column until the target write yield requirement is met. Optionally, assuming that the target write error rate is constrained to 10 -2 below, so the fault tolerance parameter of the 64×8 array is set to 5. The test results of the optimization of the write voltage values corresponding to COL0 to COL7 are as Figure 7 , before circuit optimization, the write voltage of the storage array at the target yield needs to reach 0.9V. After optimization, the write voltages of COL1, COL3, and COL4 are reduced to 0.8V, and the write voltages of COL2 and COL7 are reduced to 0.7V. In addition, the reduction of the average write power consumption of the storage cell is as Figure 8 , the average write power consumption is reduced from 5.22 fJ before the built-in self-test circuit of the present invention is introduced to 3.91 fJ, a reduction of about 25.1%.

[0058] The level conversion circuit with multi-level voltage output, as an important module in the write driver circuit, the transistor-level circuit description is as Figure 4As shown. The transistor-level circuit includes: a first PMOS transistor P1, whose gate is connected to the low level VDDL, source is connected to the high level VDDH, and drain is connected to the source terminal of the switching transistor in the equivalent PMOS transistor P5; a second PMOS transistor P2, whose gate is connected to the drain terminals of PMOS transistors P3 and P4, source is connected to the high level VDDH, and drain is connected to the source terminal of the switching transistor in the equivalent PMOS transistor P5; a third PMOS transistor P3, whose gate is connected to the drain terminals of PMOS transistors P1 and P2, source is connected to the high level VDDH, and drain is connected to the source terminal of the switching transistor in the equivalent PMOS transistor P5; a fourth PMOS transistor P4, whose gate is connected to the low level VDDL, source is connected to the high level VDDH, and drain is connected to the source terminal of the switching transistor in the equivalent PMOS transistor P5; a fifth PMOS transistor P5, which is formed by parallel connection of circuit branches composed of multiple switching transistors and load transistors. The source terminal of this equivalent PMOS transistor is connected, and the drain terminal is connected to the drain terminal of the NMOS transistor N1; a sixth PMOS transistor P6, whose gate and drain are short-circuited, source is connected to the drain terminals of PMOS transistors P3 and P4, and drain is connected to the drain terminal of the NMOS transistor N2; a first NMOS transistor N1, whose gate is connected to the low level VDDL, source is connected to the drain terminal of the NMOS transistor N3, and drain is connected to the drain terminal of the equivalent PMOS transistor P5; a second NMOS transistor N2, whose gate is connected to the low level VDDL, source is connected to the drain terminal of the NMOS transistor N4, and drain is connected to the drain terminal of the PMOS transistor P6; a third NMOS transistor N3, whose gate is connected to the output terminal of the inverter INV1, source is grounded, and drain is connected to the source terminal of the NMOS transistor N1; a fourth NMOS transistor N4, whose gate is connected to the output terminal of the inverter INV2, source is grounded, and drain is connected to the source terminal of the NMOS transistor N2; a first inverter INV1, whose input terminal is connected to the control signal IN[2^n - 1], and output terminal is connected to the gate of the NMOS transistor N3; a second inverter INV2, whose input terminal is connected to the output terminal of the inverter INV1, and output terminal is connected to the gate of the NMOS transistor N4. The analytical expression of the output low level of this multi-stage output level conversion circuit is: where and are the aspect ratios of the PMOS transistors P1 and P5 respectively, V TP,1 and V TP,5 are the threshold voltages of the PMOS transistors P1 and P5 respectively, and VDDL and VDDH are the low level and high level of the input level conversion circuit module respectively. To prevent the cross-coupled latch structure from locking the circuit output state, the analytical expression of the size design constraints for the PMOS and NMOS transistors is: where and are the aspect ratios of the NMOS transistor and PMOS transistor respectively, V TN and V TPare the threshold voltages of the NMOS and PMOS transistors respectively, and VDDL and VDDH are the low level and high level of the input level conversion circuit module respectively.

[0059] Reference Figure 4 , the equivalent PMOS transistor P5 is composed of multiple parallel circuit branches, and the structure of each circuit branch is formed by connecting a switching NMOS transistor and a load transistor in series. Optionally, in this embodiment, four-level voltage values are designed for the write voltage output, so the equivalent PMOS transistor P5 is composed of four parallel branch structures.

[0060] Reference Figure 4 , the gate and drain of the load transistor in the circuit branch structure of the equivalent PMOS transistor P5 are connected to ensure that the load transistor operates in the saturation region.

[0061] Reference Figure 5 , which is a control signal connection diagram of a multi-level output level conversion circuit provided by an embodiment of the present invention. Optionally, for a level conversion circuit with four-level voltage value output, the control signals LS[1:0], the low level VDDL, and the ground signal are connected to the decoding circuit, and the gate voltage signals IN[3:0] of the output switching transistors, the low level VDDL, and the high level VDDH are connected to the multi-level output level conversion circuit, and finally the output voltage signal V OUT . Optionally, the voltage output situation of the multi-level output level conversion circuit with four-level voltage value output is shown in reference Figure 6 .

[0062] In summary, the present invention proposes a voltage trimming built-in self-test circuit applied to a spin magnetic memory, which can improve the method of built-in self-test, test the process fluctuations of each column in the storage array, and allocate the lowest write voltage that can correctly write data to each column. The MRAM voltage trimming built-in self-test circuit proposed by the present invention can reduce the write power consumption as much as possible on the premise of ensuring the yield of the target chip.

[0063] It can be understood that the present invention is described through some embodiments. As is known to those skilled in the art, without departing from the spirit and scope of the present invention, various changes or equivalent replacements can be made to these features and embodiments. In addition, under the teaching of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application belong to the scope protected by the present invention.

Claims

1. A voltage trimming built-in self-test circuit applied to a spin magnetic memory, characterized in that This circuit module introduces a built-in self-test circuit and a level converter circuit with multi-level voltage output around the MRAM; The built-in self-test circuit is responsible for testing the process fluctuation degree of each column in the MRAM storage array, and generating a control signal for the level conversion circuit with multi-level output according to the fluctuation situation; The level conversion circuit with multi-level output can output a gradient write voltage value within a certain range according to different configuration situations of the control signal. The output range is from 0 to VDDH, where VDDH is the high level connected to the level conversion circuit; The built-in self-test circuit can detect the process fluctuation situation of each column in the storage array, and accordingly generate the control signal LS[n:0] of the level conversion circuit with multi-level voltage output; The working process of the built-in self-test circuit includes the following steps: When the BIST_en signal is enabled, the MRAM enters the test mode; the test vector generation module generates test vectors, which are divided into two categories: address and data, and writes them into the MRAM storage array; The previously written data is read out from the MRAM storage array, and compared with the expected data through the diagnostic module to calculate the number of error bits in the corresponding column; The data output from the array is transmitted to the built-in self-test circuit. This data passes through an XOR gate and a NAND gate to compare the actually written data Output[7:0] with the expected data Data_exp[7:0], and generate an error indication flag signal Fail_flag; once Fail_flag = 1, the FBC error bit count variable increases; If the final FBC error bit count variable is higher than the maximum number of error bits allowed under the target yield, it proves that the write voltage of this column is too small, and the control signal LS[n:0] of the level conversion circuit with multi-level output needs to be adjusted to increase the write voltage by one level; Retest this column until the target write yield requirement is met.

2. The voltage trimming built-in self-test circuit applied to a spin magnetic memory according to claim 1, wherein The transistor-level circuit of the level converter includes: The first PMOS transistor P1, whose gate is connected to the low level VDDL, source is connected to the high level VDDH, and drain is connected to the source terminal of the switching transistor in the equivalent PMOS transistor P5; The second PMOS transistor P2, whose gate is connected to the drain terminals of PMOS transistors P3 and P4, source is connected to the high level VDDH, and drain is connected to the source terminal of the switching transistor in the equivalent PMOS transistor P5; The third PMOS transistor P3, whose gate is connected to the drain terminals of PMOS transistors P1 and P2, source is connected to the high level VDDH, and drain is connected to the source terminal of the switching transistor in the equivalent PMOS transistor P5; The fourth PMOS transistor P4, whose gate is connected to the low level VDDL, source is connected to the high level VDDH, and drain is connected to the source terminal of the switching transistor in the equivalent PMOS transistor P5; The fifth PMOS transistor P5 is formed by paralleling circuit branches composed of multiple switching transistors and load transistors. The source terminal of this equivalent PMOS transistor is connected, and the drain terminal is connected to the drain terminal of the NMOS transistor N1; The sixth PMOS transistor P6, whose gate and drain are short-circuited, source is connected to the drain terminals of PMOS transistors P3 and P4, and drain is connected to the drain terminal of the NMOS transistor N2; The first NMOS transistor N1 has its gate connected to the low level VDDL, its source connected to the drain terminal of the NMOS transistor N3, and its drain connected to the drain terminal of the equivalent PMOS transistor P5; The second NMOS transistor N2 has its gate connected to the low level VDDL, its source connected to the drain terminal of the NMOS transistor N4, and its drain connected to the drain terminal of the PMOS transistor P6; The third NMOS transistor N3 has its gate connected to the output terminal of the inverter INV1, its source grounded, and its drain connected to the source of the NMOS transistor N1; The fourth NMOS transistor N4 has its gate connected to the output terminal of the inverter INV2, its source grounded, and its drain connected to the source of the NMOS transistor N2; The first inverter INV1 has its input terminal connected to the control signal IN[2^n - 1] and its output terminal connected to the gate of the NMOS transistor N3; The second inverter INV2 has its input terminal connected to the output terminal of the inverter INV1 and its output terminal connected to the gate of the NMOS transistor N4.

3. The voltage trimming built-in self-test circuit applied to a spin magnetic memory according to claim 2, wherein The equivalent PMOS transistor P5 is composed of multiple parallel circuit branches, and the structure of each circuit branch is formed by a switching NMOS transistor in series with a load transistor.

4. The voltage trimming built-in self-test circuit applied to the spin magnetic memory according to claim 3, characterized in that, The gate and the drain of the load transistor in the circuit branch structure of the equivalent PMOS transistor P5 are connected to ensure that the load transistor operates in the saturation region.

5. The voltage trimming built-in self-test circuit applied to a spin magnetic memory according to claim 4, characterized in that The analytical expression for the output low level is: ； wherein is the width-to-length ratio of PMOS transistor P1, is the width-to-length ratio of PMOS transistor P5, is the threshold voltage of PMOS transistor P1, is the threshold voltage of PMOS transistor P5, VDDL is the low level of the input level conversion circuit module, and VDDH is the high level of the input level conversion circuit module.

6. The voltage trimming built-in self-test circuit applied to the spin magnetic memory according to claim 5, characterized in that, To prevent the cross-coupled latch structure from locking the circuit output state, the analytical expression for the size design constraints of the PMOS and NMOS transistors is: ； Among them is the width-to-length ratio of the NMOS transistor, is the width-to-length ratio of the PMOS transistor, is the threshold voltage of the NMOS transistor, is the threshold voltage of the PMOS transistor, VDDL is the low level of the input level conversion circuit module, and VDDH is the high level of the input level conversion circuit module.

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