A method for producing a semiconductor structure with a getter

Abstract

The present invention discloses a method for manufacturing a semiconductor structure using a getter, belonging to the field of semiconductor technology. The method comprises the following steps: S01, annealing in an oxidizing atmosphere; S02, two-stage annealing in an inert atmosphere. The main advantages of the present invention are high oxygen defect adsorption efficiency, simple process, and low cost. The method employed in the present invention can not only be used to reduce the oxygen defect content in silicon-based semiconductor devices and integrated circuits, but can also be applied to reduce the micro-defect content in the substrates of compound semiconductor power devices and integrated circuits.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a method for producing a semiconductor structure with a getter. Background Art

[0002] In the manufacturing process of semiconductor devices, power devices, and large-scale and ultra-large-scale integrated circuits, how to reduce the oxygen content in silicon wafers is the key to improving the reliability and stability of semiconductor devices and integrated circuit applications.

[0003] The commonly used methods for reducing the oxygen content in silicon wafers to form ohmic contacts with silicon semiconductors are as follows:

[0004] 1 An oxygen defect adsorption layer is formed on the back of silicon by chemical etching.

[0005] 2. An oxygen defect adsorption layer is formed on the back of silicon by ion implantation.

[0006] 3. Technology of a method and apparatus for removing impurities from SOI (Silicon on Insulator) wafers manufactured using a controlled cutting process.

[0007] The main disadvantages of the above methods are:

[0008] 1. Poor stability and repeatability;

[0009] 2. Low oxygen adsorption efficiency;

[0010] 3. The process is complex and the cost is high, such as the SOI adsorption layer method. Summary of the Invention

[0011] The present invention aims to improve getter stability to the point where oxygen content in the silicon is not a factor. Experiments have shown that incorporating a low-temperature annealing step of 430-450°C during the process of forming an internal getter alters the oxygen precipitation process during subsequent high-temperature treatment: it significantly accelerates the formation of nucleation centers and actually leads to the formation of a different type of microdefect. Incorporating this annealing step during the process of generating an internal getter allows getter centers to form even when using silicon wafers manufactured using zone melting (i.e., low-oxygen zone melting).

[0012] The present invention discloses a method for manufacturing a semiconductor structure using a getter, comprising the following steps:

[0013] S01, annealing in an oxidizing atmosphere;

[0014] S02, two-stage annealing in an inert atmosphere.

[0015] In some preferred embodiments of the present invention, in S01, annealing is performed at 1120-1250° C. for 2-3 hours (h) in an oxidizing atmosphere.

[0016] In some preferred embodiments of the present invention, in S01, the oxidizing atmosphere is a dry oxygen atmosphere.

[0017] In some preferred embodiments of the present invention, in S01, the oxidizing atmosphere further comprises a chlorine-containing additive, and the active chlorine content is preferably 0.4-1.2% wt of the oxygen content.

[0018] In some preferred embodiments of the present invention, in S02, the two-stage annealing includes annealing at 1000-1050°C or annealing at 1020-1080°C and annealing at 425-455°C; preferably includes annealing at 1000-1050°C for 9-11 hours (h) or annealing at 1020-1080°C for 3-6 hours (h) and annealing at 425-455°C for 1-7 hours (h).

[0019] In some preferred embodiments of the present invention, in S02, the temperature and duration of the two-stage annealing depend on the density of micro defects after the substrate is annealed in an oxidizing environment.

[0020] In some preferred embodiments of the present invention, in S02, the density of micro defects after annealing the substrate in an oxidizing environment is less than 2×10 4 cm -3 When annealing, first anneal at 1000-1050℃ for 9-11 hours (h), then anneal at 425-455℃ for 5-7 hours (h);

[0021] 2×10 4 cm -3 ≤The density of micro defects after annealing the substrate in an oxidizing environment is less than 2×10 6 cm -3 When annealing, first anneal at 1020-1080℃ for 3-6 hours (h), then anneal at 425-455℃ for 5-7 hours (h);

[0022] 2×10 6 cm -3 ≤The density of micro defects after annealing the substrate in an oxidizing environment is less than 2×10 7 cm -3 When annealing, first anneal at 1020-1080℃ for 3-6 hours (h), and then anneal at 425-455℃ for 1-3 hours (h).

[0023] In some preferred embodiments of the present invention, the method further includes the steps of etching and determining the density of the etching pattern after S01.

[0024] In some preferred embodiments of the present invention, in the etching step, the silicon wafer is etched in a composition of 3-5 parts by weight of hydrogen fluoride, 45-50 parts by weight of chromic anhydride, and 45-50 parts by weight of water for 1.2-1.6 hours (h).

[0025] In some preferred embodiments of the present invention, the step of determining the density of the etching pattern is to perform a metallographic examination on the surface of the substrate under an optical microscope and calculate the density of the detected etching pattern.

[0026] Beneficial effects of the present invention:

[0027] Experiments have shown that in a process for forming internal getters, which includes a first annealing step at 1120-1250°C for 2-3 hours in an oxidizing atmosphere, and a second annealing step at 1000-1080°C for 3-11 hours and 425-455°C for 1-7 hours in an inert atmosphere, depending on the density of micro-defects in the semiconductor structure, the addition of a low-temperature annealing step in the 425-455°C range alters the oxygen precipitation process during the subsequent high-temperature treatment, significantly accelerating the formation of nucleation centers and effectively leading to the formation of another type of micro-defects. Incorporating this annealing step into the process for generating internal getters allows the formation of getter centers in the wafer even when using silicon wafers manufactured by zone melting (i.e., low-oxygen zone melting).

[0028] The main advantages of this invention are high oxygen defect adsorption efficiency, a simple process, and low cost. The method employed by this invention can be used not only to reduce oxygen defect content in silicon-based semiconductor devices and integrated circuits, but can also be applied to reduce microdefect content in the substrates of compound semiconductor power devices and integrated circuits. DETAILED DESCRIPTION

[0029] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] Unless otherwise specified, the examples and comparative examples are parallel experiments with the same components, component contents, preparation steps, and preparation parameters.

[0031] Typically, in raw silicon rods, oxygen is present in the excimer Si-O-Si composition. A first high-temperature heat treatment (oxidation at 1120-1250°C) followed by cooling removes some dissolved oxygen from the excimer state and initiates the formation of small oxygen complexes, an effect visible in the etch patterns. The formation of these primary complexes depends on the oxygen content and the growth history of the rod, specifically the presence of precipitation centers during the growth of the ingot. Therefore, selective metallographic monitoring after the first oxidation allows for the assessment of the material's precipitation capacity and the determination of the time required to achieve high-quality getters for a specific rod material after low-temperature annealing at temperatures of 455°C and 1000-1080°C.

[0032] The time range of etching patterns with different densities after the first oxidation was determined by experimental selection. When the density of the getter center is 3×10 9 cm -3 Internal getters are considered qualified when the main defect type in the bulk is a precipitate-dislocation complex with a total size of 0.25-0.55 μm. Such getters can stably withstand subsequent heat treatment without losing their gettering capacity during annealing at 1120°C for 18-22 hours. This time typically exceeds the total high-temperature heat treatment time for many types of devices.

[0033] Compared to the time recommended for etched patterns of different densities after the first oxidation, a reduction in the annealing time at 455°C can lead to a sharp drop in the density of the formed gettering centers or a reduction in the size of the formed oxygen precipitates, which in turn can cause these precipitates to decompose during wafer heat treatment and prevent the gettering effect from being exerted. Compared to the recommended scheme, an increase in the duration of annealing at 455°C and 1000-1080°C can cause dislocations to separate from the gettering centers and appear in the active area of ​​the silicon wafer, reducing the yield of the device crystal. This is especially true when the etched pattern density after the first oxidation is higher than 2×10 4 cm -3 When the internal getter formation is achieved, even a further annealing at 455°C for 30 minutes can lead to the formation of an excessively strong getter and the formation of dislocations on the working plane, which can cause substrate bending. Therefore, at such micro-defect densities after the first oxidation, additional annealing at temperatures of 425-455°C during the process cycle for internal getter formation is generally not recommended.

[0034] At this temperature with low microdefect density, increasing the annealing time to more than 6 hours does not lead to further activation of the precipitation process; on the contrary, an increase in the low-temperature annealing time may lead to a decrease in the density of getter centers. Then, by increasing the low-temperature annealing time to 10-12 hours in the annealing process cycle at 1000-1080 °C, even at very low microdefect densities (less than 2×10 4 cm-3 , i.e., the oxygen content in silicon is very low) high-quality internal getters can also be obtained.

[0035] Increasing the annealing time at a temperature of 1000-1080°C will not ensure the formation of internal getters on materials with low oxygen content without introducing a low temperature annealing at 425-455°C into the process cycle.

[0036] Example 1

[0037] A single crystal silicon wafer with a crystal orientation of (100) was used, and its surface was subjected to chemical mechanical polishing and chemical cleaning. The oxygen concentration of the silicon single crystal wafer was 8.9-9.3×10 17 cm -3 .

[0038] The substrate was preliminarily oxidized in dry oxygen with the addition of gaseous hydrogen chloride (HCl) at 1220°C (the active chlorine content in the oxidizing environment was 1%) for 2 hours, and then etched in a composition with a mass fraction of: 4% hydrogen fluoride, 48% chromic anhydride, and 48% water, for 1 hour of selective etching of the silicon wafer. Before the selective etching, the substrate was briefly etched in a standard polishing etchant to remove surface defects. Then, after the selective etching, the surface of the substrate was metallographically examined under an optical microscope, and the density of the detected etched patterns was calculated. The results showed that the defect density was 8.9×10 6 -1.2×10 7 cm -3 is a common feature. The substrate is then annealed in two stages: the first stage is annealed at a temperature of 1050°C for 5 hours; the second stage is annealed at a temperature of 435°C for 2 hours. In addition, the substrates produced in this way are sent for the study of the quality of the getter. They are etched in a selective etchant and the chip is then inspected under an optical microscope. Electrical testing and physical analysis methods such as capacitance-voltage (CV), scanning electron microscopy (SEM), transmission electron microscopy (TEM), X-ray diffraction (XRD), etc. are used. The presence and width of the depletion region of the semiconductor device, the density of the getter centers within the substrate, the uniformity of distribution and the appearance are recorded. In addition, the working surface of the substrate is inspected to establish the fact that the getter zone, an effective defect-free area, has been formed in the semiconductor substrate.

[0039] Example 2

[0040] A single crystal silicon wafer with a crystal orientation of (100) was used, and its surface was subjected to chemical mechanical polishing and chemical cleaning. The oxygen concentration of the silicon single crystal wafer was 6.1-6.5×10 17 cm -3 .

[0041] The substrate was initially oxidized in dry oxygen with the addition of gaseous hydrogen chloride (HCl) at 1220°C (the active chlorine content in the oxidizing environment was 1%) for 2 hours, and then etched in a composition with a mass fraction of: 4% hydrogen fluoride, 48% chromic anhydride, and 48% water, for 1 hour of selective etching of the silicon wafer. Before the selective etching, the substrate was briefly etched in a standard polishing etchant to remove surface defects. Then, after the selective etching, the surface of the substrate was metallographically examined under an optical microscope, and the density of the detected etched patterns was calculated. The results showed that the defect density ranged from 5.3×10 6 -7.2×10 6 cm -3 . The substrate is then annealed in two stages: the first at 1020°C for 3 hours and the second at 450°C for 5 hours. In addition, the substrates produced in this way are sent for studies on the quality of the getters. They are etched in a selective etchant, and the chips are then inspected under an optical microscope. Electrical tests and physical analysis methods such as capacitance-voltage (CV), scanning electron microscopy (SEM), transmission electron microscopy (TEM), X-ray diffraction (XRD), etc. are used. The presence and width of the depletion region of the semiconductor device, the density of getter centers within the substrate, the distribution uniformity and the appearance are recorded.

[0042] Example 3

[0043] A single crystal silicon wafer with a crystal orientation of (100) was used, and its surface was subjected to chemical mechanical polishing and chemical cleaning. The oxygen concentration of the silicon single crystal wafer was 1.6-1.8×10 16 cm -3 .

[0044] The substrate was initially oxidized in dry oxygen with the addition of gaseous HCl (hydrogen chloride) at 1220°C (the active chlorine content in the oxidizing environment was 1%) for 2 hours, and then etched in a composition with a mass fraction of: 4% hydrogen fluoride, 48% chromic anhydride, and 48% water, for 1 hour of selective etching of the silicon wafer. Before the selective etching, the substrate was briefly etched in a standard polishing etchant to remove surface defects. Then, after the selective etching, the surface of the substrate was metallographically examined under an optical microscope, and the density of the detected etched patterns was calculated. The results showed that the defect density ranged from 1.1×10 4 -1.7×10 4 cm -3. The substrate is then annealed in two stages: the first at 1020°C for 10 hours and the second at 450°C for 7 hours. In addition, the substrates produced in this way are sent for studies on the quality of the getters. They are etched in a selective etchant, and the chips are then inspected under an optical microscope. Electrical tests and physical analysis methods such as capacitance-voltage (CV), scanning electron microscopy (SEM), transmission electron microscopy (TEM), X-ray diffraction (XRD), etc. are used. The presence and width of the depletion region of the semiconductor device, the density of getter centers within the substrate, the uniformity of distribution and the appearance are recorded.

[0045] The experimental results show that the method for manufacturing a getter proposed by the present invention allows the formation of high-quality getter regions within the substrate; the width of the merged zone is 8-30 microns, a large number of precipitation-dislocation centers uniformly distributed throughout the entire volume are observed in the substrate volume, and no defects are recorded in the depletion region of the semiconductor device.

[0046] The method adopted by this invention can not only be used to reduce the oxygen defect content of silicon-based semiconductor devices and integrated circuits, but can also be extended to reduce the micro-defect content of the substrate of compound semiconductor power devices and integrated circuits.

[0047] The preferred specific implementation modes and embodiments of the present invention are described in detail above, but the present invention is not limited to the above implementation modes and embodiments. Various changes can be made within the scope of knowledge possessed by those skilled in the art without departing from the concept of the present invention.

Claims

1. A method for manufacturing a semiconductor structure using a getter, characterized in that The following steps are involved: S01, the substrate is annealed in an oxidizing atmosphere; S02, the substrate is annealed in two stages in an inert atmosphere; In S01, annealing is performed at 1120-1250°C for 2-3 hours (h) in an oxidizing atmosphere; In S02, the two-stage annealing includes first annealing at 1000-1050°C for 9-11 hours (h) or annealing at 1020-1080°C for 3-6 hours (h), and then annealing at 425-455°C for 1-7 hours (h); In S02, the temperature and duration of the two-stage annealing depend on the density of micro defects after the substrate is annealed in an oxidizing environment.

2. The method according to claim 1, characterized in that In S01, the oxidizing atmosphere is a dry oxygen atmosphere.

3. The method according to claim 1, characterized in that In S01, the oxidizing atmosphere further includes a chlorine-containing additive.

4. The method according to claim 3, characterized in that In S01, the active chlorine content is 0.4-1.2%wt of the oxygen content.

5. The method according to claim 1, wherein In S02, the density of micro defects after the substrate is annealed in an oxidizing environment is less than 2×10 4 cm -3 When annealing, first anneal at 1000-1050℃ for 9-11 hours (h), then anneal at 425-455℃ for 5-7 hours (h); 2×10 4 cm -3 ≤The density of micro defects after annealing the substrate in an oxidizing environment is less than 2×10 6 cm -3 When annealing, first anneal at 1020-1080℃ for 3-6 hours (h), then anneal at 425-455℃ for 5-7 hours (h); 2×10 6 cm -3 ≤The density of micro defects after annealing the substrate in an oxidizing environment is less than 2×10 7 cm -3 When annealing, first anneal at 1020-1080℃ for 3-6 hours (h), then anneal at 425-455℃ for 1-3 hours (h).

6. The method according to claim 1, characterized in that The method further includes the steps of etching after S01 and before S02 and determining the density of the etching pattern.

7. The method according to claim 6, characterized in that In the etching step, the silicon wafer is etched in a composition of 3-5 parts by weight of hydrogen fluoride, 45-50 parts by weight of chromic anhydride, and 45-50 parts by weight of water for 1.2-1.6 hours (h).

8. The method according to claim 6, characterized in that The step of determining the density of the etching pattern is to perform a metallographic inspection on the surface of the substrate under an optical microscope and calculate the density of the detected etching pattern.